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MC100E111FNR2
5V ECL 1:9 Differential Clock Driver
MC10E111, MC100E111
5V�ECL 1:9 Differential
Clock Driver
The MC10E/100E111 is a low skew 1-to-9 differential driver,
designed with clock distribution in mind. It accepts one signal input,
which can be either differential or else single-ended if the VBB output
is used. The signal is fanned out to 9 identical differential outputs. An
enable input is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q outputs HIGH.
The device is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate to gate skew within-device, and empirical modeling is used to
determine process control limits that ensure consistent tpd
distributions from lot to lot. The net result is a dependable, guaranteed
low skew device.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10 – 20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10 – 20 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 �F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation. Guaranteed Skew Spec Differential Design VBB Output PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V Internal Input 50 K� Pulldown Resistors ESD Protection: Human Body Model; > 3 kV Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34 Transistor Count = 178 devices
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
PLCC−28
FN SUFFIX
CASE 776http://
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
