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MAXQ3210-MAXQ3210+
Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
General DescriptionThe MAXQ3210 microcontroller is a low-power, 16-bit
RISC device that incorporates a driver for a high-output
piezoelectric horn/transducer, an analog comparator,
and a high-current I/O pin that directly drives an LED.
The device is uniquely suited for cost-conscious appli-
cations such as chemical detectors, alarm systems,
and white goods, but can be used in any application
that requires high-performance and low-power opera-
tion. The high-performance 16-bit RISC core and 8-bit
accumulators are complemented by standard ameni-
ties such as timers and digital I/O. The power con-
sumption per MIPS ratio is among the best in the 16-bit
microcontroller industry.
The MAXQ3210 is powered directly from a 6V to 9.5V
source, such as a battery, but an internal voltage regu-
lator operates the core at 5V. The microcontroller also
provides a flag if the input voltage supply falls below
the low-batttery detection threshold (VBF), which can be
used to signal a low-voltage condition of the 9V battery.
The MAXQ3212 is a general-purpose version of the
MAXQ3210 that is powered directly from an external
5.0V supply.
A 1kWord EEPROM program memory stores customer
application code and software algorithms. Software is
programmable in-system by the ROM-based boot-
loader and also in-application programmable under
user software control. The device provides 64 bytes of
volatile SRAM and 128 bytes of EEPROM in the data
memory space. Contact Dallas Semiconductor con-
cerning the availability of ROM-based devices for high-
volume, low-cost applications.
FeaturesHigh-Performance, Low-Power, 16-Bit RISC CoreDC to 3.58MHz Operation, Approaching 1MIPS
per MHz
Low-Cost Operation from “Colorburst” Crystal or RC
Oscillator
6V to 9.5V External Voltage Supply Operates from
Single 9V Battery
5.0V Nominal Internal Operation
Up to 15 General-Purpose I/O Pins
33 Instructions, Most Single-Cycle
Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
Two Loop Counters
4-Level Hardware Stack
16-Bit Instruction Word, 16-Bit Data Bus
16 x 8-Bit Accumulators
JTAG Debug/Visibility Port
Program and Data Memory1kWord EEPROM Program Memory, Mask ROM for
High-Volume Applications
128 Bytes EEPROM Data Memory
60,000 EEPROM Write/Erase Cycles
64 Bytes SRAM Data Memory
In-System Programming
Peripheral FeaturesPiezoelectric Horn Driver
16-Bit Programmable Timer/Counter with Prescaler
High-Current I/O Pin Suitable for LED Drive
Programmable Watchdog Timer
Selectable Power-Fail Reset
Power-On Reset (POR)
Wake-Up Timer
Internal 8kHz Ring Oscillator
Flexible Programming InterfaceIntegrated Bootloader
In-System/In-Application Programming of EEPROM
Through JTAG
Ultra-Low-Power Consumption< 6mA at 3.58MHz
5.5µA Standby Current (typ)
Low-Power Divide-by-256 Mode
Analog FeaturesAnalog Comparator Uses Internal or External Voltage
Reference
+2.5V Reference Output Available
On-Chip Voltage Regulator Supports Up to 9.5V as
Power Supply
Low-Battery Detection
5V Regulated Output Available, Up to 50mA
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and ComparatorRev 1; 5/06
EVALUATION KIT
AVAILABLE
ApplicationsGas and Chemical
Sensors
Security Alarm Systems
Environmental Systems
Battery-Powered and
Portable Devices
Electrochemical and
Optical Sensors
Home Appliances
Thermostats/Humidity
Sensors
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
Note:Some revisions of this device may incorporate deviations
from published specifications known as errata. Multiple revisions
of any device may be simultaneously available through various
sales channels. For information about device errata, go to:
Typical Operating Circuits, Pin Configuration, and Ordering
Information appear at end of data sheet.
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= VDD(MIN)to VDD(MAX), CREGOUT= 10µF + 0.1µF, CVDD= 1µF, TA= -40°C to +85°C. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on Any Digital I/O Pin
Relative to Ground...................................-0.5V to (VDDINT+ 0.5V)
Voltage Range on Any Analog I/O Pin
Relative to Ground..............................-0.5V to (VDDINT+ 0.5V)
Voltage Range on VDDRelative to Ground.........-0.5V to +10.5V
Voltage Range on FEED Relative to Ground..........-0.5V to +20V
Continuous Output Current (any single I/O pin).................25mA
Continuous Output Current (all I/O pins combined)...........25mA
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature.......................................See IPC/JEDEC
J-STD-020 Specification
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply VoltageVDD6.09.09.5V
Internal Regulated Supply
VoltageVDDINT4.55.05.5V
Voltage Regulator OutputVREGOUTMaximum ISOURCE = 50mA4.55.05.5V
0°C to +85°C7.07.51Low-Battery Detection ThresholdVBF-40°C6.97.6V
Power-Fail ResetVRST4.154.6V
IDD1/1 mode (Note 2)
sysclk = fHFXIN6.49.0mA
IDD2/2 mode (Note 2)
sysclk = fHFXIN / 24.06.0mA
IDD3/4 mode (Note 2)
sysclk = fHFXIN / 42.94.5mA
IDD4/8 mode (Note 2)
sysclk = fHFXIN / 82.33.5mA
IDD5PMM1 mode (Note 2)
sysclk = fHFXIN / 2561.73.0mA
Active Current
IDD68kHz ring mode (Note 2)0.61.2mA
ISTOP1Brownout detector off, wake-up timer on,
TA = +50°C (Note 3), VDD = 9V7.533.0
ISTOP2Brownout detector off, wake-up timer on,
TA = +25°C, VDD = 9V5.513Stop-Mode Current
ISTOP3Brownout detector on, wake-up timer on,
TA = +25°C, VDD = 9V5180
RESET PullupRRSTVRST = 0.4V, VREGOUT = 5.5V102150250kΩ
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
ELECTRICAL CHARACTERISTICS (continued)(VDD= VDD(MIN)to VDD(MAX), CREGOUT= 10µF + 0.1µF, CVDD= 1µF, TA= -40°C to +85°C. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL VOLTAGE REFERENCEVoltage Reference OutputVREFOISOURCE = 50µA max,
ISINK = 50µA max2.442.52.56V
Regulated Voltage Settling TimetREFOTur n on to 0.1% of fi nal V R E F O val ue ( N ote 3) 1.2ms
Input Common-Mode VoltageVREFIInput0VDDINT
- 1.5V
Input CurrentIREFIInput1nA
PIEZOELECTRIC HORN DRIVERInput High Voltage: FEEDVIH20.85 x
VDDV
Input Low Voltage: FEEDVIL20.15 x
VDDV
Input Leakage: FEEDIIL1FEED = 0 and 18V, VDD = 9V, typical at
feed = 18V-50+9+50µA
Output High Voltage: HORNS,
HORNBVOH2VDD = 9V, TA = +25°C, ISOURCE = 16mAVDD -
VDD -
0.34V
Output Low Voltage: HORNS,
HORNBVOL2VDD = 9V, TA = +25°C, ISINK = 16mA0.360.5V
ANALOG VOLTAGE COMPARATORInput Offset VoltageVOS-11+11mV
Input Common-Mode VoltageVCMR0VDDINT
- 1.5V
Common-Mode Rejection RatioCMRR(Note 3)55dB
Response Time
fHFIN = 3.58MHz, comparator on,
comparator reference at (VDDINT - 1.5) / 2
while CMPI transitions from GND to (VDDINT
- 1.5) in approximately 2ns
0.14 +
tCLCL
0.6 +
tCLCLµs
Comparator Mode Change to
Output ValidfHFIN = 3.58MHz, ΔV=20mV0.81.6µs
DC Input-Leakage CurrentTA = +25°C-50+50nA
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
ELECTRICAL CHARACTERISTICS (continued)(VDD= VDD(MIN)to VDD(MAX), CREGOUT= 10µF + 0.1µF, CVDD= 1µF, TA= -40°C to +85°C. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL I/O AND OSCILLATORInput High Voltage:
Px.x and HFXINVIHXTRC = 0/10.85 x
VDDINTV
Input Low Voltage:
Px.x and HFXINVILXTRC = 0/10.15 x
VDDINTV
Output High Voltage: Px.xVOHISOURCE = 4mA0.85 x
VDDINTV
Output Low Voltage: Px.x
(except P0.7)VOLISINK = 4mA0.4V
Output Low Voltage: P0.7VOL1ISINK = 10mA0.4V
Input Low Current (All Ports)ILInput mode with weak pullup disabled-1+1µA
Input Low Current (All Ports)ILInput mode with weak pullup active,
VIL = 0.4V, VDDINT = 5.5V-31-50µA
CLOCK SOURCESExternal crystal1.003.58External-Clock FrequencyfHFINExternal oscillator03.58MHz
Internal Ring
OscillatorfRO8kHz
JTAG PROGRAMMINGTCK FrequencyfTCK
JTAG programming (Note 3). Sysclk is a
function of fHFXIN and the clock divisor; see
IDDx parameters abovesysclk /MHz
MEMORY CHARACTERISTICS (Note 3)θJA = +85°C15,000CyclesEEPROM Write/Erase Cycles
θJA = +25°C60,000Cycles
EEPROM Data Retention10Years
Note 1:Specifications to -40°C are guaranteed by design and are not production tested.
Note 2:Measured on the VDDpin with VDD= 9.5V, fHFXIN = 3.58MHz, program EEPROM contains checkerboard, and not in reset.
Note 3:Specification guaranteed by design but not production tested.
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
DIGITAL SUPPLY CURRENT
vs. CLOCK FREQUENCYMAXQ3210 toc01
fHFXIN (MHz)
IDD1
(mA)21
VDD = +9.0V
CLOCK SOURCE DRIVE ON HFXIN
TA = -40°C
TA = +85°C
P0/P1 HIGH OUTPUT VOLTAGE
vs. SOURCE CURRENTMAXQ3210 toc02
VOH (V)
IOH
(mA)321
TA = -40°C
TA = +85°C
TA = +25°C
VDD = +9.0V
fHFXIN = 3.58MHz
RC VALUE vs. OPERATING FREQUENCYMAXQ3210 toc03
R (kΩ)
C (pF)
OSC2 PIN (kHz)49.9100
ANALOG COMPARATOR DELAY
MAXQ3210 toc04
50ns/div
CMPI5V/div
5V/divCMPO
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
Pin Description
PINNAMEFUNCTIONGND
GroundVREF/P0.4
Vo lt a g e R e f e r e n c e In p u t / O u t p u t or G e n e r a l- Pu r p o s e , D i g i t a l I/O , Ty p e D Po r t . Thi s p i n functi ons as ei ther the
outp ut of the i nter nal vol tag e r efer ence or as a b i d i r ecti onal I/O . Thi s p i n can al so b e d r i ven w i th an exter nal
vol tag e to p r ovi d e an op ti onal vol tag e r efer ence. The p i n d efaul ts to a d i g i tal i np ut w i th a w eak p ul l up after a r eset.CMP0/P0.3
Analog Voltage Comparator Output or General-Purpose, Digital I/O, Type D Port. This pin functions as eitherthe output of the analog voltage comparator or as a bidirectional I/O. The pin defaults to a digital input with a
weak pullup after a reset.T2P/P0.2
Timer 2 Input/Output or General-Purpose, Digital I/O, Type D Port. This pin functions as either the input oroutput of Timer 2 or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset.T2PB/P0.1
Secondary Timer 2 Input/Output or General-Purpose, Digital I/O, Type D Port. This pin functions as either thesecondary output of Timer 2 or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a
reset.P0.0
General-Purpose, Digital I/O, Type D Port. This pin functions as a bidirectional I/O, and defaults to a digitalinput with a weak pullup after a reset.P1.6
General-Purpose, Digital I/O, Type D Port. This pin functions as a bidirectional I/O, and defaults to a digitalinput with a weak pullup after a reset.P1.5
General-Purpose, Digital I/O, Type D Port. This pin functions as a bidirectional I/O, and defaults to a digitalinput with a weak pullup after a reset.TD O/P 1.4
D e b u g Po r t Sig n a l T D O o r G e n e r a l - Pu r p o s e , D i g i t a l I/O , T y p e D Po r t . Thi s p i n functi ons as ei ther the TD O
si g nal of the d eb ug p or t or as a b i d i r ecti onal I/O. The p i n d efaul ts to a d i g i tal i np ut w i th a w eak p ul l up after a r eset.TCK/P1.3
D e b u g Po r t Sig n a l T C K o r G e n e r a l- Pu r p o s e , D i g it a l I/ O , Ty p e D Po r t . Thi s p i n functi ons as ei ther the TC K
si g nal of the d eb ug p or t or as a b i d i r ecti onal I/O . The p i n d efaul ts to a d i g i tal i np ut w i th a w eak p ul l up after a r eset.HFXIN
Oscillator Input. Connect an external crystal or resonator between HFXIN and HFXOUT for system clockgeneration. When using a crystal, a load capacitor of approximately 22pF must be connected between this pin
and ground. Alternatively, HFXIN is the input for an external clock source when HFXOUT is floating.HFXOUT
s c i l l a t o r O u t p u t . C onnect an exter nal cr ystal or r esonator b etw een H FX IN and H FX O U T as the system cl ock.hen usi ng a cr ystal , a l oad cap aci tor of ap p r oxi m atel y 22p F m ust b e connected b etw een thi s p i n and g r ound .
Al ter nati vel y, fl oat H FX O U T w hen an exter nal hi g h- fr eq uency cl ock sour ce i s connected to the H FX IN p i n.
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
Pin Description (continued)
PINNAMEFUNCTIONFEED
Piezoelectric Horn Driver, Feedback. This input is connected to the feedback electrode of the horn. If FEED isnot used, it should be grounded.HORNB
Piezoelectric Horn Driver, Horn Brass. This output pin is connected to the piezo metal support electrode of thehorn.GNDHORN
Piezoelectric Horn Driver, Ground. This pin should be connected to GND, the same ground as pin 1. There isno special isolation required for this pin.HORNS
Piezoelectric Horn Driver, Horn Silver. This output pin is connected to the ceramic electrode and provides thecomplementary output to HORNB when the horn output is enabled.VDD
Digital Power. This pin should be connected to a bypass capacitor to ground.REGOUT
Voltage Regulator Output. This pin provides the regulated output of the internal voltage regulator. This pinrequires sufficient bypass capacitance, preferrably a parallel combination of 10µF and 0.1µF capacitors
between this pin and ground.TMS/P1.2
D e b u g Po r t Sig n a l T M S o r G e n e r a l- Pu r p o s e , D i g it a l I/ O , Ty p e D Po r t . Thi s p i n functi ons as ei ther the TM S
si g nal of the d eb ug p or t or as a b i d i r ecti onal I/O . The p i n d efaul ts to a d i g i tal i np ut w i th a w eak p ul l up after a r eset.RESET/P1.1
Active-Low Reset Input or General-Purpose, Digital I/O, Type D Port. This pin defaults to the reset inputmode of operation following a POR. The reset input mode can be deactivated and the digital I/O mode enabled
by programming the RSTD bit to 1.TDI/P1.0
D e b u g Po r t Sig n a l T D I o r G e n e r a l- Pu r p o s e , D i g it a l I/ O , Ty p e D Po r t . Thi s p i n functi ons as ei ther the TD I si g nal
of the d eb ug p or t or as a b i d i r ecti onal I/O . The p i n d efaul ts to a d i g i tal i np ut w i th a w eak p ul l up after a r eset.LED/P0.7
High-Current (Sink) Driver Output or General-Purpose, Digital I/O, Type D Port. This pin functions with ahigh-current pulldown to drive a device such as an LED or as a bidirectional I/O. The pin defaults to a digital
input with a weak pullup after a reset.INT/P0.6
External Edge-Selectable Interrupt or General-Purpose, Digital I/O, Type D Port. This pin functions as eitheran external edge-selectable interrupt or as a bidirectional I/O. The pin defaults to a digital input with a weak
pullup after a reset.CMPI/P0.5
Analog Voltage Comparator Input or General-Purpose, Digital I/O, Type D Port. This pin functions as eitherthe input to the analog voltage comparator or as a bidirectional I/O. The pin defaults to a digital input with a weak
pullup after a reset.
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
Detailed DescriptionThe following is an introduction to the primary features
of the microcontroller. More detailed descriptions of the
device features can be found in the data sheets, errata
sheets, and user’s guides described later in the
Additional Documentationsection.
MAXQ Core ArchitectureThe MAXQ3210 is a low-cost, high-performance,
CMOS, fully static, 16-bit RISC microcontroller with
EEPROM and an integrated piezoelectric horn driver
and analog comparator. It is structured on a highly
advanced, 8-bit accumulator-based, 16-bit RISC archi-
tecture. Fetch and execution operations are completed
in one cycle without pipelining, because the instruction
contains both the op code and data. The result is a
streamlined 3.58 million instructions-per-second (MIPS)
microcontroller.
A 4-level hardware stack, enabling fast subroutine call-
ing and task switching, supports the highly efficient
core. Data can be quickly and efficiently manipulated
with three internal data pointers. Multiple data pointers
allow more than one function to access data memory
without having to save and restore data pointers each
time. The data pointers can automatically increment or
decrement before or after an operation, eliminating the
need for software intervention. As a result, the applica-
tion speed is greatly increased.
Instruction SetThe instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular, so that
new devices and modules can often reuse code devel-
oped for existing products.
The architecture is transport-triggered. This means that
writes or reads from certain register locations can trig-
ger other associated operations. These operations form
the basis for the higher-level instructions defined by the
assembler, such as ADDC, OR, JUMP, etc. The op
codes are actually implemented as MOVE instructions
between certain register locations, while the assembler
handles the encoding, which need not be a concern to
the programmer.
The 16-bit instruction word is designed for efficient exe-
cution. Bit 15 indicates the format for the source field of
the instruction. Bits 0 to 7 of the instruction represent the
source for the transfer. Depending on the value of the
format field, this can either be an immediate value or a
source register. If this field represents a register, the
lower four bits contain the module specifier and the
upper four bits contain the register index in that module.
Bits 8 to 14 represent the destination for the transfer.
This value always represents a destination register,
with the lower four bits containing the module specifier
Functional Diagram1kWORD EEPROM
(PROGRAM)
128B EEPROM
(DATA)
MAXQ10 RISC CORE
(16 x 8-BIT ACCUMULATORS)
2kWORD UTILITY ROM
WATCHDOG
TIMERS
POWER REDUCTION/
CLOCK GENERATION
PORJTAG
64B SRAM
(DATA)
PIEZOELECTRIC
HORN DRIVER
COMPARATOR16-BIT TIMER/COUNTER
WITH PRESCALER
GPIO
HIGH-CURRENT
LED DRIVER
EXTERNAL CRYSTAL/
EXTERNAL OSCILLATOR/
EXTERNAL RC OR RESONATOR
VOLTAGE
REGULATOR5V
MAXQ3210
TMS, TDI,
TDO, TCK
and the upper three bits containing the register
subindex within that module. Any time that it is neces-
sary to directly select one of the upper 24 index loca-
tions in a destination module, the prefix register PFX is
needed to supply the extra destination bits. This prefix
register write is inserted automatically by the assembler
and requires only one additional execution cycle.
Memory OrganizationThe device incorporates several memory areas:2kWords of utility ROM1kWords of EEPROM for program storage128bytes of EEPROM for data storage64bytes of SRAM for storage of temporary variables 4-level stack memory for storage of program return
addresses and general-purpose use
The memory is arranged by default in a Harvard archi-
tecture, with separate address spaces for program and
data memory. A special pseudo-Von Neumann memory
mode allows data memory to be mapped into program
space, permitting code execution from data memory.
This places the utility ROM, code, and data memory
into a single contiguous memory map. This is useful for
applications that require dynamic program modification
or unique memory configurations. In addition, another
mode allows program memory to be mapped into data
space, permitting code constants to be accessed as
data memory.
The incorporation of EEPROM for program storage allows
the devices to be reprogrammed, eliminating the expense
of throwingaway one-time programmable devices during
development and field upgrades. EEPROM can be pass-
word protected with a 16-word key, denying access to
program memory by unauthorized individuals.
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator1k x 16
PROGRAM MEMORY
PROGRAM
SPACE
DATA SPACE
(BYTE MODE)
DATA SPACE
(WORD MODE)0000h
03FFh
2k x 16
UTILITY ROM
87FFh
64 x 16
EEPROMA020h
8000h
A05Fh
4k x 8
UTILITY ROM
8FFFh
8000h
0040h
00BFh
2k x 16
UTILITY ROM
87FFh
8000h
32 x 16
SRAMA000h
A01Fh
128 x 8 EEPROM
0000h
003Fh64 x 8 SRAM
0020h
005Fh64 x 16 EEPROM
0000h
001Fh32 x 16 SRAM
EXECUTING FROM
Figure 1. Memory Map
MAXQ3210
Stack MemoryA 16-bit-wide internal stack provides storage for pro-
gram return addresses and general-purpose use. The
stack is used automatically by the processor when the
CALL, RET, and RETI instructions are executed and
interrupts serviced. The PUSH, POP, and POPI instruc-
tions can also be used explicitly to store and retrieve
data to/from the stack. For the MAXQ3210, the stack is
four levels deep.
On reset, the stack pointer, SP, initializes to the top of
the stack (03h). The CALL, PUSH, and interrupt-vector-
ing operations increment SP, then store a value at the
stack location pointed to by SP. The RET, RETI, POP,
and POPI operations retrieve the value at the stack
location pointed to by SP, and then decrement SP.
Utility ROMThe utility ROM is a block of internal memory that starts
at address 8000h. The utility ROM consists of subrou-
tines that can be called from application software.
These include:In-system programming (bootloader) over JTAG
interfaceIn-circuit debug routinesTest routines (internal memory tests, memory loader,
etc.)User-callable routines for in-application EEPROM
programming and fast table lookup
Routines within the utility ROM are user-accessible and
can be called as subroutines by the application soft-
ware. More information on the utility ROM contents is
contained in the user’s guide for this device.
Some applications require protection against unautho-
rized viewing of program code memory. For these
applications, access to in-system programming or in-
circuit debugging functions is prohibited until a pass-
word has been supplied. The password is defined as
the 16 words of physical program memory at address-
es x0010h to x001Fh.
A single Password Lock (PWL) bit is implemented in
the SC register. When the PWL is set to one (power-on
reset default), the password is required to access the
utility ROM, including in-circuit debug and in-system
programming routines that allow reading or writing of
internal memory. When PWL is cleared to zero, these
utilities are fully accessible without the password. The
password is automatically set to all zeros following a
mass erase. An additional Code Lock bit set from the
bootloader prevents any access to the device, even
through the password. The device must be erased by
the mass erase operation to clear the Code Lock bit
before the device can be reprogrammed.
ProgrammingThe microcontroller’s EEPROM can be programmed by
two different methods: in-system programming and in-
application programming. Both methods afford great
flexibility in system design as well as reduce the life-
cycle cost of the embedded system. In-system pro-
gramming can be password protected to prevent
unauthorized access to code memory.
In-System ProgrammingAn internal bootloader allows the device to be reloaded
over a simple JTAG interface. As a result, system soft-
ware can be upgraded in-system, eliminating the need
for a costly hardware retrofit when software updates are
required. Remote software uploads are possible that
enable physically inaccessible applications to be fre-
quently updated. The interface hardware can be a
JTAG connection to another microcontroller, or a con-
nection to a PC serial port using a serial to JTAG con-
verter such as the MAXQJTAG-001, available from
Dallas Semiconductor. If in-system programmability is
not required, a commercial gang programmer can be
used for mass programming.
Activating the JTAG interface and sending the system
programming instruction invokes the bootloader.
Setting the SPE bit to 1 during reset through the JTAG
interface executes the bootloader-mode program that
resides in the utility ROM. When programming is com-
plete, the bootloader can clear the SPE bit and reset
the device, allowing the device to bypass the utility
ROM and begin execution of the application software.
Optionally, the bootloader can be invoked by the appli-
cation code.
The following bootloader functions are supported:
•LoadDumpCRCVerifyErase
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
In-Application Programming:The in-application programming feature allows the
microcontroller to modify its own program memory from
its application software. This allows on-the-fly software
updates in mission-critical applications that cannot
afford downtime. Alternatively, it allows the application
to develop custom loader software that can operate
under the control of the application software. The utility
ROM contains user-accessible programming functions
that erase and program memory. These functions are
described in detail in the user’s guide for this device.
Register SetMost functions of the device are controlled by sets of
registers. These registers provide a working space for
memory operations as well as configuring and address-
ing peripheral registers on the device. Registers are
divided into two major types: system registers and
peripheral registers. The common register set, also
known as the system registers, includes the ALU, accu-
mulator registers, data pointers, interrupt vectors and
control, and stack pointer. The peripheral registers
define additional functionality that may be included by
different products based on the MAXQ architecture.
This functionality is broken up into discrete modules so
that only the features required for a given product need
to be included. The following tables show the
MAXQ3210 register set. Note that the accumulators are
8 bits wide for this device.
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
Table 1. System Register Map
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a registeris 16 bits wide. Registers in module AP are bit addressable.
MODULE NAME (BASE SPECIFIER)REGISTER
INDEXAP (8h)A (9h)PFX (Bh)IP (Ch)SP (Dh)DPC (Eh)DP (Fh)0xhAPA[0]
PFX[0]IP———
1xhAPCA[1]
PFX[1]—
SP——
2xh—A[2]
PFX[2]—
IV——
3xh—A[3]
PFX[3]——Offs
DP04xhPSFA[4]
PFX[4]——
DPC—
5xhICA[5]
PFX[5]——
GR—
6xhIMRA[6]
PFX[6]—
LC0GRL—
7xh—A[7]
PFX[7]—
LC1BPDP18xhSCA[8]———
GRS—
9xh—A[9]———GRH—
Axh—A[10]———
GRXL—
BxhIIRA[11]———
BP [offs]—
Cxh—A[12]—————
Dxh—A[13]—————
ExhCKCNA[14]—————
FxhWDCNA[15]—————
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
Table 2. System Register Bit Functions
REGISTERREGISTER BIT14131211109876543210————AP (4 bits)
APCCLRIDS———MOD2MOD1MOD0
PSFZS—GPF1GPF0OVCE——CGDS———INSIGE
IMRIMS—————IM1IM0TAP————RODPWL—
IIRIIS—————II1II0
CKCNXT/RCRGSLRGMDSTOPSWBPMMECD1CD0
WDCNPOREWDI——WDIFWTRFEWTRWT
A[n]
(0..15)A[n] (8 bits)
PFXPFX (16 bits)IP (16 bits)——————————————SP (2 bits)IV (16 bits)
LC[0]LC[0] (16 bits)
LC[1]LC[1] (16 bits)
OffsOffs (8 bits)
DPC———————————WBS2WBS1WBS0SDPS1SDPS0GR.15GR.14GR.13GR.12GR.11GR.10GR.9GR.8GR.7GR.6GR.5GR.4GR.3GR.2GR.1GR.0
GRLGR.7GR.6GR.5GR.4GR.3GR.2GR.1GR.0BP (16 bits)
GRSGR.7GR.6GR.5GR.4GR.3GR.2GR.1GR.0GR.15GR.14GR.13GR.12GR.11GR.10GR.9GR.8
GRHGR.15GR.14GR.13GR.12GR.11GR.10GR.9GR.8
GRXLGR.7GR.7GR.7GR.7GR.7GR.7GR.7GR.7GR.7GR.6GR.5GR.4GR.3GR.2GR.1GR.0
BP[offs]BP[offs] (16 bits)
DP[0]DP[0] (16 bits)
DP[1]DP[1] (16 bits)
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
Table 3. System Register Bit Reset Values
REGISTER BITREGISTER151413121110987654321000000000
APC00000000
PSF1000000000000000
IMR0000000010iii0s0
IIR00000000
CKCNsss00000
WDCNss000ss0
A[n]
(0..15)00000000
PFX0000000000000000100000000000000000000000000000110000000000000000
LC[0]0000000000000000
LC[1]0000000000000000
Offs00000000
DPC00000000000000000000000000000000
GRL000000000000000000000000
GRS0000000000000000
GRH00000000
GRXL0000000000000000
BP[offs]0000000000000000
DP00000000000000000
DP10000000000000000
Note: Bits marked with an “i” have an indeterminate value upon reset. Bits marked with an “s” have special behavior upon reset.Refer to the User’s Guide Supplement for this device for more details.
MAXQ3210
Microcontroller with Internal Voltage Regulator,
Piezoelectric Horn Driver, and Comparator
Table 4. Peripheral Register Map
MODULE NAME (BASE SPECIFIER)REGISTER INDEXM0 (x0h)M1 (x1h)M2 (x2h)0xhPO0CMPC—
1xhPO1——
2xh———
3xh———
4xh—T2CNA—
5xh—T2H—
6xh—T2RH—
7xhEIE0T2CH—
8xhPI0T2CNB—
9xhPI1
T2V—
Axh—
T2R—
Bxh—
T2C—
CxhHRNC——
DxhPWCN——
ExhWUTC——
Fxh
WUT——
MODULE NAME (BASE SPECIFIER)REGISTER INDEXM0 (x0h)M1 (x1h)M2 (x2h)10xhPD0T2CFG—
11xhPD1——
12xh———
13xh———
14xhKEN0——
15xhKEN1——
16xh———
17xh———
18xh———
19xh———
1Axh———
1BxhICDF——
1Cxh———
1Dxh———
1Exh———
1Fxh———
Note:Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register
is 16 bits wide.
