MAXQ2000-RAX+-MAXQ2000RFX Fast Delivery |IC PHOENIX CO.,LIMITED

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MAXQ2000-RAX+-MAXQ2000RFX
Low-Power LCD Microcontroller
General Description
The MAXQ2000 microcontroller is a low-power, 16-bit
device that incorporates a liquid-crystal display (LCD)
interface that can drive up to 100 (-RBX/-RBX+) or 132
(-RAX/-RAX+/-RFX/-RFX+) segments. The MAXQ2000
is uniquely suited for the blood-glucose monitoring mar-
ket, but can be used in any application that requires
high performance and low-power operation. The device
can operate at a maximum of either 14MHz (VDD>
1.8V) or 20MHz (VDD> 2.25V). The MAXQ2000 has
32kWords of flash memory, 1kWord of RAM, three 16-
bit timers, and one or two universal synchronous/asyn-
chronous receiver/transmitters (UARTs). Flash memory
aids prototyping and low-volume production. The
microcontroller core is powered by a 1.8V supply, with
a separate I/O supply for optimum flexibility. An ultra-
low-power sleep mode makes these parts ideal for bat-
tery-powered, portable equipment.
Applications
Medical Instrumentation
Battery-Powered and Portable Devices
Electrochemical and Optical Sensors
Industrial Control
Data-Acquisition Systems and Data Loggers
Home Appliances
Consumer Electronics
Thermostats/Humidity Sensors
Security Sensors
Gas and Chemical Sensors
HVAC
Smart Transmitters
FeaturesHigh-Performance, Low-Power, 16-Bit RISC Core
DC to 20MHz Operation, Approaching 1MIPS per MHz
Dual 1.8V Core/3V I/O Enables Low Power/Flexible
Interfacing
33 Instructions, Most Single Cycle
Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
16-Level Hardware Stack
16-Bit Instruction Word, 16-Bit Data Bus
16 x 16-Bit, General-Purpose Working Registers
Optimized for C-Compiler (High-Speed/Density Code)Program and Data Memory
32kWords Flash Memory, Mask ROM for High-
Volume Applications
10,000 Flash Write/Erase Cycles
1kWord of Internal Data RAM
JTAG/Serial Boot Loader for ProgrammingPeripheral Features
Up to 50 General-Purpose I/O Pins
100/132 Segment LCD Driver
Up to 4 COM and 36 Segments
Static, 1/2, and 1/3 LCD Bias Supported
No External Resistors Required
SPITMand 1-Wire®(-RAX/-RAX+/-RFX/-RFX+ Only)
Hardware I/O Ports
One or Two Serial UARTs
One-Cycle, 16 x 16 Hardware Multiply/Accumulate
with 48-Bit Accumulator
Three 16-Bit Programmable Timers/Counters
8-Bit, Subsecond, System Timer/Alarm
32-Bit, Binary Real-Time Clock with Time-of-Day Alarm
Programmable Watchdog TimerFlexible Programming Interface
Bootloader Simplifies Programming
In-System Programming Through JTAG
Supports In-Application Programming of Flash MemoryUltra-Low-Power Consumption
190µA typ at 8MHz Flash Operation, PMM1 at 2.2V
700nA typ in Lowest Power Stop Mode
Low-Power 32kHz Mode and Divide-by-256 Mode
MAXQ2000
Low-Power LCD Microcontroller
Rev 10; 7/08
Typical Operating Circuit, Pin Configurations, and
Ordering Information appear at end of data sheet.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
1-Wire is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated Products, Inc.
EVALUATION KIT
AVAILABLE
Note:Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
MAXQ2000
Low-Power LCD Microcontroller
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= VDD(MIN)to VDD(MAX), VDDIO= 2.7V to 3.6V, TA= -40°C to +85°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on Any Pin Relative to
Ground Except VDD.................................-0.5V to (VDDIO+ 0.5)V
Voltage Range on VDDRelative to Ground.........-0.5V to +2.75V
Voltage Range on VDDIORelative to Ground........-0.5V to +3.6V
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature ..........................Refer to the IPC/JEDEC
J-STD-020 Specification.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
32k x 16 flash 1.8 2.5 2.75 Core Supply Voltage VDDFlash programming 2.25 2.5 2.75 V
I/O Supply Voltage VDDIO VDD 3.6 V
VDD Slew Rate VDD rising (Note 2) 225 mV/ms
IDD1 /1 mode 6.0 9.2
IDD2 /2 mode 5.6 8.6
IDD3 /4 mode 3.4 5.1
IDD4 /8 mode 1.9 2.9
IDD5 PMM1 mode 0.5 0.7
Rev A2 4.8 7.6
Active Current,
fHFIN = 14MHz
(Note 3)
IDD6PMM2 mode;
32KIN = 32.768kHz Rev A3 0.1 0.95
mA
IDD1 /1 mode 6.5 10.4
IDD2 /2 mode 5.9 9.6
IDD3 /4 mode 3.8 6.2
IDD4 /8 mode 2.2 3.8
IDD5 PMM1 mode 0.6 1.4
Rev A2 4.8 7.6
Active Current,
fHFIN = 20MHz
(Note 3)
IDD6PMM2 mode;
32KIN = 32.768kHz Rev A3 0.1 0.95
mA
Execution from flash memory, 20MHz,
VDD = 2.2V, TA = +25°C 5.1
Execution from flash memory, 8MHz,
/8 mode, VDD = 2.2V, TA = +25°C 0.85
Execution from flash memory, 8MHz,
PMM1 mode, VDD = 2.2V, TA = +25°C 0.19
Execution from RAM, 8MHz,
/8 mode, VDD = 2.2V, TA = +25°C 0.30
Active Current
Execution from RAM, 1MHz,
/1 mode, VDD = 2.2V, TA = +25°C 0.14
mA
-40°C < TA < +25°C 0.7 55 Stop-Mode Current ISTOP(VDD)TA = +85°C 20 550 μA
Digital I/O Supply Current IDDIORTC enabled; HFIN 14MHz;
all I/O disconnected 1 50 μA
MAXQ2000
Low-Power LCD Microcontroller
ELECTRICAL CHARACTERISTICS (continued)
(VDD= VDD(MIN)to VDD(MAX), VDDIO= 2.7V to 3.6V, TA= -40°C to +85°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Input High Voltage:
HFIN and 32KIN VIH10.8 x
VDDIO VDDIO V
Input High Voltage:
P6.4–P6.5 and P7.0–P7.1 VIH2 SVS on, VLCD = 3.3V 0.8 x
VLCD VLCD V
Input High Voltage:
All Other Pins VIH30.8 x
VDDIO VDDIO V
Input Low Voltage:
HFIN and 32KIN VIL1 0 0.2 x
VDDIOV
Input Low Voltage:
All Other Pins VIL2 0 0.2 x
VDDIOV
Output High Voltage:
P6.4–P6.5 and P7.0–P7.1 VOH1 SVS on; IOH(MAX) = 0.75mA; VLCD = 2.7V VLCD -
0.2 V
Output High Voltage:
All Other Pins VOH2 IOH(MAX) = 0.75mA; VDDIO =1.8V VDDIO -
0.2 V
Output Low Voltage for
All Other Pins VOL1 IOL = 1.0mA; VDDIO = 1.8V GND 0.2 V
Output Low Voltage for
P6.4–P6.5 and P7.0–P7.1 VOL2 IOL = 1.4mA; VDDIO = 2.7V GND 0.2 V
Input Leakage Current IL Internal pullup disabled -100 +100 nA
Input Pullup Current IIP Internal pullup enabled -20 -5 μA
LCD INTERFACE
LCD Reference Voltage VLCD 2.7 3.3 3.6 V
LCD Bias Voltage 1 VLCD1 1/3 bias VADJ + 2/3 (VLCD - VADJ) V
LCD Bias Voltage 2 VLCD2 1/3 bias VADJ + 1/3 (VLCD - VADJ) V
LCD Adjustment Voltage VADJ Guaranteed by design 0 0.4 x
VLCDV
LCD Bias Resistor RLCD 100 k
LCD Adjustment Resistor RLADJ LRA4:LRA0 = 11111b 200 k
When segment is driven at VLCD level;
VLCD = 3V; ISEGxx = -3μA;
guaranteed by design
VLCD -
0.02 VLCD
When segment is driven at VLCD1 level;
VLCD1 = 2V; ISEGxx = -3μA;
guaranteed by design
VLCD1 -
0.02 VLCD1
When segment is driven at VLCD2 level;
VLCD2 = 1V; ISEGxx = -3μA;
guaranteed by design
VLCD2 -
0.02 VLCD2
LCD Segment Voltage VSEGxx
When segment is driven at VADJ level;
VADJ = 0V; ISEGxx = 3μA;
guaranteed by design
VADJ 0.1
MAXQ2000
Low-Power LCD Microcontroller
ELECTRICAL CHARACTERISTICS (continued)
(VDD= VDD(MIN)to VDD(MAX), VDDIO= 2.7V to 3.6V, TA= -40°C to +85°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EXTERNAL CLOCK SOURCE
External oscillator, VDD 2.25V 0 20
External oscillator, VDD < 2.25V 0 14
External crystal, VDD 2.25V 3 20
External crystal, VDD < 2.25V 3 14
Flash programming, VDD 2.25V 2 20
External-Clock
Frequency fHFIN
Flash programming, VDD < 2.25V 2 14
MHz
External-Clock Period tCLCL 48% minimum duty cycle 50 ns
2.25V VDD 2.75V 0 20 System-Clock Frequency fCK1.8V VDD 2.75V 0 14 MHz
System-Clock Period tCK 50 ns
REAL-TIME CLOCK
RTC Input Frequency f32KIN 32kHz watch crystal 32.768 kHz
JTAG/FLASH PROGRAMMING
Mass erase 200 Flash Erase Time Page erase 20 ms
Flash Programming Time 2.5 5.0 ms
Write/Erase Cycles TA = +25°C 10,000 cycles
Data Retention TA = +25°C 100 years
SPI TIMING
SPI Master Operating
Frequency 1/tMCK fCK / 2 MHz
SPI Slave Operating
Frequency 1/tSCK fCK / 8 MHz
SCLK Output Pulse-Width
High/Low tMCH, tMCLtMCK / 2
- 25 ns
SCLK Input Pulse-Width
High/Low tSCH, tSCL tSCK / 2 ns
MOSI Output Hold Time
after SCLK Sample Edge tMOH CL = 50pF tMCK / 2
- 25 ns
MOSI Output Valid to
Sample Edge tMOVtMCK / 2
- 25 ns
MISO Input Valid to SCLK
Sample Edge Rise/Fall
Setup
tMIS 30 ns
MISO Input to SCLK
Sample Edge Rise/Fall
Hold
tMIH 0 ns
MAXQ2000
Low-Power LCD Microcontroller
Note 1:Specifications to -40°C are guaranteed by design and not production tested.
Note 2:Guaranteed by design.
Note 3:Measured on the VDDpin with VDD= 2.75V and not in reset.
ELECTRICAL CHARACTERISTICS (continued)
(VDD= VDD(MIN)to VDD(MAX), VDDIO= 2.7V to 3.6V, TA= -40°C to +85°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCLK Inactive to MOSI
Inactive tMLHtMCK / 2
- 25 ns
MOSI Input to SCLK
Sample Edge Rise/Fall
Setup
tSIS 30 ns
MOSI Input from SCLK
Sample Edge Transition
Hold
tSIH tCK + 25 ns
MISO Output Valid after
SCLK Shift Edge
Transition
tSOV 3tCK + ns
SS Inactive tSSH tCK + 25 ns
SCLK Inactive to SS
Rising tSD tCK + 25 ns
MISO Output Disabled
after CS Edge Rise tSLH 2tCK + ns
SS Active to First Shift
Edge tSSE 4tCK ns
MAXQ2000
Low-Power LCD Microcontroller
SCLK
CKPOL/CKPHA
0/1 or 1/0
tMCHtMCL
MOSIMSB
tMOH
tMOV
MISO
tMIStMIH
MSB-1
MSB
tMLH
MSB-1LSB
LSB
tMCK
SCLK
CKPOL/CKPHA
0/0 or 1/1
SHIFTSAMPLESHIFTSAMPLE
SPI Master Timing
tSSE
tSCK
tSCH
tSIS
tSOVtSLH
tSD
tSSH
tSIH
tSCL
SHIFTSAMPLESHIFTSAMPLE
SCLK
CKPOL/CKPHA
0/1 or 1/0
MOSI
MISO
SCLK
CKPOL/CKPHA
0/0 or 1/1
MSB
MSB
MSB-1
MSB-1
LSB
LSB
SPI Slave Timing
MAXQ2000
Low-Power LCD Microcontroller
DIGITAL SUPPLY CURRENT
vs. CLOCK FREQUENCY
MAXQ2000 toc01
fHFIN (MHz)
DD1
(mA)5
VDD = 2.75V
TA = +25°C
TA = -40°CTA = 0°C
TA = +85°C
Typical Operating Characteristics
Pin Description
PIN
TQFN-EPQFN-EPLQFPNAMEFUNCTION
40 49 70 VDDDigital Supply Voltage
22 27 36, 62 VDDIOI/O Supply Voltage
23, 35 28, 42 39, 63 GND Ground
45 54 83 VLCDLCD Bias-Control Voltage. Highest LCD drive voltage used with static bias. Connected
to an external source.
46 55 84 VLCD1
LCD Bias, Voltage 1. LCD drive voltage used with 1/2 and 1/3 LCD bias. An internal
resistor- divider sets the voltage. External resistors and capacitors can be used to
change the LCD voltage or drive capability at this pin.
47 56 85 VLCD2
LCD Bias, Voltage 2. LCD drive voltage used with 1/3 LCD bias. An internal
resistor-divider sets the voltage. External resistors and capacitors can be used to
change LCD voltage or drive capability at this pin.
48 57 86 VADJLCD Adjustment Voltage. Connect to an external resistor to provide external control
of the LCD contrast. Leave disconnected for internal contrast adjustment.
28 33 50 RESET
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this is low
and begins executing from the reset vector when released. The pin includes pullup
current source and should be driven by an open-drain, external source capable of
sinking in excess of 2mA. This pin is driven low as an output when an internal reset
condition occurs.
42 51 76 HFXIN
High-Frequency Crystal Input. Connect an external crystal or resonator between
HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the
input for an external, high-frequency clock source when HFXOUT is floating.
41 50 71 HFXOUT
High-Frequency Crystal Output/Input. Connect an external crystal or resonator
between HFXIN and HFXOUT as the high-frequency system clock. Alternatively,
float HFXOUT when an external, high-frequency clock source is connected to the
HFXIN pin.
MAXQ2000
Low-Power LCD Microcontroller
Pin Description (continued)
PIN
TQFN-EP QFN-EP LQFP
NAMEFUNCTION
29 34 52 32KIN
32kHz Crystal Input. Connect an external, 32kHz watch crystal between 32KIN and
32KOUT as the low-frequency system clock. Alternatively, 32KIN is the input for an
external, 32kHz clock source when 32KOUT is floating.
30 35 53 32KOUT
32kHz Crystal Output/Input. Connect an external, 32kHz watch crystal between
32KIN and 32KOUT as the low-frequency system clock. Alternatively, float 32KOUT
when an external, 32kHz clock source is connected to the 32KIN pin.
General-Purpose, 8-Bit, Digital, I/O, Type-C Port; LCD Segment-Driver Output.
These port pins function as both bidirectional I/O pins and LCD segment-drive
outputs. All port pins are defaulted as input with weak pullup after a reset. Enabling
a pin’s LCD function disables the general-purpose I/O on the pin. Setting the PCF1
bit enables the LCD for all pins on this port and disables the general-purpose I/O
function on all pins.
56-PIN68-PIN100-PINPORTALTERNATE FUNCTION
1 66 97 P1.0SEG8
2 67 98 P1.1 SEG9
3 68 3 P1.2 SEG10
4 1 4 P1.3 SEG11
5 2 5 P1.4 SEG12
6 3 6 P1.5 SEG13
7 4 7 P1.6 SEG14
1–8 66, 67,
68; 1–5
97, 98,
3–8
P1.0–
P1.7;
SEG8–
SEG15
8 5 8 P1.7 SEG15
General-Purpose, 8-Bit, Digital, I/O, Type-C Port; LCD Segment-Driver Output.
These port pins function as both bidirectional I/O pins and LCD segment-drive
outputs. All port pins are defaulted as input with weak pullup after a reset. Enabling
a pin’s LCD function disables the general-purpose I/O on the pin. Setting the PCF2
bit enables the LCD for all pins on this port and disables the general-purpose I/O
function on all pins.
ALTERNATE FUNCTIONS56-PIN68-PIN100-PINPORT56-PIN68-PIN
— 6 9 P2.0 — SEG16
— 7 10 P2.1 — SEG17
— 8 11 P2.2 — SEG18
— 9 14 P2.3 — SEG19
9 10 15 P2.4 SEG16 SEG20
10 11 16 P2.5 SEG17 SEG21
11 12 17 P2.6 SEG18 SEG22
9–12 6–13
9, 10,
11, 14–
P2.0–
P2.7;
SEG16–
SEG23
12 13 18 P2.7 SEG19 SEG23
MAXQ2000
Low-Power LCD Microcontroller
Pin Description (continued)
PIN
TQFN-EP QFN-EP LQFPNAME FUNCTION
General-Purpose, Digital, I/O, Type-D Port; LCD Segment-Driver Output; External
Edge-Selectable Interrupt. This port functions as both bidirectional I/O pins and LCD
segment-drive outputs. All port pins are defaulted as inputs with weak pullups after a
reset. The port pads can be configured as an external interrupt for pins 7 to 4. If the
external interrupt is enabled, the LCD function on the associated pin is disabled.
Setting the PCF3 bit enables the LCD for all pins on this port and disables the general-
purpose I/O function on all pins.
It is possible to mix the LCD and interrupt functions on the same port. To do this, the
interrupt enable must be established prior to setting the PCF0 bit. Care must be taken
not to enable the external interrupt while the LCD is in normal operational mode, as
this could result in potentially harmful contention between the LCD controller output
and the external source connected to the interrupt input.
ALTERNATE FUNCTIONS56-PIN68-PIN100-PINPORT56-PIN68-PIN
— 14 19 P3.0— SEG24
— 15 20 P3.1 — SEG25
— 16 21 P3.2 — SEG26
— 17 22 P3.3 — SEG27
13 18 23 P3.4 SEG20/INT4 SEG28/INT4
14 19 27 P3.5 SEG21/INT5 SEG29/INT5
15 20 28 P3.6 SEG22/INT6 SEG30/INT6
13–16 14–21
19–23,
27, 28,
P3.0–
P3.7;
SEGx;
INT4–
INT7
16 21 29 P3.7 SEG23/INT7 SEG31/INT7
LCD Segment-Driver Output; LCD Common-Drive Output. The selection of a pin
function as either segment or its alternative common-mode signal is controlled by the
choice of duty cycle (DUTY1:0).
FUNCTION56-PIN68-PIN100-PIN56-PIN68-PIN100-PIN
ALTERNATE
FUNCTIONS
17 22 30 SEG24SEG32 SEG32 —
18 23 31 SEG25SEG33 COM3COM3
19 24 32 SEG26SEG34 COM2 COM2
20 25 33 SEG27SEG35 COM1 COM1
17–21 22–26 30–34
SEGx;
COM3–
COM0
21 26 34 — COM0 COM0 —
General-Purpose, Digital, I/O, Type-D Port; Debug Port Signal; External Edge-
Selectable Interrupt. Pins default to JTAG on POR; other functions must be enabled
from software.
56-PIN68-PIN100-PINPORTALTERNATE FUNCTIONS
24 29 40 P4.0TCKINT8
25 30 41 P4.1 TDI INT9
26 31 42 P4.2 TMS —
24–27 29–32 40–43
P4.0–
P4.3;
TCK/TDI/
TMS/
TDO;
INT8,
INT9
27 32 43 P4.3 TDO —
MAXQ2000
Low-Power LCD Microcontroller
Pin Description (continued)
PIN
TQFN-EP QFN-EP LQFP
NAME FUNCTION
— 36 54 P5.2/RX1/
INT10
General-Purpose, Digital, I/O, Type-D Port; Serial Port 1 Receive; External Edge-
Selectable Interrupt 10
— 37 56 P5.3/TX1/
INT11
General-Purpose, Digital, I/O, Type-D Port; Serial Port 1 Transmit; External Edge-
Selectable Interrupt 11
31 38 57 P5.4/SSGeneral-Purpose, Digital, I/O, Type-C Port; Active-Low, SPI, Slave-Select Input.
Becomes the slave-select input in SPI mode.
32 39 58 P5.5;
MOSI
General-Purpose, Digital, I/O, Type-C Port; SPI, Master-Out Slave-In Output. Data
is clocked out of the microcontroller on SCLK’s falling edge and into the slave
device on SCLK’s rising edge. Becomes MOSI input in SPI mode.
33 40 59 P5.6;
SCLK
General-Purpose, Digital, I/O, Type-C Port; SPI, Clock Output. Becomes SCLK
input in slave mode but limited to SYSCLK / 8.
34 41 60 P5.7/
MISO
General-Purpose, Digital, I/O, Type-C Port; SPI, Master-In Slave-Out Input. Data is
clocked out of the slave on SCLK’s falling edge and into the microcontroller on
SCLK’s rising edge. Becomes MISO output in slave mode.
36 43 64 P6.0/T1B/
INT12
General-Purpose, Digital, I/O, Type-D Port; Timer 1 Alternative Output (PWM);
External Edge-Selectable Interrupt 12
37 44 65 P6.1/T1/
INT13
General-Purpose, Digital, I/O Type-D Port; Timer 1 Output (PWM); External Edge-
Selectable Interrupt 13
— 45 66 P6.2/T2B/
OW_OUT
General-Purpose, Digital, I/O, Type-D Port; Timer 2 Alternative Output (PWM);
1-Wire Data Output
— 46 67 P6.3/T2/
OW_IN
General-Purpose, Digital, I/O, Type-D Port; Timer 2 Output (PWM); 1-Wire Data
Input
38 47 68 P6.4/T0B/
WKOUT0
General-Purpose, Digital, I/O, Type-C Port; Timer 0 Alternative Output (PWM);
Wakeup Output 0
39 48 69 P6.5/T0/
WKOUT1
General-Purpose, Digital, I/O, Type-C Port; Timer 0 Output (PWM); Wakeup
Output 1
43 52 81 P7.0/TX0/
INT14
General-Purpose, Digital, I/O, Type-D Port; Serial Port 0 Transmit; External, Edge-
Selectable Interrupt 14
44 53 82 P7.1/RX0/
INT15
General-Purpose, Digital, I/O, Type-D Port; Serial Port 0 Receive; External Edge-
Selectable Interrupt 15
MAXQ2000
Low-Power LCD Microcontroller
Pin Description (continued)
PIN
TQFN-EP QFN-EP LQFPNAME FUNCTION
General-Purpose, Digital, I/O, Type-D Port; LCD Segment-Driver Output; External
Edge-Selectable Interrupt. This port functions as both bidirectional I/O pins and
LCD segment-drive outputs. All port pins are defaulted as input with weak pullup
after a reset. The port pads can be configured as an external interrupt for pins 7 to
4. If the external interrupt is enabled, the LCD function on the associated pin is
disabled. Setting the PCF0 bit enables the LCD for all pins on this port and disables
the general-purpose I/O function on all pins.
It is possible to mix the LCD and interrupt functions on the same port. To do this,
the interrupt enable must be established prior to setting the PCF0 bit. Care must be
taken not to enable the external interrupt while the LCD is in normal operational
mode, as this could result in potentially harmful contention between the LCD
controller output and the external source connected to the interrupt input.
56-PIN68-PIN100-PINPORTALTERNATE FUNCTIONS
49 58 89 P0.0 SEG0 —
50 59 90 P0.1 SEG1 —
51 60 91 P0.2 SEG2 —
52 61 92 P0.3 SEG3 —
53 62 93 P0.4 SEG4 INT0
54 63 94 P0.5 SEG5 INT1
55 64 95 P0.6 SEG6 INT2
49–56 58–65 89–96
P0.0–
P0.7;
SEG0–
SEG7;
INT0–
INT3
56 65 96 P0.7 SEG7 INT3
— —
1, 2, 12,
13, 24,
25, 26,
35, 37,
38, 44–
49, 51,
55, 61,
72–75,
77–80,
87, 88,
99, 100
N.C.No Connection. These pins should not be connected.
— — — EP Exposed Paddle. Exposed paddle is on the under side of the package. It should be
left unconnected.
MAXQ2000
Low-Power LCD Microcontroller
Block Diagram
SCLK
MOSI
MISO
3/4-WIRE (SPI)
INTERFACE
32k
OSC
32KIN
32KOUT
RTC AND
ALARMS
16-BIT
RISC CPU
32k x 16
(64kByte)
FLASH ROM
MASK ROM
2k x 8
RAM
LCD
CONTROLLER/
DRIVER
INTERRUPT
CONTROLLER
WATCHDOG
TIMER
TIMER0
TIMER1
TIMER2
DPTR0
DPTR1
REGISTER
FILE
32KCLK
2:1
MUX
SYS_AL
DAY_AL
WDCLK
SYS_AL
DAY_AL
SYSCLK
LCD BIAS
CONTROL
VLCD1
VLCD2
VADJ
SEG[32]/INT16
COM[3:1]/SEG[33:35]
EMULATION/
DOWNLOAD
x 8 LCD
DISPLAY
RAM
P4.0/TCK/INT8
P4.2/TMS
P4.1/TDI/INT9
P4.3/TDO
IOINT
HFXIN
SCLKDIV
OWOUT1WINT
VLCD
VDDIO
VDD
GND
RESET
WDDIVWDCLKT2INT
T1INT
T0INT
2:1
MUXES
TCLKDIVT0CLK
T1CLK
T2CLK
T2CLK
T1CLK
T0CLK
U1INT
3WINT
SEG[0:3]/P0[0:3]
WDINT
TXD0
RXD0
SERIAL
UART2
SERIAL
UART1
U2INTTXD1
RXD1
SEG[4:7]/P0[4:7]/INT[0:3]
SEG[16:23]/P2[0:7]
SEG[0]:SEG32
SEG[8:15]/P1[0:7]
GNDIO
HF OSC
HFXOUT
HFCLK
COM[0]
16 x 16
MULTIPLY
MAXQ2000
OWIN
GND
SEG[24:27]/P3[0:3]
SEG[28:31]/P3[4:7]/INT[4:7]
P5.3/TX1/INT11
P5.2/RX1/INT10
P7.1/RX0/INT15
P7.0/TX0/INT14
P5.6/SCLK
P5.7/MISO
P5.5/MOSI
P5.4/SS
T2B
T1B
T0B
P6.1/T1/INT13
P6.0/T1B/INT12
P6.5/T0B/WKOUT
P6.4/T0/WKOUT
P6.3/T2/OWIN
P6.2/T2B/OWOUT
PAD DRIVERS
WKOUT_EN
WKUPWK_OUT
DPTR2
1-WIRE
INTERFACE
VLCD
32KHzLCD
CLK
SELECTHF OSC / 128
VDDIO
MAXQ2000
Low-Power LCD Microcontroller
Detailed Description
The following is an introduction to the primary features
of the microcontroller. More detailed descriptions of the
device features can be found in the data sheets, errata
sheets, and user’s guides described later in the
Additional Documentationsection.
MAXQ Core Architecture
The MAXQ2000 is a low-cost, high-performance,
CMOS, fully static, 16-bit RISC microcontroller with flash
memory and an integrated 100- or 132-segment LCD
controller. It is structured on a highly advanced, accu-
mulator-based, 16-bit RISC architecture. Fetch and exe-
cution operations are completed in one cycle without
pipelining, because the instruction contains both the op
code and data. The result is a streamlined 20 million
instructions-per-second (MIPS) microcontroller.
The highly efficient core is supported by a 16-level
hardware stack, enabling fast subroutine calling and
task switching. Data can be quickly and efficiently
manipulated with three internal data pointers. Multiple
data pointers allow more than one function to access
data memory without having to save and restore data
pointers each time. The data pointers can automatically
increment or decrement following an operation, elimi-
nating the need for software intervention. As a result,
application speed is greatly increased.
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular, so that
new devices and modules can reuse code developed
for existing products.
The architecture is transport-triggered. This means that
writes or reads from certain register locations can also
cause side effects to occur. These side effects form the
basis for the higher-level op codes defined by the
assembler, such as ADDC, OR, JUMP, etc. The op
codes are actually implemented as MOVE instructions
between certain register locations, while the assembler
handles the encoding, which need not be a concern to
the programmer.
The 16-bit instruction word is designed for efficient exe-
cution. Bit 15 indicates the format for the source field of
the instruction. Bits 0 to 7 of the instruction represent the
source for the transfer. Depending on the value of the
format field, this can either be an immediate value or a
source register. If this field represents a register, the
lower four bits contain the module specifier and the
upper four bits contain the register index in that module.
Bits 8 to 14 represent the destination for the transfer.
This value always represents a destination register, with
the lower four bits containing the module specifier and
the upper three bits containing the register subindex
within that module. Any time that it is necessary to
directly select one of the upper 24 registers as a desti-
nation, the prefix register, PFX, is needed to supply the
extra destination bits. This prefix register write is insert-
ed automatically by the assembler and requires only
one additional execution cycle.
Memory Organization
The device incorporates several memory areas:4kB utility ROM,32kWords of flash memory for program storage,1kWord of SRAM for storage of temporary variables, and16-level stack memory for storage of program return
addresses and general-purpose use.
The memory is arranged by default in a Harvard archi-
tecture, with separate address spaces for program and
data memory. A special mode allows data memory to be
mapped into program space, permitting code execution
from data memory. In addition, another mode allows pro-
gram memory to be mapped into data space, permitting
code constants to be accessed as data memory.
The incorporation of flash memory allows the devices to
be reprogrammed, eliminating the expense of throwing
away one-time programmable devices during develop-
ment and field upgrades. Flash memory can be pass-
word protected with a 16-word key, denying access to
program memory by unauthorized individuals.
A pseudo-Von Neumann memory map can also be
enabled. This places the utility ROM, code, and data
memory into a single contiguous memory map. This is
useful for applications that require dynamic program
modification or unique memory configurations.
Stack Memory
A 16-bit-wide internal stack provides storage for pro-
gram return addresses and general-purpose use. The
stack is used automatically by the processor when the
CALL, RET, and RETI instructions are executed and
interrupts serviced. The stack can also be used explic-
itly to store and retrieve data by using the PUSH, POP,
and POPI instructions.
MAXQ2000
Low-Power LCD Microcontroller
00h
06h
0Fh
07h
SPRs
0000h
FFFFhFFFFh
REGISTERS
0000h
SFRs
1Fh
FFh
00h
0Fh
16 x 16
STACK
1k x 16 SRAM
03FFh
7FFFh
87FFh
32k x 16
FLASH
MEMORY
2k x 16
UTILITY
ROM
PROGRAM MEMORYDATA MEMORY
Figure 1. Memory Map
MAXQ2000
Low-Power LCD Microcontroller
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vector-
ing operations increment SP, then store a value at the
location pointed to by SP. The RET, RETI, POP, and
POPI operations retrieve the value @SP and then
decrement SP.
Utility ROM
The utility ROM is a 4kB block of internal ROM memory
that defaults to a starting address of 8000h. The utility
ROM consists of subroutines that can be called from
application software. These include:In-system programming (bootstrap loader) over JTAG
or UART interfacesIn-circuit debug routinesTest routines (internal memory tests, memory
loader, etc.)User-callable routines for in-application flash pro-
gramming and fast table lookup
Following any reset, execution begins in the utility
ROM. The ROM software determines whether the pro-
gram execution should immediately jump to location
0000h, the start of user-application code, or to one of
the special routines mentioned. Routines within the utili-
ty ROM are user-accessible and can be called as sub-
routines by the application software. More information
on the utility ROM contents is contained in the MAXQ
Family User’s Guide: MAXQ2000 Supplement.
Some applications require protection against unautho-
rized viewing of program code memory. For these
applications, access to in-system programming, in-
application programming, or in-circuit debugging func-
tions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses x0010h to x001Fh.
A single password lock (PWL) bit is implemented in the
SC register. When the PWL is set to one (power-on
reset default), the password is required to access the
utility ROM, including in-circuit debug and in-system
programming routines that allow reading or writing of
internal memory. When PWL is cleared to zero, these
utilities are fully accessible without password. The
password is automatically set to all ones following a
mass erase.
Programming
The flash memory of the microcontroller can be pro-
grammed by two different methods: in-system pro-
gramming and in-application programming. Both
methods afford great flexibility in system design as well
as reduce the life-cycle cost of the embedded system.
These features can be password protected to prevent
unauthorized access to code memory.
In-System Programming
An internal bootstrap loader allows the device to be
reloaded over a simple JTAG interface. As a result,
software can be upgraded in-system, eliminating the
need for a costly hardware retrofit when updates are
required. Remote software uploads are possible that
enable physically inaccessible applications to be fre-
quently updated. The interface hardware can be a
JTAG connection to another microcontroller, or a con-
nection to a PC serial port using a serial-to-JTAG con-
verter such as the MAXQJTAG-001, available from
Maxim Integrated Products. If in-system programmabili-
ty is not required, a commercial gang programmer can
be used for mass programming.
Activating the JTAG interface and loading the test
access port (TAP) with the system programming instruc-
tion invokes the bootstrap loader. Setting the SPE bit to
1 during reset through the JTAG interface executes the
bootstrap-loader-mode program that resides in the utility
ROM. When programming is complete, the bootstrap
loader can clear the SPE bit and reset the device, allow-
ing the device to bypass the utility ROM and begin exe-
cution of the application software.
The following bootstrap loader functions are supported:LoadDumpCRCVerifyErase
Optionally, the bootstrap loader can be invoked by the
application code. In this mode, the application software
would configure the SPE and PSS bits for UART com-
munication, then jump to the start of the utility ROM. In
this way, the bootstrap loader can be accessed through
another UART-enabled peripheral, or a PC serial port
through an RS-232 transceiver such as the MAX232.
Because the bootstrap loader defaults to the JTAG con-
figuration on reset, the UART versus JTAG selection
must be made from the application code. As a result,
bootstrap loader access through the UART is not possi-
ble in an unprogrammed device.
MAXQ2000
Low-Power LCD Microcontroller
In-Application Programming
The in-application programming feature allows the
microcontroller to modify its own flash program memory
while simultaneously executing its application software.
This allows on-the-fly software updates in mission-
criticalapplications that cannot afford downtime.
Alternatively, it allows the application to develop cus-
tom loader software that can operate under the control
of the application software. The utility ROM contains
user-accessible flash programming functions that erase
and program flash memory. These functions are
described in detail in the user’s guide supplement for
this device.
Register Set
Most functions of the device are controlled by sets of reg-
isters. These registers provide a working space for mem-
ory operations as well as configuring and addressing
peripheral registers on the device. Registers are divided
into two major types: system registers and peripheral reg-
isters. The common register set, also known as the sys-
tem registers, includes the ALU, accumulator registers,
data pointers, interrupt vectors and control, and stack
pointer. The peripheral registers define additional func-
tionality that may be included by different products based
on the MAXQ architecture. This functionality is broken up
into discrete modules so that only the features required
for a given product need to be included. Tables 1 and 4
show the MAXQ2000 register set.
Table 1. System Register Map
MODULE NAME (BASE SPECIFIER)REGISTER
INDEXAP (8h)A (9h)PFX (Bh)IP (Ch)SP (Dh)DPC (Eh)DP (Fh)
0xhAPA[0]PFXIP———
1xhAPCA[1]——SP——
2xh—A[2]——IV——
3xh—A[3]———OffsDP0
4xhPSFA[4]———DPC—
5xhICA[5]———GR—
6xhIMRA[6]——LC0GRL—
7xh—A[7]——LC1BPDP1
8xhSCA[8]———GRS—
9xh—A[9]———GRH—
Axh—A[10]———GRXL—
BxhIIRA[11]———FP—
Cxh—A[12]—————
Dxh—A[13]—————
ExhCKCNA[14]—————
FxhWDCNA[15]—————
Note:Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register
is 16 bits wide. Registers in module AP are bit addressable.
MAXQ2000
Low-Power LCD Microcontroller
REGISTER BIT
REGISTER
6543
AP (4 bits)
APC
CLR
IDS
MOD2
MOD1
MOD0
PSF
GPF1
GPF0
CGDS
INS
IGE
IMR
IMS
IM4
IM3
IM2
IM1
IM0
TAP
CDA0
ROD
PWL
IIR
IIS
II4
II3
II2
II1
II0
CKCN
RGSL
RGMD
STOP
SWB
PMME
CD1
CD0
WDCN
POR
EWDI
WD1
WD0
WDIF
WTRF
EWT
RWT
A[n]
(0..15)
A[n] (16 bits)
PFX
PFX (16 bits)
IP (16 bits)
———————
———
bits)
IV (16 bits)
LC[0]
LC[0] (16 bits)
LC[1]
LC[1] (16 bits)
Offs
Offs (8 bits)
———————
WBS2
WBS1
WBS0
SDPS1
SDPS0
GR.15
GR.14
GR.13
GR.12
GR.11
GR.10
GR.9
GR.8
GR.7
GR.6
GR.5
GR.4
GR.3
GR.2
GR.1
GR.0
GRL
GR.7
GR.6
GR.5
GR.4
GR.3
GR.2
GR.1
GR.0
BP (16 bits)
GRS
GR.7
GR.6
GR.5
GR.4
GR.3
GR.2
GR.1
GR.0
GR.15
GR.14
GR.13
GR.12
GR.11
GR.10
GR.9
GR.8
GRH
GR.15
GR.14
GR.13
GR.12
GR.11
GR.10
GR.9
GR.8
GRXL
GR.7
GR.7
GR.7
GR.7
GR.7
GR.7
GR.7
GR.7
GR.7
GR.6
GR.5
GR.4
GR.3
GR.2
GR.1
GR.0
FP (16 bits)
DP[0]
DP[0] (16 bits)
DP[1]
DP[1] (16 bits)
MAXQ2000
Low-Power LCD Microcontroller
Table 3. System Register Bit Reset Values
REGISTER BITREGISTER151413121110987654321000000000
APC00000000
PSF1000000000000000
IMR00000000000000s0
IIR00000000
CKCN0ss00000
WDCNss000000
A[n]
(0..15)0000000000000000
PFX0000000000000000100000000000000000000000000011110000000000000000
LC[0]0000000000000000
LC[1]0000000000000000
Offs00000000
DPC00000000000111000000000000000000
GRL000000000000000000000000
GRS0000000000000000
GRH00000000
GRXL00000000000000000000000000000000
DP00000000000000000
DP10000000000000000
MAXQ2000
Low-Power LCD Microcontroller
Table 4. Peripheral Register Map
MODULE NAME (BASE SPECIFIER)REGISTER
INDEXM0 (x0h)M1 (x1h)M2 (x2h)M3 (x3h)M4 (x4h)M5 (x5h)
0xhPO0PO4MCNTT2CNA0T2CNA1—
1xhPO1PO5MAT2H0T2H1—
2xhPO2PO6MBT2RH0T2RH1—
3xhPO3PO7MC2T2CH0T2CH1—
4xh——MC1—T2CNA2—
5xh——MC0SPIBT2H2—
6xhEIF0EIF1SCON0SCON1T2RH2—
7xhEIE0EIE1SBUF0SBUF1T2CH2—
8xhPI0PI4SMD0SMD1T2CNB1—
9xhPI1PI5PR0PR1T2V1—
AxhPI2PI6——T2R1—
BxhPI3PI7MC1R—T2C1—
CxhEIES0EIES1MC0RT2CNB0T2CNB2—
Dxh——LCRAT2V0T2V2—
Exh——LCFGT2R0T2R2—
Fxh——LCD16T2C0T2C2—
10xhPD0PD4LCD0T2CFG0T2CFG1—
11xhPD1PD5LCD1—T2CFG2—
12xhPD2PD6LCD2———
13xhPD3PD7LCD3OWA——
14xh——LCD4OWD——
15xh——LCD5SPICN——
16xh——LCD6SPICF——
17xh——LCD7SPICK——
18xh——LCD8ICDT0——
19xhRCNT—LCD9ICDT1——
1AxhRTSS—LCD10ICDC——
1BxhRTSH—LCD11ICDF——
1CxhRTSL—LCD12ICDB——
1DxhRSSA—LCD13ICDA——
1ExhRASHSVSLCD14ICDD——
1FxhRASLWKOLCD15TM——
Note:Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register
is 16 bits wide.
MAXQ2000
Low-Power LCD Microcontroller
REGISTER BIT
REGISTER
210
PO0
PO0 (8 bits)
PO1
PO1 (8 bits)
PO2
PO2 (8 bits)
PO3
PO3 (8 bits)
EIF0
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
EIE0
EX7
EX6
EX5
EX4
EX3
EX2
EX1
EX0
PI0
PI0 (8 bits)
PI1
PI1 (8 bits)
PI2
PI2 (8 bits)
PI3
PI3 (8 bits)
EIES0
IT7
IT6
IT5
IT4
IT3
IT2
IT1
IT0
PD0
PD0 (8 bits)
PD1
PD1 (8 bits)
PD2
PD2 (8 bits)
PD3
PD3 (8 bits)
RCNT
X32D
ACS
ALSF
ALDF
RDYE
RDY
BUSY
ASE
ADE
RTCE
RTSS
RTSS (8 bits)
RTSH
RTSH (16 bits)
RTSL
RTSL (16 bits)
RSSA
RSSA (8 bits)
RASH
RASH (8 bits)
RASL
RASL (16 bits)
PO4
PO4 (5 bits)
PO5
PO5 (8 bits)
PO6
PO6 (8 bits)
PO7
—————
PO7 (2 bits)
EIF1
IE15
IE14
IE13
IE12
IE11
IE10
IE9
IE8
EIE1
EX15
EX14
EX13
EX12
EX11
EX10
EX9
EX8
PI4
PI4 (5 bits)
PI5
PI5 (8 bits)
PI6
PI6 (8 bits)
PI7
—————
PI7 (2 bits)
EIES1
IT15
IT14
IT13
IT12
IT11
IT10
IT9
IT8
PD4
PD4 (5 bits)
PD5
PD5 (8 bits)
PD6
PD6 (8 bits)

Partno	Mfg	Dc	Qty	Available	Descript
MAXQ2000RFX	DALLAS	N/a	557	avai	Low-Power LCD Microcontroller
MAXQ2000-RAX+ \|MAXQ2000RAX	MAXIM	N/a	2	avai	Low-Power LCD Microcontroller