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MAX9383ESAMAXIMN/a2500avaiECL/PECL Phase-Frequency Detectors


MAX9383ESA ,ECL/PECL Phase-Frequency DetectorsApplicationsMAX9383EUA* -40°C to +85°C 8 µMAXMAX9383ESA -40°C to +85°C 8 SOPrecision Clock Distribu ..
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MAX9383ESA
ECL/PECL Phase-Frequency Detectors
General Description
The MAX9382/MAX9383 are high-speed PECL/ECL
phase-frequency detectors designed for use in high-
bandwidth phase-locked loop (PLL) applications. The
devices compare a single-ended reference (R) and a
VCO (V) input and produce pulse streams on differen-
tial up (U) and down (D) outputs. When integrated, the
difference of the output pulse streams provides a con-
trol voltage proportional to input phase or frequency dif-
ference. Guaranteed minimum short pulse duration
completely eliminates minimum phase difference
requirements during the lock condition, maximizing
loop jitter performance.
The MAX9382/MAX9383 feature low propagation and
reset delay, making them ideal for high-frequency clock
synchronization use. The MAX9382 uses 100K logic
levels, has a supply voltage range of VCC- VEE= 4.2V
to 5.5V, and is pin compatible with Motorola’s
MCK12140. The MAX9383 uses 10H logic levels with a
supply voltage range of VCC- VEE= 4.75V to 5.5V and
is pin compatible with the MCH12140.
The MAX9382/MAX9383 are available in industry-stan-
dard 8-pin SO and space-saving 8-pin µMAX packages.
Applications

Precision Clock Distribution
Central Office
DSLAM
DLC
Base Station
ATE
Features
Guaranteed Minimum Pulse Width Eliminates
Dead Band
450MHz Typical Bandwidth with up to ±πPhase
Detection
75kΩInternal Input Pulldown Resistors44mA Typical Supply Current±2kV ESD Protection (Human Body Model)Pin Compatible with MCK12140 and MCH12140Available in 8-Pin µMAX and SO Packages
MAX9382/MAX9383
ECL/PECL Phase-Frequency Detectors
Pin Configuration
Ordering Information

19-2234; Rev 1; 11/02
*Future product—contact factory for availability.
Functional Diagram
MAX9382/MAX9383
ECL/PECL Phase-Frequency Detectors
ABSOLUTE MAXIMUM RATINGS
MAX9382 DC ELECTRICAL CHARACTERISTICS

(VCC- VEE= 4.2V to 5.5V. Outputs loaded with 50Ω±1% to VCC- 2V, unless otherwise noted. Typical values at VCC- VEE= 4.5V.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE............................................................................+6.0V
Inputs (R, V).................................................(VCC) to (VEE- 0.3V)
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
Junction-to-Ambient Thermal Resistance in Still Air*
8-Pin µMAX..............................................................+221°C/W
8-Pin SO ..................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with*
500LFPM Airflow
8-Pin µMAX..............................................................+155°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin µMAX...............................................................+39°C/W
8-Pin SO....................................................................+40°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (R, V, U, U, D, D)............................±2kV
Soldering Temperature (10s)..........................................+300°C
*Ratings are for single-layer board.
MAX9382/MAX9383
ECL/PECL Phase-Frequency Detectors
MAX9383 DC ELECTRICAL CHARACTERISTICS

(VCC- VEE= 4.75V to 5.5V. Outputs loaded with 50Ω±1% to VCC- 2V, unless otherwise noted. Typical values at VCC- VEE= 5.2V.)
MAX9382/MAX9383 AC ELECTRICAL CHARACTERISTICS
MAX9382/MAX9383
ECL/PECL Phase-Frequency Detectors
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters are production tested at +85°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4:
All pins open except VCCand VEE.
Note 5:
Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 6:
Phase offset is defined as the difference in propagation delay timing between the two input paths. It is measured between
the U and D outputs at the differential crosspoint with a rising edge simultaneously applied at the R and V inputs.
Note 7:
Device jitter added to the input signal.
MAX9382/MAX9383 AC ELECTRICAL CHARACTERISTICS (continued)
MAX9382/MAX9383
ECL/PECL Phase-Frequency Detectors

SUPPLY CURRENT vs. TEMPERATURE
MAX9382/83 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX9382
TRANSITION TIME vs. TEMPERATURE
MAX9382/83 toc02
TEMPERATURE (°C)
TRANSITION TIME (ps)
MAX9383
TRANSITION TIME vs. TEMPERATURE
MAX9382/83 toc03
TEMPERATURE (°C)
TRANSITION TIME (ps)
OUTPUT SHORT-PULSE DURATION
vs. TEMPERATURE
MAX9382/83 toc04
TEMPERATURE (°C)
OUTPUT SHORT-PULSE DURATION (ps)
PROPAGATION DELAY
vs. TEMPERATURE
MAX9382/83 toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
DIFFERENTIAL OUTPUT VOLTAGE
vs. FREQUENCY

MAX9382/83 toc06
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE (V)
OUTPUT PHASE ERROR
vs. INPUT PHASE DIFFERENCE
MAX9382/83 toc07
INPUT PHASE DIFFERENCE (ns)
OUTPUT PHASE ERROR (ps)0-224
Typical Operating Characteristics

(VCC- VEE= +4.5V (MAX9382) or VCC- VEE= +5.2V (MAX9383), VIH= VCC- 1.00V, VIL= VCC- 1.60V, fR= fV= 100MHz, outputs
loaded with 50Ωto VCC- 2V, TA= +25°C, unless otherwise noted.)
MAX9382/MAX9383
Detailed Description

The MAX9382/MAX9383 are high-speed phase or fre-
quency detectors. The MAX9382 is compatible with 100K
logic and has a power-supply range of VCC- VEE = 4.2V
to 5.5V. The MAX9383 is compatible with 10H logic with a
power-supply range of VCC- VEE= 4.75V to 5.5V. Both
devices are specified to function from -40°C to +85°C.
Each device is symmetrical; the R and V input functions
may be swapped, together with the U and D output
functions, and the inputs and outputs relabeled.
Because of this device symmetry, a necessary condi-
tion for correct phase measurement operation is that
the Uand Doutputs must both be high (state 0 condi-
tion) when the rising edge of the leading input is
received. This condition is automatically generated
when the two inputs are at different frequencies.
Phase Detection

The MAX9382/MAX9383 are intended for use in high-
bandwidth PLL applications. These devices compare a
single-ended VCO input (V) to a single-ended refer-
ence input (R) to determine the phase or frequency
relationship between V and R. The device differential
outputs U, Uand D, Dprovide pulse trains with duty
cycle proportional to the phase or frequency difference
between R and V. These outputs are the up and down
signals required to control the system VCO. Figure 1
shows typical waveforms when V leads R and V lags R.
Subtracting and integrating these two outputs provide
the necessary VCO control signal. Figure 3 shows the
device transfer function obtained. The detector can
detect phase differences up to ±2π. The application
frequency and the characteristics of the device internal
reset circuits determine the usable input phase differ-
ence range.
Frequency Detection

Figure 4 is the state diagram for the MAX9382/
MAX9383. With the two inputs at the same frequency,
and input R leading input V, the device toggles
between states 0 and 2. Similarly, if input R lags input
V, the device toggles between states 0 and 1. With the
two inputs at different frequencies, the output becomes
a function of the frequency difference. The normalized
ideal transfer function is given by:
and
Output Pulses

When inputs R and V are at the same phase and fre-
quency, outputs U, Uand D, Dproduce a stream of
minimum duration pulses that occur at the rising edges
of the input waveforms. This is the lock condition. If
either input starts to lead the other in phase, the width
of pulses on the corresponding output (U for R input, D
for V input) increases in proportion to the phase differ-
ence. In a PLL implementation, these outputs direct the
ECL/PECL Phase-Frequency Detectors
Pin Description
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