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MAX9323EUP-MAX9323EUP+
One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
General DescriptionThe MAX9323 low-skew, low-jitter, clock and data dri-
ver distributes one of two single-ended LVCMOS inputs
to four differential LVPECL outputs. A single logic con-
trol signal (CLK_SEL) selects the input signal to distrib-
ute to all outputs. The device operates from 3.0V to
3.6V, making the device ideal for 3.3V systems, and
consumes only 25mA (max) of supply current.
The MAX9323 features low 150ps part-to-part skew, low
11ps output-to-output skew, and low 1.7ps RMS jitter,
making the device ideal for clock and data distribution
across a backplane or board. All outputs are enabled
and disabled synchronously with the clock input to pre-
vent partial output clock pulses.
The MAX9323 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm ✕4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range. The MAX9323 is pin com-
patible with Integrated Circuit Systems’ ICS8535-01.
ApplicationsPrecision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
Hubs
Features1.7psRMSAdded Random Jitter150ps (max) Part-to-Part Skew11ps Output-to-Output Skew450ps Propagation DelayPin Compatible with ICS8535-01Consumes Only 25mA (max) Supply Current
(50% Less than ICS8535-01)Synchronous Output Enable/DisableTwo Selectable LVCMOS Inputs3.0V to 3.6V Supply Voltage Range-40°C to +85°C Operating Temperature Range
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
Ordering Information19-2575; Rev 0; 10/02
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
PARTTEMP RANGEPIN-PACKAGEMAX9323EUP-40°C to +85°C20 TSSOP
MAX9323ETP*-40°C to +85°C20 Thin QFN-EP**
VCCCLK0
CLK_SEL
CLK_EN
GND
TOP VIEW
VCCN.C.
N.C.
CLK1
N.C.
VCC
N.C.
MAX9323
TSSOP**EXPOSED PADDLE
THIN QFN-EP** (4mm x 4mm)**CONNECT EXPOSED PADDLE TO GND.
CLK0
N.C.
CLK1
N.C.
N.C.
N.C.Q3
VCC
CLK_SELCLK_ENGNDQ0Q0
MAX9323
Pin Configurations*Future product—Contact factory for availability.
**EP = Exposed paddle.
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= 3.0V to 3.6V, outputs terminated with 50Ω±1% to (VCC- 2V), CLK_SEL = VCCor GND, CLK_EN = VCC, TA= -40°C to +85°C,
unless otherwise noted. Typical values are at VCC= 3.3V, TA= +25°C.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
Q_, Q_, CLK_, CLK_SEL,
CLK_EN to GND.....................................-0.3V to (VCC+ 0.3V)
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 11mW/°C)..............................879.1mW
20-Pin 4mm ✕4mm Thin QFN (derate 16.9mW/°C)...1349.1mW
Junction-to-Ambient Thermal Resistance in Still Air
20-Pin TSSOP............................................................+91°C/W
20-Pin 4mm ✕4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP............................................................+20°C/W
20-Pin 4mm ✕4mm Thin QFN......................................+2°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature (10s)...........................................+300°C
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
INPUTS (CLK0, CLK1, CLK_SEL, CLK_EN)CLK0, CLK12VCCInput High VoltageVIHFigure 1CLK_EN, CLK_SEL2VCCV
CLK0, CLK101.3Input Low VoltageVILFigure 1CLK_EN, CLK_SEL00.8V
CLK0, CLK1, CLK_SEL = VCC150Input High CurrentIIHCLK_EN = VCC-5+5µA
CLK0, CLK1, CLK_SEL = GND-5+5Input Low CurrentIILCLK_EN = GND-150µA
Input CapacitanceCINCLK0, CLK1, CLK_SEL, CLK_EN (Note 4)4pF
OUTPUTS (Q_, Q_)Single-Ended Output High
VoltageVOHFigure 1VCC -
VCC -
1.0V
Single-Ended Output Low
VoltageVOLFigure 1VCC -
VCC -
1.7V
Differential Output VoltageVODFigure 1, VOD = VOH - VOL0.60.85V
SUPPLYSupply Current (Note 5)ICC25mA
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Positive current flows into a pin. Negative current flows out of a pin.
Note 3:DC parameters are production tested at TA= +25°C and guaranteed by design over the full operating temperature range.
Note 4:Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 5:All pins open except VCCand GND.
Note 6:Measured from the 50% point of the input to the crossing point of the differential output signal.
Note 7:Measured between outputs of the same part at the differential signal crosspoint for a same-edge transition.
Note 8:Measured between outputs of different parts at the differential signal crosspoint under identical conditions for a same-edge
transition.
Note 9:Jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS(VCC= 3.0V to 3.6V, outputs terminated with 50Ω±1% to (VCC-2V), fIN< 266MHz, input duty cycle = 50%, input transition time =
1.1ns (20% to 80%), VIH= VCC, VIL= GND, CLK_SEL = VCCor GND, CLK_EN = VCC, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at VCC= 3.3V, TA= +25°C.) (Note 4)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITSVOH - VOL ≥ 0.6V266800Switching FrequencyfMAXVOH - VOL ≥ 0.3V1500MHz
Propagation DelaytPHL, tPLHCLK0 or CLK1 to Q_, Q_, Figure 1 (Note 6)100450600ps
Output-to-Output SkewtSKOO(Note 7)30ps
Part-to-Part SkewtSKPP(Note 8)150ps
Output Rise TimetR20% to 80%, Figure 1100203300ps
Output Fall TimetF80% to 20%, Figure 1100198300ps
Output Duty CycleODC485052%
Added Random JittertRJfIN = 266MHz, clock pattern (Note 9)1.73ps(RMS)
Added Jitter (Note 9)tAJVCC = 3.3V with 25mV superimposed
sinusoidal noise at 100kHz10ps(P-P)
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
Typical Operating Characteristics(VCC= 3.3V, outputs terminated to (VCC- 2V) through 50Ω, CLK_SEL = VCCor GND, CLK_EN = VCC, TA= +25°C.)
SUPPLY CURRENT vs. TEMPERATUREMAX9323 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)35-1510
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
MAX9323 toc02
FREQUENCY (MHz)
OUTPUT AMPLITUDE (mV)
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9323 toc03
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)3510-15
PROPAGATION DELAY
vs. TEMPERATURE
MAX9323 toc04
TEMPERATURE (°C)
PROPAGATION DELAY (ps)3510-15
tPHL
tPLH
Detailed DescriptionThe MAX9323 low-skew, low-jitter, clock and data dri-
ver distributes one of two single-ended LVCMOS input
signals to four differential LVPECL outputs. An input
multiplexer allows selection of one of the two input sig-
nals. The output drivers operate at frequencies up to
1.5GHz. The MAX9323 operates from 3.0V to 3.6V,
making it ideal for 3.3V systems.
Data Inputs
Single-Ended LVCMOS InputsThe MAX9323 accepts two single-ended LVCMOS
inputs (CLK0 and CLK1, Figure 1). An internal refer-
ence (VCC/2) provides the input thresold voltage for
CLK0 and CLK1. CLK_SEL selects the CLK0 input or
CLK1 input to be converted to four differential LVPECL
signals (see Table 1). Connect CLK_SEL to GND to
select CLK0. Connect CLK_SEL to VCCto select CLK1.
CLK0 and CLK1 are pulled to GND through internal
51kΩresistors, when not connected.
CLK_EN InputCLK_EN enables/disables the differential outputs of the
MAX9323. Connect CLK_EN to VCCto enable the differ-
ential outputs. The (Q_, Q_) outputs are driven to a differ-
ential low condition when CLK_EN = GND. Each
differential output pair disables following successive ris-
ing and falling edges on CLK_, after CLK_EN connects to
GND. Both a rising and falling edge on CLK_ are required
to complete the enable/disable function (Figure 2).
CLK_SEL InputCLK_SEL selects which single-ended LVCMOS input
signal is output differentially as four LVPECL signals.
Connect CLK_SEL to GND to select the CLK0 input.
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
Pin Description
PIN
TSSOPQFNNAMEFUNCTION18GNDGround. Provide a low-impedance connection to the ground plane.19CLK_EN
Synchronous Output Enable. Connect CLK_EN to VCC or leave floating to enable the
differential outputs. Connect CLK_EN to GND to disable the differential outputs. When
disabled, Q_ asserts low and Q_ asserts high. An internal 51kΩ pullup resistor to VCC allows
CLK_EN to be left floating.20CLK_SEL
Clock Select Input. Connect CLK_SEL to VCC to select the CLK1 input. Connect CLK_SEL to
GND or leave floating to select the CLK0 input. Only the selected CLK_ signal is reproduced
at each output. An internal 51kΩ pulldown resistor to GND allows CLK_SEL to be left floating.1CLK0
LVCMOS Clock Input. When CLK_SEL = GND, each set of outputs differentially reproduces
CLK0. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_, Q_) to differential low
when CLK0 is left open or at GND, CLK_SEL = GND, and the outputs are enabled.
5, 7, 8, 92, 4, 5, 6N.C.No Connect. Not internally connected.3CLK1
LVCMOS Clock Input. When CLK_SEL = VCC, each set of outputs differentially reproduces
CLK1. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_, Q_) to differential low
when CLK1 is left open or at GND, CLK_SEL = VCC, and the outputs are enabled.
10, 13, 187, 10, 15VCC
Positive Supply Voltage. Bypass VCC to GND with three 0.01µF and one 0.1µF ceramic
capacitors. Place the 0.01µF capacitors as close to each VCC input as possible (one per VCC
input). Connect all VCC inputs together, and bypass to GND with a 0.1µF ceramic capacitor.8Q3Inverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.9Q3Noninverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.11Q2Inverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.12Q2Noninverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.13Q1Inverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.14Q1Noninverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.16Q0Inverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.17Q0Noninverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data DriverCLK0/CLK1
tPLH
50% OF CLK INPUT
20%
80%80%
20%
(DIFFERENTIAL)
DIFFERENTIAL
OUTPUT
WAVEFORM
VOD
Q_ - Q_
VIL
VOL
VIH
VOH
tPHLtF
Figure 1. MAX9323 Clock Input-to-Output Delay and Rise/Fall Time
CLK0 OR
CLK1
DISABLEDENABLED
CLK_EN
Figure 2. MAX9323 CLK_EN Timing Diagram
