MAX9315EUP ,1:5 Differential LVPECL/LVECL/HSTL Clock and Data DriverELECTRICAL CHARACTERISTICS(V - V = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to V - 2V, SEL = hig ..
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MAX9315EUP
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
General DescriptionThe MAX9315 low-skew, 1-to-5 differential driver is
designed for clock and data distribution. This device
allows selection between two inputs. The selected input
is reproduced at five differential outputs. The differential
inputs can be adapted to accept a single-ended input
by connecting the on-chip VBBsupply to one input as a
reference voltage.
The MAX9315 features low output-to-output skew
(20ps), making it ideal for clock and data distribution
across a backplane or a board. For interfacing to differ-
ential HSTL and LVPECL signals, this device operates
over a +2.375V to +3.8V supply range, allowing high-
performance clock or data distribution in systems with a
nominal +2.5V or +3.3V supply. For differential LVECL
operation, this device operates with a -2.375V to -3.8V
supply.
The MAX9315 is offered in a space-saving 20-pin
TSSOP package.
ApplicationsPrecision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
Features+2.375V to +3.8V Supply for Differential
HSTL/LVPECL Operation-2.375V to -3.8V Supply for Differential LVECL
OperationTwo Selectable Differential InputsSynchronous Output Enable/Disable20ps Output-to-Output Skew360ps Propagation DelayGuaranteed 400mV Differential Output at 1.5GHzOn-Chip Reference for Single-Ended InputsInput Biased Low when Left OpenPin Compatible with MC100LVEP14
MAX9315VECL/HSTL
Clock and Data Driver
Pin Configuration
Ordering Information
Typical Application Circuit
Functional Diagram appears at end of data sheet.
MAX9315
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC- VEE= 2.375V to 3.8V, outputs loaded with 50Ω±1% to VCC- 2V, SEL = high or low, EN= low, unless otherwise noted. Typical
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE...............................................................................4.1V
Inputs (CLK_, CLK_, SEL, EN)
to VEE...........................................(VEE- 0.3V) to (VCC+ 0.3V)
CLK_ to CLK_....................................................................±3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
VBBSink/Source Current...............................................±0.65mA
Continuous Power Dissipation (TA= +70°C)
Single-Layer PC Board
20-Pin TSSOP (derate 7.69mW/°C above +70°C).......615mW
Multilayer PC Board
20-Pin TSSOP (derate 10.9mW/°C above +70°C).......879mW
Junction-to-Ambient Thermal Resistance in Still Air
Single-Layer PC Board
20-Pin TSSOP.........................................................+130°C/W
Multilayer PC Board
20-Pin TSSOP...........................................................+91°C/W
Junction-to-Ambient Thermal Resistance with 500LFPM
Airflow Single-Layer PC Board
20-Pin TSSOP..........................................................+9.6°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP............................................................+20°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (Inputs and Outputs).......................≥2kV
Soldering Temperature (10s)...........................................+300°C
MAX9315
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)(VCC- VEE= 2.375V to 3.8V, outputs loaded with 50Ω±1% to VCC- 2V, SEL = high or low, EN= low, unless otherwise noted. Typical
MAX9315
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
AC ELECTRICAL CHARACTERISTICS(VCC- VEE= 2.375V to 3.8V, outputs loaded with 50Ω±1% to VCC- 2V, input frequency = 1.5GHz, input transition time = 125ps (20%
to 80%), SEL = high or low, EN= low, VIHD= VEE+ 1.2V to VCC, VILD= VEEto VCC- 0.15V, VIHD- VILD= 0.15V to the smaller of 3V or
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:DC parameters production tested at TA= +25°C and guaranteed by design over the full operating temperature range.
Note 4:Single-ended input operation using VBBis limited to VCC- VEE= 3.0V to 3.8V.
Note 5:Use VBBonly for inputs that are on the same device as the VBBreference.
Note 6:All pins open except VCCand VEE.
Note 7:Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 9:Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 10:Device jitter added to the input signal.
MAX9315
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
Typical Operating Characteristics(VCC= +3.3V, VEE= 0, VIHD= VCC- 1V, VILD= VCC- 1.15V, input transition time = 125ps (20% to 80%), fIN= 2GHz, outputs loaded
with 50Ωto VCC- 2V, TA= +25°C, unless otherwise noted.)
MAX9315
Detailed DescriptionThe MAX9315 is a low-skew, 1-to-5 differential driver
designed for clock or data distribution. A 2-to-1 MUX
selects one of the two differential clock inputs, CLK0,
CLK0or CLK1, CLK1. The MUX is switched by the sin-
gle-ended SEL input. A logic low selects the CLK0,
CLK0input and a logic high selects the CLK1, CLK1
input. The SEL logic threshold is set by the internal volt-
age reference VBB. SEL can be driven to VCCand VEE
or by a single-ended LVPECL/LVECL signal. The
selected input is reproduced at five differential outputs.
Synchronous EnableThe MAX9315 is synchronously enabled and disabled
with outputs in the low state to eliminate shortened
clock pulses. ENis connected to the input of an edge-
triggered D flip-flop. After power-up, drive ENlow and
toggle the selected clock input to enable the outputs.
The outputs are enabled on the falling edge of the
selected clock input after ENgoes low. The outputs are
set to a low state on the falling edge of the selected
clock input after ENgoes high. The threshold for ENis
equal to VBB.
SupplyFor interfacing to differential HSTL and LVPECL signals,
the VCCrange is from +2.375V to +3.8V (with VEE
grounded), allowing high-performance clock or data
distribution in systems with a nominal +2.5V or +3.3V
supply. For interfacing to differential LVECL, the VEE
range is -2.375V to -3.8V (with VCCgrounded). Output
levels are referenced to VCCand are considered
LVPECL or LVECL, depending on the level of the VCC
supply. With VCCconnected to a positive supply and
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
