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MAX9218ECMMAXIMN/a8avai27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer


MAX9218ECM ,27-Bit, 3MHz-to-35MHz DC-Balanced LVDS DeserializerApplicationsNavigation System DisplayPKGPART TEMP RANGE PIN-PACKAGECODEIn-Vehicle Entertainment Sys ..
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MAX9218ECM
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
General Description
The MAX9218 digital video serial-to-parallel converter
deserializes a total of 27 bits during data and control
phases. In the data phase, the LVDS serial input is con-
verted to 18 bits of parallel video data and in the control
phase, the input is converted to 9 bits of parallel control
data. The separate video and control phases take
advantage of video timing to reduce the serial data rate.
The MAX9218 pairs with the MAX9217 serializer to form
a complete digital video transmission system.
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9218 features a selec-
table rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9218 operates from a +3.3V core supply and
features a separate output supply for interfacing to 1.8V
to 3.3V logic-level inputs. This device is available in 48-
lead Thin QFN and TQFP packages and is specified
from -40°C to +85°C.
Applications

Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
Features
Proprietary Data Decoding for DC Balance and
Reduced EMI
Control Data Deserialized During Video BlankingFive Control Data Inputs Are Single Bit-Error
Tolerant
Output Transition Time Is Scaled to Operating
Frequency for Reduced EMI
Staggered Output Switching Reduces EMIOutput Enable Allows Busing of OutputsClock Pulse Stretch on LockWide ±2% Reference Clock ToleranceSynchronizes to MAX9217 Serializer Without
External Control
ISO 10605 ESD ProtectionSeparate Output Supply Allows Interface to 1.8V
to 3.3V Logic
+3.3V Core Power SupplySpace-Saving Thin QFN and TQFP Packages-40°C to +85°C Operating Temperature
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Pin Configurations

19-3557; Rev 1; 4/05
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC_= +3.0V to +3.6V, PWRDWN= high, differential input voltage ⏐VID⏐= 0.05V to 1.2V, input common-mode voltage VCM= ⏐VID/2⏐
to VCC- ⏐VID/2⏐, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC_= +3.3V, ⏐VID⏐= 0.2V, VCM= 1.2V,
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC_to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
IN+, IN- to LVDS GND...........................................-0.5V to +4.0V
IN+, IN- Short Circuit to LVDS GND or VCCLVDS......Continuous
(R/F, OUTEN, RNG_, REFCLK,
PWRDWN) to GND.................................-0.5V to (VCC+ 0.5V)
(RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT,
LOCK) to VCCOGND...........................-0.5V to (VCCO+ 0.5V)
Continuous Power Dissipation (TA= +70°C)
48-Lead Thin QFN (derate 37mW/°C above +70°C).2963mW
48-Lead TQFP (derate 20.8mW/°C above +70°C)....1667mW
ESD Protection
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND...........................................................±3.0kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (IN+, IN-) to GND............................±10kV
Air Discharge (IN+, IN-) to GND....................................±30kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
DC ELECTRICAL CHARACTERISTICS (continued)

(VCC_= +3.0V to +3.6V, PWRDWN= high, differential input voltage ⏐VID⏐= 0.05V to 1.2V, input common-mode voltage VCM= ⏐VID/2⏐
to VCC- ⏐VID/2⏐, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC_= +3.3V, ⏐VID⏐= 0.2V, VCM= 1.2V,
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer

except VTHandVTL.
Note 2:
Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3:
All LVTTL/LVCMOS inputs, except PWRDWNat ≤0.3V or ≥VCC- 0.3V. PWRDWNis ≤0.3V.
Note 4:
AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 5:
CLincludes probe and test jig capacitance.
AC ELECTRICAL CHARACTERISTICS

(VCC_= +3.0V to 3.6V, CL= 8pF, PWRDWN= high, differential input voltage ⏐VID⏐= 0.1V to 1.2V, input common-mode voltage
VCM = ⏐VID/2⏐to VCC- ⏐VID/2⏐, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC_= +3.3V, ⏐VID⏐= 0.2V, VCM=
1.2V, TA= +25°C.) (Notes 4, 5)
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY

MAX9218 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)27711151923
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9218 toc02
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9218 toc03
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
BIT-ERROR RATE
vs. CABLE LENGTH
MAX9218 toc04
CAT5e CABLE LENGTH (m)
BIT-ERROR RATE1284
Typical Operating Characteristics
(VCC_ = +3.3V, CL= 8pF, TA= +25°C, unless otherwise noted.)
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Pin Description
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Functional Diagram

Figure1. LVDS Input Bias
Figure2. Worst-Case Output Pattern
Figure3. Output Rise and Fall Times
Figure4. High and Low Times
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer

Figure5. Synchronous Output Timing
Figure6. Deserializer Delay
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