MAX7318ATG+-MAX7318AUG-MAX7318AUG+ Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX7318ATG+-MAX7318AUG-MAX7318AUG+
2-Wire-Interfaced, 16-Bit, I/O Port Expander with Interrupt and Hot-Insertion Protection
General Description
The MAX7318 2-wire-interfaced expander provides 16-
bit parallel input/output (I/O) port expansion for SMBus™
and I2C applications. The MAX7318 consists of input
port registers, output port registers, polarity inversion
registers, configuration registers, and an I2C-compatible
serial interface logic compatible with SMBus. The sys-
tem master can invert the MAX7318 input data by writing
to the active-high polarity inversion register.
Any of the 16 I/O ports can be configured as an input or
output. A power-on reset (POR) initializes the 16 I/Os
as inputs. Three address select pins configure one of
64 slave ID addresses.
The MAX7318 supports hot insertion. All port pins, the
INToutput, SDA, SCL, and the slave address inputs
AD0–2 remain high impedance in power-down (V+ =
0V) with up to 6V asserted upon them.
The MAX7318 is available in 24-pin SO, SSOP, TSSOP,
and thin QFN packages and is specified over the -40°C
to +125°C automotive temperature range.
For applications requiring an SMBus timeout function,
refer to the MAX7311 data sheet.
Applications
Servers
RAID Systems
Industrial Control
Medical Equipment
PLCs
Instrumentation and Test Measurement
Features400kbps I2C-Compatible Serial Interface2V to 5.5V Operation5.5V Overvoltage-Tolerant I/OsSupports Hot Insertion16 I/O Pins that Default to Inputs on Power-Up100kΩPullup on Each I/OOpen-Drain Interrupt Output (INT)Noise Filter on SCL/SDA Inputs64 Slave ID Addresses AvailableLow Standby Current (5.4µA typ)Polarity Inversion4mm ✕4mm, 0.8mm Thin QFN Package-40°C to +125°C Operation
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
Ordering Information
19-3381; Rev 3; 12/07
SMBus is a trademark of Intel Corp.
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEPKG
CODE
MAX7318AWG-40°C to +125°C24 Wide SO—
MAX7318AAG-40°C to +125°C24 SSOP—
MAX7318ATG-40°C to +125°C24 Thin QFN
(4mm ✕ 4mm)T2444-4
MAX7318AUG-40°C to +125°C24 TSSOP—
TOP VIEW
SDA
SCL
AD0I/O0
AD2
AD1
I/O15
I/O14
I/O13
I/O12I/O4
I/O3
I/O2
I/O1
I/O11
I/O10
I/O9
I/O8GND
I/O7
I/O6
I/O5
TSSOP/SSOP/SO
MAX7318
INT
THIN QFN
MAX7318ATG34561716151413
SCL
SDA
INT
AD2
I/O0I/O1I/O2I/O3I/O4I/O5
AD0I/O15
I/O13
I/O12I/O11
AD1
I/O10
I/O8
I/O9
GND
I/O6
I/O7
I/O14
Pin Configurations
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND................................................................-0.3V to +6V
I/O0–I/O15 as Inputs....................................(GND - 0.3V) to +6V
SCL, SDA, AD0, AD1, AD2, INT...................(GND - 0.3V) to +6V
Maximum V+ Current......................................................+250mA
Maximum GND Current...................................................-250mA
DC Input Current on I/O0–I/O15.......................................±20mA
DC Output Current on I/O0–I/O15....................................±80mA
Continuous Power Dissipation (TA= +70°C)
24-Pin Wide SO (derate 11.8mW/°C above +70°C)....941mW
24-Pin SSOP (derate 8.0mW/°C above +70°C)...........640mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C).......976mW
24-Pin Thin QFN (derate 20.8mW/°C above +70°C).1667mW
Operating Temperature Range.........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
Supply VoltageV+2.05.5V
V+ = 2V2436
V+ = 3.3V4562Supply CurrentI+All I/Os unloaded,
fSCL = 400kHz
V+ = 5.5V83124
V+ = 2V4.812.1
V+ = 3.3V5.414.4Standby CurrentISTBYAll I/Os unloaded,
fSCL = 0
V+ = 5.5V6.419.4
Power-On Reset VoltageVPOR1.41.7V
SCL, SDA
Input-Voltage LowVIL0.3 x V+V
Input-Voltage HighVIH0.7 x V+V
Low-Level Output VoltageVOLISINK = 6mA0.4V
Leakage CurrentIL-1+1µA
Input Capacitance10pF
I/O_
Input-Voltage LowVIL0.8V
Input-Voltage HighVIH1.8V
Input Leakage CurrentTA = -40°C to +85°C; includes internal
pullup current, VIO = V+1µA
Internal Pullup CurrentTA = -40°C to +85°C, VIO = 034100µA
V+ = 2V, VOL = 0.5V8.517
V+ = 3.3V, VOL = 0.5V1732Low-Level Output CurrentISINK
V+ = 5V, VOL = 0.5V43
V+ = 3.3V, VOH = 2.4V2941High Output CurrentISOURCEV+ = 5V, VOH = 4.5V31mA
AD0, AD1, AD2
Input-Voltage LowVIL0.3 x V+V
Input-Voltage HighVIH0.7 x V+V
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
Note 1:All parameters are 100% production tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2:A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VILof the SCL
signal) to bridge the undefined region SCL’s falling edge.
Note 3:CB= total capacitance of one bus line in pF.
Note 4:The maximum tFfor the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tFis
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified tF.
Note 5:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA= +25°C.) (Note 1)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
Leakage Current-1+1µA
Input Capacitance4pF
INT
Low-Level Output CurrentIOLVOL = 0.4V6mA
AC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
SCL Clock FrequencyfSCL400kHz
Bus Free Time Between STOP
and START ConditionstBUFFigure 21.3µs
Hold Time (Repeated) START
ConditiontHD,STAFigure 20.6µs
Repeated START Condition
Setup TimetSU,STAFigure 20.6µs
STOP Condition Setup TimetSU,STOFigure 20.6µs
Data Hold TimetHD,DATFigure 2 (Note 2)0.9µs
Data Setup TimetSU,DATFigure 2100ns
SCL Low PeriodtLOWFigure 21.3µs
SCL High PeriodtHIGHFigure 20.7µs
V+ < 3.3V500SDA Fall TimetFFigure 2 (Notes 3, 4)V+ ≥ 3.3V250ns
Pulse Width of Spike SuppressedtSP(Note 5)50ns
PORT TIMING
Output Data ValidtPVFigure 73µs
Input Data Setup Time27µs
Input Data Hold Time0µs
INTERRUPT TIMING
Interrupt ValidtIVFigure 930.5µs
Interrupt ResettIRFigure 92µs
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX7318 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (
fSCL = 400kHz
ALL I/Os UNLOADED
V+ = 3.3V
V+ = 5V
V+ = 2V
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
MAX7318 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (
SCL = V+
ALL I/Os UNLOADED
V+ = 5V
V+ = 3.3V
V+ = 2V
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7318 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
fSCL = 400kHz
ALL I/Os UNLOADED
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
MAX7318 toc04
VOL (V)
ISINK
(mA)
V+ = 2V
TA = +125°C
TA = +25°C
TA = -40°C
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
MAX7318 toc05
VOL (V)
ISINK
(mA)
V+ = 3.3V
TA = +125°C
TA = -40°C
TA = +25°C
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
MAX7318 toc06
VOL (V)
ISINK
(mA)
V+ = 5V
TA = +125°C
TA = -40°C
TA = +25°C
I/O OUTPUT LOW VOLTAGE
vs. TEMPERATURE
MAX7318 toc07
TEMPERATURE (°C)
(mV)
V+ = 5V, ISINK = 10mA
V+ = 2V, ISINK = 10mA
V+ = 2V, ISINK = 1mAV+ = 5V, ISINK = 1mA
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
MAX7318 toc08
V+ - VOH (V)
ISOURCE
(mA)
V+ = 2V
TA = +125°C
TA = +25°C
TA = -40°C
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
MAX7318 toc09
V+ - VOH (V)
ISOURCE
(mA)
V+ = 3.3V
TA = +125°C
TA = +25°C
TA = -40°C
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
Pin Description
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
MAX7318 toc10
V+ - VOH (V)
SOURCE
(mA)
V+ = 5V
TA = +125°C
TA = +25°C
TA = -40°C
I/O HIGH VOLTAGE vs. TEMPERATURE
MAX7318 toc11
TEMPERATURE (°C)
- V
(V)
V+ = 5V, ISOURCE = 10mA
V+ = 2V, ISOURCE = 10mA
PIN
TSSOP/
SSOP/SO
THIN
QFN
NAMEFUNCTION
122INTInterrupt Output (Open Drain)23AD1Address Input 124AD2Address Input 2
4–111–8I/O0–I/O7Input/Output Port 19GNDSupply Ground
13–2010–17I/O8–I/O15Input/Output Port 218AD0Address Input 019SCLSerial Clock Line20SDASerial Data Line21V+Supply Voltage. Bypass with a 0.047µF capacitor to GND.—EPExposed Pad on Package Underside. Connect to GND.
MAX7318
Detailed Description
The MAX7318 general-purpose input/output (GPIO)
peripheral provides up to 16 I/O ports, controlled
through an I2C-compatible serial interface. The
MAX7318 consists of input port registers, output port
registers, polarity inversion registers, and configuration
registers. Upon power-on, all I/O lines are set as inputs.
Three slave ID address select pins, AD0, AD1, and
AD2, choose one of 64 slave ID addresses, including
the eight addresses supported by the Phillips PCA9555.
Table 1 is the register address table. Tables 2–5 show
detailed register information.
Serial Interface
Serial Addressing
The MAX7318 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX7318, and generates the SCL clock that synchro-
nizes the data transfer (Figure 2).
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
INPUT/OUTPUT
PORT 1
SMBus
CONTROL
8 BIT
READ PULSE
WRITE PULSE
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
INPUT/OUTPUT
PORT 2
8 BIT
READ PULSE
WRITE PULSE
INTPOWER-ON
RESET
INPUT
FILTER
SDA
SCL
AD2
AD1
AD0
GND
MAX7318
Figure 1. Block Diagram
SCL
SDA
START CONDITIONSTOP CONDITIONREPEATED START CONDITIONSTART CONDITION
tSU,DAT
tHD,DATtLOW
tHD,STA
tHIGHtF
tSU,STA
tHD,STA
tSU,STO
tBUF
Figure 2. 2-Wire Serial Interface Timing Diagram
Each transmission consists of a START condition sent by
a master, followed by the MAX7318 7-bit slave address
plus R/Wbit, a register address byte, 1 or more data
bytes, and finally a STOP condition (Figure 3).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7318, the MAX7318
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
SDA
SCLS
START
CONDITION
STOP
CONDITION
Figure 3. START and STOP Conditions
SDA
SCL
DATA LINE STABLE; DATA VALIDCHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGMENTSTART CONDITION
SDA
BY RECEIVER89
Figure 5. Acknowledge
MAX7318
generates the acknowledge bit since the MAX7318 is
the recipient. When the MAX7318 is transmitting to the
master, the master generates the acknowledge bit.
Slave Address
The MAX7318 has a 7-bit-long slave address (Figure 6).
The 8th bit following the 7-bit slave address is the R/W
bit. Set this bit low for a write command and high for a
read command.
Slave address pins AD2, AD1, and AD0 choose 1 of 64
slave ID addresses (Table 7).
Data Bus Transaction
The command byte is the first byte to follow the 8-bit
device slave address during a write transmission
(Table 1, Figure 7). The command byte is used to deter-
mine which of the following registers are written or read.
Writing to Port Registers
Transmit data to the MAX7318 by sending the device
slave address and setting the LSB to a logic zero. The
command byte is sent after the address and deter-
mines which registers receive the data following the
command byte (Figure 7).
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
SDA
SDAA5A4A3A2A1A0
MSBLSB
ACKR/W
PROGRAMMABLE
Figure 6. Slave Address
COMMAND BYTE
ADDRESS (hex)FUNCTIONPROTOCOLPOWER-UP
DEFAULT
0x00Input port 1Read byteXXXX XXXX
0x01Input port 2Read byteXXXX XXXX
0x02Output port 1Read/write byte1111 1111
0x03Output port 2Read/write byte1111 1111
0x04Port 1 polarity inversionRead/write byte0000 0000
0x05Port 2 polarity inversionRead/write byte0000 0000
0x06Port 1 configurationRead/write byte1111 1111
0x07Port 2 configurationRead/write byte1111 1111
0xFFFactory reserved. (Do not write to this register.)——
Table 1. Command-Byte Register3456789SCL
SDASA000000176543210A76543210A0ASLAVE ADDRESS
COMMAND BYTEPORT 1 DATAPORT 2 DATA
R/WACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVESTART
CONDITION
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
tPV
tPV
WRITE TO PORT
DATA OUT PORT 1
READ FROM PORT 2
The MAX7318’s eight registers are configured to oper-
ate as four register pairs: input ports, output ports,
polarity inversion ports, and configuration ports. After
sending 1 byte of data to one register, the next byte is
sent to the other register in the pair. For example, if the
first byte of data is sent to output port 2, then the next
byte of data is stored in output port 1. An unlimited
number of data bytes can be sent in one write transmis-
sion. This allows each 8-bit register to be updated inde-
pendently of the other registers.
Reading Port Registers
To read the device data, the bus master must first send
the MAX7318 address with the R/Wbit set to zero, fol-
lowed by the command byte, which determines which
register is accessed. After a restart, the bus master
must then send the MAX7318 address with the R/Wbit
set to 1. Data from the register defined by the com-
mand byte is then sent from the MAX7318 to the master
(Figures 8, 9).
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection0AAS1AANAPSLAVE ADDRESSSLAVE ADDRESSMSBDATALSBMSBDATALSBCOMMAND BYTE
R/WR/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
MASTER TRANSMITTER BECOMES
MASTER RECEIVER AND SLAVE
RECEIVER BECOMES SLAVE TRANSMITTER
DATA FROM LOWER OR
UPPER BYTE OF REGISTER
DATA FROM LOWER OR
UPPER BYTE OF REGISTER
TRANSFER OF DATA CAN BE STOPPED AT ANY TIME BY A STOP CONDITION.
Figure 8. Read from Register3456789SCL
SLAVE ADDRESSPORT 1 DATAPORT 2 DATAPORT 1 DATAPORT 2 DATAS1777700001PAAAA
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTERNONACKNOWLEDGE
FROM MASTER
tIVtIR
READ FROM PORT 1
READ FROM PORT 2
DATA INTO PORT 1
DATA INTO PORT 2
INT
TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE
STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS
VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.
Figure 9. Read from Input Registers
MAX7318
Data is clocked into a register on the falling edge of the
acknowledge clock pulse. After reading the first byte,
additional bytes may be read and reflect the content in
the other register in the pair. For example, if input port 1
is read, the next byte read is input port 2. An unlimited
number of data bytes can be read in one read trans-
mission, but the final byte received must not be
acknowledged by the bus master.
Interrupt (INT)
The open-drain interrupt output, INT,activates when
one of the port pins changes states and only when the
pin is configured as an input. The interrupt deactivates
when the input returns to its previous state or the input
register is read (Figure 9). A pin configured as an out-
put does not cause an interrupt. Each 8-bit port register
is read independently; therefore, an interrupt caused by
port 1 is not cleared by a read of port 2’s register.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of the input port register.
Input/Output Port
When an I/O is configured as an input, FETs Q1 and Q2
are off (Figure 10), creating a high-impedance input with
a nominal 100kΩpullup to V+. All inputs are overvoltage
protected to 5.5V, independent of supply voltage. When
a port is configured as an output, either Q1 or Q2 is on,
depending on the state of the output port register. When
V+ powers up, an internal power-on reset sets all regis-
ters to their respective defaults (Table 1).
Input Port Registers
The input port registers (Table 2) are read-only ports.
They reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or
an output by the respective configuration register. A
read of the input port 1 register latches the current
value of I/O0–I/O7. A read of the input port 2 register
latches the current value of I/O8–I/O15. Writes to the
input port registers are ignored.
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interruptand Hot-Insertion Protection
SET
CLR
SET
CLR
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
DATA FROM
SHIFT REGISTER
WRITE PULSE
READ PULSE
OUTPUT PORT
REGISTER
SET
CLR
POLARITY INVERSION
REGISTER
POLARITY
REGISTER
DATA
SET
CLR
INPUT PORT
REGISTER
CONFIGURATION
REGISTER
100kΩ
DATA FROM
SHIFT REGISTER
WRITE POLARITY
PULSE
POWER-ON
RESET
TO INT
INPUT PORT
REGISTER DATA
GND
VDD
I/O PIN
OUTPUT PORT
REGISTER DATA
Figure 10. Simplified Schematic of I/Os

Partno	Mfg	Dc	Qty	Available	Descript
MAX7318ATG+	MAIXM	N/a	2500	avai	2-Wire-Interfaced, 16-Bit, I/O Port Expander with Interrupt and Hot-Insertion Protection
MAX7318AUG	MAXIM	N/a	10	avai	2-Wire-Interfaced, 16-Bit, I/O Port Expander with Interrupt and Hot-Insertion Protection
MAX7318AUG+ \|MAX7318AUG	MAX	N/a	27	avai	2-Wire-Interfaced, 16-Bit, I/O Port Expander with Interrupt and Hot-Insertion Protection