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MAX6852AEEMAXIMN/a3avai4-Wire Interfaced, 5 x 7 Matrix Vacuum-Fluorescent Display Controller


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MAX6852AEE
4-Wire Interfaced, 5 x 7 Matrix Vacuum-Fluorescent Display Controller
General Description
The MAX6852 compact vacuum-fluorescent display
(VFD) controller provides microprocessors with the mul-
tiplex timing for 5 x 7 matrix VFD displays up to 96
characters and controls industry-standard, shift-regis-
ter, high-voltage grid/anode VFD tube drivers. The
device supports display tubes using either one or two
digits per grid, as well as universal displays. The
MAX6852 provides an internal crosspoint switch to
match any tube-driver shift-register grid/anode order,
and is compatible with both chip-in-glass and external
tube drivers. Hardware is included to simplify the gener-
ation of cathode bias and filament supplies and to pro-
vide up to five logic outputs, including a buzzer driver.
The MAX6852 includes an ASCII 104-character font,
multiplex scan circuitry, and static RAM that stores
digit, cursor, and annunciator data, as well as font data
for 24 user-definable characters. The display intensity
can be adjusted by an internal 16-step digital bright-
ness control. The device also includes separate annun-
ciator and cursor control with automatic blinking, as
well as a low-power shutdown mode.
The MAX6852 provides timing to generate the PWM
waveforms to drive the tube filament from a DC supply.
The filament drive is synchronized to the display multi-
plexing to eliminate beat artifacts. The MAX6852 is
compatible with SPI™ and QSPI™.
For a 2-wire interfaced version, refer to the MAX6853
data sheet.
Applications
Features
High-Speed 26MHz SPI-/QSPI-/MICROWIRE™-
Compatible Serial Interface
2.7V to 3.6V OperationControls Up to 96 5 x 7 Matrix CharactersOne Digit and Two Digits per Grid and Universal
Displays Supported
16-Step Digital Brightness ControlBuilt-In ASCII 104-Character Font24 User-Definable CharactersUp to Four Annunciators per Grid with Automatic
Blinking Control
Separate Cursor Control with Automatic BlinkingFilament Drive Full-Bridge Waveform SynthesisBuzzer Tone Generator with Single-Ended or
Push-Pull Driver
Up to Five General-Purpose Logic Outputs9µA Low-Power Shutdown (Data Retained)16-Pin QSOP Package
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
Ordering Information

19-2537; Rev 1; 11/02
PARTTEMP RANGEPIN-PACKAGE

MAX6852AEE-40°C to +125°C16 QSOP
Display Modules
Retail POS Displays
Weight and Tare
Displays
Bar Graph Displays
Industrial Controllers
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX6852
VFCLK
VFDOUT
VFLOAD
VFBLANK
OSC2
DIN
SCLK
OSC1
DOUT
SCLK
MICROCONTROLLER
56pF
0.1μF
GND
CHIP-ON-GLASS VFD
VFD SUPPLY VOLTAGE
10kΩ
Typical Application Circuit
Pin Configuration and Functional Diagram appear at end of
data sheet.
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with respect to GND).............................................................................-0.3V to +4V
DIN, SCLK, CS......................................................-0.3V to +5.5V
All Other Pins................................................-0.3V to (V+ + 0.3V)
Current
V+..................................................................................200mA
GND.............................................................................-200mA
PHASE1, PHASE2, PORT0, PORT1, PUMP................±150mA
VFCLK, VFDOUT, VFLOAD, VFBLANK......................±150mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate at 8.34mW/°C above +70°C).....667mW
Operating Temperature Range (TMIN, TMAX)
MAX6852AEE................................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
DC ELECTRICAL CHARACTERISTICS

(Typical operating circuit, V+ = 2.7V to 3.6V, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Operating Supply VoltageV+2.73.6V
TA = TMIN to
TMAX85Shutdown Supply CurrentISHDNShutdown mode, all digital
inputs at V+ or GND
TA = +25°C930
TA = TMIN to
TMAX3.5Operating Supply CurrentI+
OSC = 4MHz
VFLOAD, VFDOUT, VFCLK,
VFBLANK, loaded 100pFTA = +25°C0.713.0
Master Clock Frequency (OSC
Internal Oscillator)fOSC
OSC1 fitted with COSC = 56pF, OSC2 fitted
with ROSC = 10kΩ; see the Typical
Operating CircuitMHz
Master Clock Frequency (OSC
External Oscillator)OSC1 overdriven with external fOSC28MHz
Dead-Clock Protection
Frequency200kHz
OSC High TimetCH50ns
OSC Low TimetCL50ns
Fast or Slow Segment Blink Duty
Cycle(Note 2)49.550.5%
LOGIC INPUTS AND OUTPUTS

Input Leakage Current DIN,
SCLK, CSIIH, IIL0.21µA
Logic-High Input Voltage DIN,
SCLK, CSVIH2.4V
Logic-Low Input Voltage DIN,
SCLK, CSVIL0.6V
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Output Rise and Fall Time
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
tRFTCLOAD = 100pF25ns
Output High-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOHISOURCE = 10mAV + - 0.6V
Output Low-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOLISINK = 10mA0.4VV
Output Short-Circuit Source
Current PHASE1, PHASE2,
PORT0, PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
IOHSCOutput programmed high, output short
circuit to GND (Note 2)62125mA
Output Short-Circuit Sink Current
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
IOLSCOutput programmed low, output short
circuit to V+ (Note 2)72125mA
4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (Figure 6)

SCLK Clock PeriodtCP38.4ns
SCLK Pulse Width HightCH19ns
SCLK Pulse Width LowtCL19ns
CS Fall to SCLK Rise Setup TimetCSS9.5ns
SCLK Rise to CS Rise Hold TimetCSH5ns
DIN Setup TimetDS9.5ns
DIN Hold TimetDH2ns
Minimum CS Pulse HightCSW19ns
DOUT Cascade Setup Time
PORT0, PORT1tCSUPORT0 and/or PORT1 enabled as DOUT9.5ns
VFD INTERFACE TIMING CHARACTERISTICS (Figure 9)

VFCLK Clock PeriodtVCP(Note 2)2501050ns
VFCLK Pulse Width HightVCH(Note 2)125ns
VFCLK Pulse Width LowtVCL(Note 2)125ns
VFCLK Rise to VFD Load Rise
Hold TimetVCSH(Note 2)19µs
VFDOUT Setup TimetVDS(Note 2)50ns
VFLOAD Pulse HightVCSW(Note 2)245ns
Note 1:
All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
DC ELECTRICAL CHARACTERISTICS (continued)

(Typical operating circuit, V+ = 2.7V to 3.6V, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
Typical Operating Characteristics

(Typical operating circuit, V+ = 3.3V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX6852 toc01
V+ (V)
ISUPPLY
(mA)
TA = -40°C
TA = +125°C
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE

MAX6852 toc02
V+ (V)
ISUPPLY
TA = -40°C
TA = +25°C
TA = +125°C
OSC1 = 0
FREQUENCY (MHz)6543
SHUTDOWN SUPPLY CURRENT
vs. EXTERNAL OSC FREQUENCY
MAX6852 toc03
ISUPPLY6040200100
OUTPUT LOW VOLTAGE vs. ISINK

MAX6852 toc04
ISINK (mA)
(V)
TA = -40°C
V+ = 3.3V
V+ = 3.6V
V+ = 2.7V6040200100
OUTPUT LOW VOLTAGE vs. ISINK

MAX6852 toc05
ISINK (mA)
(V)
TA = +25°C
V+ = 3.6V
V+ = 2.7V
V+ = 3.3V6040200100
OUTPUT LOW VOLTAGE vs. ISINK

MAX6852 toc06
ISINK (mA)
(V)
TA = +125°C
V+ = 3.6V
V+ = 2.7V
V+ = 3.3V6040200100
VIN - VOH vs. ISOURCE

MAX6852 toc07
ISOURCE (mA)
VOL
(V)
TA = -40°C
V+ = 3.6V
V+ = 2.7V
V+ = 3.3V6040200100
VIN - VOH vs. ISOURCE

MAX6852 toc08
ISOURCE (mA)
VOL
(V)
TA = +25°C0.4
V+ = 3.6V
V+ = 2.7V
V+ = 3.3V6040200100
VIN - VOH vs. ISOURCE

MAX6852 toc09
ISOURCE (mA)
VOL
(V)
TA = +125°C
V+ = 3.6V
V+ = 2.7V
V+ = 3.3V
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
fOSC vs. TEMPERATURE

MAX6852 toc10
TEMPERATURE (°C)
fOSC
(MHz)
V+ = 2.7V
V+ = 3.3V
V+ = 3.6V
DEAD-CLOCK OSC FREQUENCY
vs. TEMPERATURE

MAX6852 toc11
TEMPERATURE (°C)
FREQUENCY (MHz)
V+ = 2.7V
V+ = 3.6V
V+ = 3.3Vypical Operating Characteristics (continued)
(Typical operating circuit, V+ = 3.3V, TA = +25°C, unless otherwise noted.)
Pin Description
PINNAMEFUNCTION
VFCLKSerial-Clock Output to External Driver. Push-pull clock output to external display driver. On VFCLK’s
falling edge, data is clocked out of VFDOUT.VFDOUTSerial-Data Output to External Driver. Push-pull data output to external display driver.VFLOADSerial-Load Output to External Driver. Push-pull load output to external display driver. Rising edge is
used by external display driver to load serial data into display latch.VFBLANKDisplay Blanking Output to External Driver. Push-pull blanking output to external display driver used for
PWM intensity control.PUMPCharge-Pump Output and General-Purpose Output. User-configurable push-pull logic output can also
be used as a driver for external charge pump.PHASE1Filament Drive PHASE1 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.PHASE2Filament Drive PHASE2 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.V+Positive Supply Voltage. Bypass V+ to GND with a 0.1µF ceramic capacitor.GNDGroundPORT0PORT0 General-Purpose Output. User-configurable push-pull logic output.SCLKSerial-Clock Input. On SCLK’s rising edge, data shifts into the internal shift register, and data is
clocked out of DOUT. SCLK is active only while CS is low.DINSerial-Data Input. Data from DIN loads into the internal 16-bit shift register on SCLK’s rising edge.CSChip-Select Input. Serial data is loaded into the shift register while CS is low. The most recent 16 bits of
data latch on CS’s rising edge.PORT1PORT1 General-Purpose Output. User-configurable push-pull logic output.
MAX6852
Detailed Description
Overview of the MAX6852

The MAX6852 VFD controller generates the multiplex
timing for the following VFD display types:Multiplexed displays with one digit per grid, and up
to 48 grids (in 48/1 mode). Each grid can contain
one 5 x 7 matrix character, a decimal place (DP)
segment, a cursor segment, and four extra annunci-
ator segments (Figure 1).Multiplexed displays with two digits per grid, and up
to 48 grids (in 96/2 mode). Each grid can contain
two 5 x 7 matrix characters, two DP segments, and
two cursor segments. No annunciator segments are
supported (Figure 2).
Each digit can have a 5 x 7 matrix character, a DP seg-
ment, a cursor segment, and (for one-digit-per-grid dis-
plays only) four annunciators (Figure 3).
The 5 x 7 matrix character segments are not controlled
directly, but use on-chip fonts that map the segments.
The fonts comprise an ASCII 104-character fixed-font
set, and 24 user-definable characters. The predefined
characters follow the Arial font, with the addition of the
following common symbols: £, €, ¥, °, µ, ±, ↑, and ↓.
The 24 user-definable characters are uploaded by the
user into on-chip RAM through the serial interface and
are lost when the device is powered down. As well as
custom 5 x 7 characters, the user-definable fonts can
control up to 35 custom segments, bar graphs, or
graphics.
Annunciator segments have individual, independent
control, so any combination of annunciators can be lit.
Annunciators can be off, lit, or blink either in phase or
out of phase with the cursor. The blink-speed control is
software selectable to be one or two blinks per second
(OSC = 4MHz).
DP segments can be lit or off, but have no blink control.
A DP segment is set by the same command that writes
the digit’s 5 x 7 matrix character.
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
Pin Description (continued)
PINNAMEFUNCTION
OSC1Multiplex Clock Input 1. To use the internal oscillator, connect capacitor COSC from OSC1 to GND. To
use the external clock, drive OSC1 with a 2MHz-to-8MHz CMOS clock.OSC2Multiplex Clock Input 2. Connect resistor ROSC from OSC2 to GND.
GRID 1GRID 2GRID 3GRID 4GRID 5GRID 6GRID 7GRID 8
GRID 10GRID 9GRID 11GRID 12GRID 13GRID 14GRID 15GRID 16
Figure1. Example of a One-Digit-per-Grid Display
The cursor segment is controlled differently. A single
register selects one digit’s cursor from the entire dis-
play, and that can be lit either continuously or blinking.
All the other digits’ cursors are off.
The designations of DP, cursor, and annunciator are
interchangeable. For example, consider an application
requiring only one DP lit at a time, but the DP needs to
blink. The DP function does not have blink capability.
Instead, the DP segments on the display are routed
(using the output map) to the cursor function. In this
case, the DP segments are controlled using the cursor
register.
The output of the controller is a 4-wire serial stream that
interfaces to industry-standard, shift-register, high-volt-
age grid/anode VFD tube drivers (Figure 4). This inter-
face uses three outputs to transfer and latch grid and
anode data into the tube drivers, and a fourth output
that enables/disables the tube driver outputs (Figure 5).
The enable/disable control is modulated by the
MAX6852 for both PWM intensity control and interdigit
blanking, and disables the tube driver in shutdown. The
controller multiplexes the display by enabling each grid
of the VFD in turn for 100µs (OSC = 4MHz) with the cor-
rect segment (anode) data. The data for the next grid is
transferred to the tube drivers during the display time of
the current grid.
The controller uses an internal output map to match any
tube-driver’s shift-register grid/anode order, and is
therefore compatible with all VFD internal chip-in-glass
or external tube drivers.
The MAX6852 provides five high-current output ports,
which can be configured for a variety of functions:
The PUMP output can be configured as either an
80kHz (OSC = 4MHz) clock intended for DC-DC con-
verter use, the 4-wire serial interface’s DOUT data out-
put, or a general-purpose logic output.
The PHASE1 and PHASE2 outputs can be individually
configured as either 10kHz PWM outputs (OSC =
4MHz) intended for filament driving, blink status out-
puts, or general-purpose logic outputs.
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller

GRID 1GRID 2GRID 3GRID 4GRID 5GRID 6GRID 7GRID 8
Figure2. Example of a Two-Digits-per-Grid Display (8 Grids, 16 Digits)°FpHmW4 ANNUNCIATOR SEGMENTS
DECIMAL POINT (DP) SEGMENT
CURSOR SEGMENT
5 x 7 MATRIX CHARACTER
WITH 35 SEGMENTS
Figure3. Digit Structure with 5 ✕ 7 Matrix Character, DP
Segment, Cursor Segment, Four Annunciators
MAX6852
VFCLK
VFDOUT
VFLOAD
DIN
SCLK
VFBLANK
VFDIN
VFCLK
VFLOAD
VFBLANK
MICROCONTROLLERVFD TUBE DRIVER
DOUT
SCLK
VFD TUBE
GRID/
ANODE
DRIVERS
Figure4. Connection of the MAX6852 to VFD Driver and VFD Tube
MAX6852
The PORT0 and PORT1 outputs can be individually
configured as either 625Hz, 1250Hz, or 2500Hz clocks
(OSC = 4MHz) intended for buzzer driving, the 4-wire
serial interface’s DOUT data output, blink or shutdown
status outputs, or general-purpose logic outputs.
Display Modes

The MAX6852 has two display modes (Table 1), select-
ed by the M bit in the configuration register (Table 21).
The display modes trade the maximum allowable num-
ber of digits (96/2 mode) against the availability of
annunciator segments (48/1 mode). Table 2 is the reg-
ister address map.
Initial Power-Up

On initial power-up, all control registers are reset, the
display segment and annunciator data are cleared,
intensity is set to minimum, and shutdown is enabled
(Table 3).
Character Registers

The MAX6852 uses 48 character registers (48/1 mode)
(Table 4) or 96 character registers (96/2 mode) (Table
5) to store the 5 x 7 characters (Table 6). Each digit is
represented by 1 byte of memory. The data in the char-
acter registers does not control the character segments
directly. Instead, the register data is used to address a
character generator, which stores the data of the 128-
character font (Table 7). The lower 7 bits of the charac-
ter data (D6 to D0) select a character from the font
table. The most significant bit (MSB) of the register data
(D7) controls the DP segment of the digit; it is set to
light the DP, cleared to leave it unlit.
The character registers address maps are shown in
Table 4 (48/1 mode) and Table 5 (96/2 mode).
In 48/1 mode, the character registers use a single
address range 0x20 to {0x20 + g}, where g is the value
in the grids register (Table 24). The 48/1 mode upper
address limit, when g is 0x2F, is therefore 0x4F. The
address range 0x50 to 0x7F is used for annunciator
data in 48/1 mode.
In 96/2 mode, the character registers use two address
ranges. The first row’s address range is 0x20 to
{0x20+g}. The second row’s address range is 0x50 to
{0x50+g}. Therefore, in 96/2 mode, the character regis-
ters are only one contiguous memory range when a 48-
grid display is used.
Character Generator Font Mapping

The font is a 5 x 7 matrix comprising 104 characters in
ROM, and 24 user-definable characters. The selection
from the total of 128 characters is represented by the
lower 7 bits of the 8-bit digit registers. The MSB, shown
as x in the ROM map (Table 7), controls the DP seg-
ment of the digit; it is set to light the DP, cleared to
leave it unlit.
The character map follows the Arial font for 96 charac-
ters in the x0100000 through x1111111 range. The first
32 characters map the 24 user-definable positions
(RAM00 to RAM23), plus eight extra common charac-
ters in ROM.
User-Defined Fonts

The 24 user-definable characters are represented by
120 entries of 7-bit data, five entries per character, and
are stored in the MAX6852’s internal RAM.
The 120 user-definable font data entries are written and
read through a single register, address 0x05. An
autoincrementing font address pointer in the MAX6852
indirectly accesses the font data. The font address
pointer can be written, setting one of 120 addresses
between 0x00 and 0xF7, but cannot be read back. The
font data is written to and read from the MAX6852 indi-
rectly, using this font address pointer. Unused font
locations can be used as general-purpose scratch
RAM, noting that the font registers are only 7 bits wide,
not 8.
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller

SERIAL-TO-PARALLEL SHIFT REGISTER
LATCHES
VFCLK
VFDIN
VFLOAD
VFBLANK
VFD TUBE DRIVER
VFD TUBE SIMPLIFIED
Figure5. Block Diagram of VFD Tube Driver and VFD Tube
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
DISPLAY
MODEMAXIMUM NO. OF DIGITSMAXIMUM NO. OF
ANNUNCIATORS
MAXIMUM NO.
OF GRIDS
DIGITS COVERED
BY EACH GRID
48/1 mode
48 digits, each with a DP segment and a cursor
segment4 per digit1 digit per grid
96/2 mode
96 digits, each with a DP segment and a cursor
segmentNone
48 grids
2 digits per grid
Table 1. Display Modes
COMMAND ADDRESSREGISTER
D15D14D13D12D11D10D9D8
HEX
CODE

No-opR/W00000000x00
VFBLANK polarityR/W00000010x01
IntensityR/W00000100x02
GridsR/W00000110x03
ConfigurationR/W00001000x04
User-defined fontsR/W00001010x05
Output mapR/W00001100x06
Display test and device IDR/W00001110x07
PUMP registerR/W00010000x08
Filament duty cycleR/W00010010x09
PHASE1R/W00010100x0A
PHASE2R/W00010110x0B
PORT0R/W00011000x0C
PORT1R/W00011010x0D
Shift limitR/W00011100x0E
CursorR/W00011110x0F
Factory reserved. Do not write to register.X00100000x10
Table 2. Register Address Map

Table 8 shows how to use the single user-defined font
register 0x05 to set the font address pointer, write font
data, and read font data. A read action always returns
font data from the font address pointer position. A write
action sets the 7-bit font address pointer if the MSB is
set, or writes 7-bit font data to the font address pointer
position if the MSB is clear.
The font address pointer autoincrements after a valid
access to the user-definable font data. Autoincrementing
allows the 120-font data entries to be written and read
back very quickly because the font pointer address need
only be set once. After the last data location 0xF7 has
been written, further font data entries are ignored until the
font address pointer is reset. If the font address pointer is
set to an out-of-range address by writing data in the 0xF8
to 0xFF range, then address 0x80 is set instead (Table 9).
Table 10 shows the user-definable font pointer base
addresses.
Table 11 shows an example of data (characters 0, 1,
and 2) being stored in the first three user-defined font
locations, illustrating the orientation of the data bits.
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
REGISTER DATAREGISTERPOWER-UP CONDITIONCOMMAND
ADDRESSD7D6D5D4D3D2D1D0

VFBLANK polarityVFBLANK is high to disable the
display0x01XXXXXX00
Intensity1/16 (min on)0x02XXXX0000
GridsDisplay has 1 grid0x03XX000000
ConfigurationShutdown enabled,
configuration unlocked0x041000X000
User-defined font
address pointer
Address 0x80; pointing to the
first user-defined font location0x0510000000
User-defined fontsAll 24 characters blank—00000000
Output map pointerPointing to first entry address0x0610000000
Output map dataPredefined for 40-digit display—See Table 30 for power-up patterns.
Display testNormal operation0x07XXXXXXX0
PUMPGeneral-purpose output, logic0x0800000000
Filament duty cycleMinimum duty cycle0x0900000001
PHASE1General-purpose output, logic0x0A00000000
PHASE2General-purpose output, logic0x0B00000000
PORT0General-purpose output, logic0x0C00000000
PORT1General-purpose output, logic0x0D00000001
Shift limit1 output bit0x0EX0000001
CursorOff0x0F01100000
Character and
annunciator dataClear0x2000000000
UP TO
UP TO————————
Character and
annunciator dataClear0x7F00000000
Table 3. Initial Power-Up Register Status

Table 12 shows the six sequential write commands
required to set a MAX6852’s font character RAM02 with
the data to display character 2 given in Table 7.
Cursor Register

The cursor register controls the behavior of the cursor
segments (Table 13). The MAX6852 controls 48 cursors
in 48/1 mode, and 96 cursors in 96/2 mode. The cursor
register selects one digit’s cursor to be lit either contin-
uously or blinking. All the other digits’ cursors are off.
The 7 least significant bits (LSBs) of the cursor register
identify the cursor position. The MSB is clear for the
cursor to be on continuously, and set for the cursor to
be lit only during the first half of each blink period.
The valid cursor position address range is contiguous:
0 to 47 (0x00 to 0x2F) for the 1st digit row, and 48 to 95
(0x30 to 0x5F) for the 2nd digit row. If the cursor regis-
ter is programmed with an out-of-range value of 95 to
127 (0x60 to 0x7F), then all cursors are off.
Annunciator Registers

The annunciator registers are organized in bytes, with
each segment of each grid being represented by 2
bits. Thus, the four annunciators segments allowed for
each grid are represented by exactly 1 byte (Table 14).
Annunciators are only available in 48/1 mode. The
annunciator address map is shown in Table 4.
Configuration Register

The configuration register is used to enter and exit shut-
down, lock the key VFD configuration settings, select
the blink rate, globally clear the digit and annunciator
data, reset the blink timing, and select between 48/1
and 96/2 display modes (Table 15).
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
COMMAND ADDRESSREGISTERD15D14D13D12D11D10D9D8
HEX
CODE

Digit 0 5 x 7 matrix characterR/W01000000x20
Digit 1 5 x 7 matrix characterR/W01000010x21
Digit 2 5 x 7 matrix characterR/W01000100x22
UP TO
—————————
Digit 45 5 x 7 matrix characterR/W10011010x4D
Digit 46 5 x 7 matrix characterR/W10011100x4E
Digit 47 5 x 7 matrix characterR/W10011110x4F
Digit 0 annunciatorsR/W10100000x50
Digit 1 annunciatorsR/W10100010x51
Digit 2 annunciatorsR/W10100100x52
UP TO
—————————
Digit 45 annunciatorsR/W11111010x7D
Digit 46 annunciatorsR/W11111100x7E
Digit 47 annunciatorsR/W11111110x7F
Table 4. Character and Annunciator Register Address Map in 48/1 Mode
COMMAND ADDRESSREGISTERD15D14D13D12D11D10D9D8
HEX
CODE

Digit 0 5 x 7 matrix character, 1st rowR/W01000000x20
Digit 1 5 x 7 matrix character, 1st rowR/W01000010x21
Digit 2 5 x 7 matrix character, 1st rowR/W01000100x22
UP TO
—————————
Digit 45 5 x 7 matrix character, 1st rowR/W10011010x4D
Digit 46 5 x 7 matrix character, 1st rowR/W10011100x4E
Digit 47 5 x 7 matrix character, 1st rowR/W10011110x4F
Digit 0 5 x 7 matrix character, 2nd rowR/W10100000x50
Digit 1 5 x 7 matrix character, 2nd rowR/W10100010x51
Digit 2 5 x 7 matrix character, 2nd rowR/W10100100x52
UP TO
—————————
Digit 45 5 x 7 matrix character, 2nd rowR/W11111010x7D
Digit 46 5 x 7 matrix character, 2nd rowR/W11111100x7E
Digit 47 5 x 7 matrix character, 2nd rowR/W11111110x7F
Table 5. Character Register Address Map in 96/2 Mode
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
REGISTER DATAMODECOMMAND ADDRESSD7D6D5D4D3D2D1D0

Writing character data to use font map
data with DP segment unlit
0x20 to 0x4F (48/1 mode)
0x20 to 0x7F (96/2 mode)0
Writing character data to use font map
data with DP segment lit
0x20 to 0x4F (48/1 mode)
0x20 to 0x7F (96/2 mode)1
Bits D6 to D0 select font characters 0 to 127
Table 6. Character Registers Format
Shutdown Mode (S Data Bit D0) Format

The S bit in the configuration register selects shutdown
or normal operation (Table 16). The display driver can
be programmed while in shutdown mode, and shut-
down mode is overridden when in display test mode.
For normal operation, set S bit to 1.
When the MAX6852 is in shutdown mode, the multiplex
oscillator is halted at the end of the current 100µs multi-
plex period (OSC = 4MHz), and the VFBLANK output is
used to disable the VFD tube driver. Data in the digit
and other control registers remains unaltered.
If the PUMP output is configured as a square-wave
clock, then the PUMP output is forced low for the dura-
tion of shutdown, and the square-wave clock restored
when the MAX6852 comes out of shutdown.
If the PHASE1 output or PHASE2 output is configured as
a filament driver, then that output is forced low for the
duration of shutdown and the filament drive waveforms
restored when the MAX6852 comes out of shutdown.
When the MAX6852 comes out of shutdown, the exter-
nal VFD tube driver is presumed to contain invalid data.
The VFBLANK output is used to disable the VFD tube
driver for the first multiplex cycle after exiting shutdown,
clearing any invalid data. The next multiplex cycle uses
newly sent valid data.
Configuration Lock (L Data Bit D1) Format

The configuration lock register is a safety feature to
reduce the risk of the VFD configuration settings being
inadvertently changed due to spurious writes if soft-
ware fails. When set, the shift-limit register (0x0E), grids
register (0x03), and output map data (0x06) can be
read but cannot be written. The output map data point-
er itself may be written in order to allow the output map
data to be read back (Table 17).
Blink Rate Selection (B Data Bit D2) Format

The B bit in the configuration register selects the blink
rate of the cursor and annunciator segments. This is the
speed that the segments blink on and off when blinking
is selected for these segments. The frequency of the
multiplex clock OSC and the setting of the B bit (Table
18) determine the blink rate.
Global Blink Timing Synchronization
(T Data Bit D4) Format

Setting the T bit in multiple MAX6852s at the same time
(or in quick succession) synchronizes the blink timing
across all the devices (Table 19). The display multiplex-
ing sequence is also reset, which can give rise to a
one-time display flicker when the register is written.
Global Clear Digit Data (R Data Bit D5) Format

When the R bit (Table 20) is set, the segment and
annunciator data are cleared.
Display Mode (M Data Bit D6) Format

The M bit (Table 21) selects the display modes (Table 1).
The display modes trade maximum allowable number of
digits (mode 96/2) against the availability of annunciator
segments (mode 48/1).
Blink Phase Readback (P Data Bit D7) Format

When the configuration register is read, the P bit
reflects the blink phase pin at that time (Table 22).
Microcontroller 4-Wire Serial Interface

The MAX6852 communicates through an SPI-compati-
ble 4-wire serial interface (Figure 6). The interface has
three inputs, clock (SCLK), chip select (CS), data in
(DIN), and output data out (DOUT). CSmust be low to
clock data into or out of the device, and DIN must be
stable when sampled on the rising edge of SCLK.
DOUT is not a specific pin, but instead, any of the
PUMP, PORT0, or PORT1 outputs can be configured to
be DOUT. DOUT is stable on the rising edge of SCLK.
While the SPI protocol expects DOUT to be high
impedance when the MAX6852 is not being accessed,
DOUT on the MAX6852 is never high impedance. SCLK
and DIN can be used to transmit data to other peripher-
als. The MAX6852 ignores all activity on SCLK and DIN
except when CSis low.
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller
Control and Operation Using the 4-Wire
Interface

Controlling the MAX6852 requires sending a 16-bit
word. The first byte, D15 through D8, is the command
address, and the second byte, D7 through D0, is the
data to be written to the command address (Table 23).
Connecting Multiple MAX6852s to the
4-Wire Bus

Daisy-chain multiple MAX6852s by connecting the
DOUT of one device to the DIN of the next, and driving
SCLK and CSlines in parallel. Data at DIN propagates
through the internal shift registers and appears at
DOUT 15.5 clock cycles later, clocked out on the rising
edge of SCLK. When sending commands to daisy-
chained MAX6852s, all devices are accessed at the
same time. An access requires (16 x n) clock cycles,
where n is the number of MAX6852s connected togeth-
er. To update just one device in a daisy-chain, send the
no-op command (0x00) to the others. Care must be
taken on power-up when daisy-chaining the serial inter-
face in this manner. Configure each MAX6852’s PORT0
or PORT1 outputs, in turn, to act as DOUT before data
propagates through it. For this reason, PORT0 is the
preferred output to configure as DOUT because its out-
put on power-up is low. This means that a daisy-
chained DIN input taking data from an uninitialized
PORT0 output clocks in 16 logic zeros, which is the
safe no-op instruction.
Writing Device Registers

The MAX6852 contains a 16-bit shift register into which
DIN is clocked on the rising edge of SCLK, when CSis
low. When CSis high, transitions on SCLK have no
effect. When CSgoes high, the 16 bits in the shift regis-
ter are parallel loaded into a 16-bit latch. The 16 bits in
the latch are then decoded and executed.
The MAX6852 is written to using the following
sequence:Take SCLK low.Take CSlow. This enables the internal 16-bit shift
register.Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.Take CShigh (while SCLK is still high after clocking
in the last data bit).Take SCLK low.
Figure 7 shows a write operation when 16 bits are
transmitted.RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM09
RAM08
RAM07
RAM05
RAM04
RAM03
RAM02
RAM01
RAM00RAM16
RAM17
RAM18
RAM19
RAM20
RAM21
RAM23
RAM06RAM220110
MSB
LSB
x000x001x010x011x100x101x110x111
Table 7. Character Map
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller

CLK
DIN
D15
= 0
D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DOUTD15 = 0
Figure7. 16-Bit Write Transmission to the MAX6852
If fewer or greater than 16 bits are clocked into the
MAX6852 between taking CSlow and taking CShigh
again, the MAX6852 stores the last 16 bits received,
including the previous transmission(s). The general
case is when n bits (where n > 16) are transmitted to
the MAX6852. The last bits comprising bits {n-15} to {n}
are retained and are parallel loaded into the 16-bit latch
as bits D15 to D0, respectively (Figure 8).
Reading Device Registers

Any register data within the MAX6852 may be read by
sending a logic high to bit D15. The sequence is:Take SCLK low.Take CSlow. This enables the internal 16-bit shift
register.Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is high,
indicating a read command, and bits D14 through
D8 contain the address of the register to read. Bits
D7 to D0 contain dummy data, which is discarded.Take CShigh. Positions D7 through D0 in the shift
register are now loaded with the data in the register
addressed by bits D15 through D8.Take SCLK low.Issue another read or write command (which can be
no-op), and examine the bit stream at DOUT; the
first 8 bits contain the address of the register that
was read (Note:The MSB, which was transmitted as
a 1 for a read command, may read back either as a
1 or a zero). The second 8 bits are the contents of
the register addressed by bits D14 through D8 in
Step 3.
VFD Driver Serial Interface

The VFD driver interface on the MAX6852 is a serial
interface using three output pins, VFLOAD, VFCLK, and
VFDOUT (Figure 9) to drive industry-standard, shift-reg-
tCSStCLtCH
tCP
tCSH
tCSW
tDS
tDH
SCLK
DIN
DN-1D1D0
D15
tCSU
DOUT
Figure6. 4-Wire Serial Interface Timing Diagram
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller

ister, high-voltage grid/anode VFD tube drivers (Figures
3 and 4). The speed of VFCLK is 2MHz when OSC is
4MHz. The maximum speed of VFCLK is 4MHz when
OSC is 8MHz. This interface is used to transfer display
data from the MAX6852 to the VFD tube driver. The ser-
ial interface bit stream output is programmable up to
122 bits, which are labeled DD0–DD121.
The functions of the three interface pins are as follows:
VFCLK is the serial clock output, which shifts data on
its falling edge from the MAX6852’s 122-bit output shift
register to VFLOAD.
VFDOUT is the serial data output. The data changes on
VFCLK’s falling edge, and is stable when it is sampled
by the display driver on the rising edge of VFCLK.
VFLOAD is the latch-load output. VFLOAD is high to
transfer data from the display tube driver’s shift register to
the display driver’s output latch (transparent mode), and
low to retain that data in the display driver’s output latch.
A fourth output pin, VFBLANK, provides gating control
of the tube driver. VFBLANK can be configured to be
either high or low using the VBLANK polarity register
(Table 26) to enable the VFD tube driver. In the default
condition, VFBLANK is high to disable the VFD tube dri-
ver, which is expected to force its driver outputs low to
blank the display without altering the contents of its out-
put latches. In the default condition, VFBLANK is low to
enable its VFD tube driver outputs to follow the state of
the VFD tube driver’s output latches. The VFBLANK
output is used for PWM intensity control and to disable
the VFD tube driver in shutdown.
Multiplex Architecture

The multiplex engine transmits grid and anode control
data to the external VFD driver using the VFCLK, VFD-
OUT, and VFLOAD. The number of data bits m trans-
mitted is set by the user in the shift-limit register (Table
28). Figure 10 is the VFD multiplex timing diagram.
The essential rules for multiplex action are as follows:The external VFD driver’s data latch contains the
data for the current grid being displayed.The VFBLANK input is controlled to provide the
PWM intensity control.The VFCLK and VFDOUT outputs are used to fill the
external VFD driver’s shift register with the multiplex
data for the next grid, during the multiplex timeslot
for the current grid.The VFLOAD output loads the new grid-anode data
pattern at the start of its multiplex cycle.
Grids Register

The grids register sets how many grids are multiplexed
from 1 to 48 (Table 24).
When the grids register is written, the external VFD tube
driver is presumed to contain invalid data. The
VFBLANK output is used to disable the VFD tube driver
for the first multiplex cycle after exiting shutdown, clear-
ing any invalid data. The next multiplex cycle uses
newly sent, valid data. If the grids register is written
with an out-of-range value of 0x30 to 0xFF, then the
value 0x2F is stored instead.
Intensity Register

Digital control of display brightness is provided by
pulse-width modulation of the tube blanking time, which
is controlled by the lower nibble of the intensity register
(Table 25). The modulator scales the VFBLANK output
in 15 steps from a minimum of 1/16 up to 15/16 of each
grid’s multiplex period (Figure 11). Figure 12 shows the
modulator behavior when the VFBLANK polarity regis-
ter is set to 0x00 (Table 26), so VFBLANK is high to dis-
able (blank) the display.
The minimum off-time period of a 1/16 multiplex period
(6.25µs with OSC = 4MHz) is always at the start of the
multiplex cycle. This allows time for slow display drivers
to turn off, and slow display phosphors time to decay
CLK
DINBIT
BIT
N-9N-8N-7N-6N-5N-4N-3N-2
DOUTN-15 = 0
N-15
= 0N-14N-13N-12N-11N-10N-1
N-31N-30N-29N-28N-27N-26N-25N-24N-23N-22N-21N-20N-19N-18N-17N-16
Figure8. Transmission of More than 16 Bits to the MAX6852
MAX6852
4-Wire Interfaced, 5 ✕7 Matrix Vacuum-
Fluorescent Display Controller

between grids. Thus, image ghosting is avoided. If a
display has very slow phosphor, then the allowed decay
time can be doubled by not using a 15/16 duty cycle.
VFBLANK Polarity Register

The VFBLANK polarity register sets the active level of
the VFBLANK output pin (Table 26).
No-Op Register

A write to the no-op register is ignored.
Display-Test and Device ID Register

Writing the display-test and device ID register switches
the drivers between one of two modes: normal and dis-
play test. Display-test mode turns all segments and
annunciators on and sets the duty cycle to 7/16 (half-
power) (Table 27).
Reading the display-test and device ID register returns
the MAX6852 device ID 0b0000 011 that identifies the
driver type, plus the display-test status in the LSB.
Output Shift-Limit Register

The output serial interface is used to transfer display
data from the MAX6852 to the display driver. The serial
interface bit-stream output length is programmable up
to 122 bits, which are labeled DD0–DD121. Set the
number of bits with the shift-limit register, address
0x0E. If the shift-limit register is written with an out-of-
range value 0x7A to 0xFF, then the value 0x79 is stored
instead. Table 28 shows the shift-limit register.
Output Map

The output map comprises 122 words of 7-bit RAM.
The output map data should be written when the
MAX6852 is configured after power-up. Table 29 shows
the output map RAM codes.
tVCL
tVDS
tVCHtVCPtVCSH
tVCSW
VFCLK
VFLOAD
M (M IS VALUE IN SHIFT-LIMIT REGISTER)VFDOUTDD0DD1M-1
Figure9. VFD Interface Timing Diagram
VFCLK
VFDOUT
VFLOAD
DD0DD1DD2DD3DD4DD5DD6DD7DD8DD9DD10M-4M-3M-2M-1M(M IS VALUE IN SHIFT-LIMIT REGISTER)
GRID 1's DATA, SENT DURING GRID 0's TIMESLOT
GRID 0's 100μs MULTIPLEX TIMESLOT
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)START OF NEXT
CYCLE
500ns500ns500ns500ns
100μs TIMESLOT
GRID 0
100μs TIMESLOT
GRID 1
100μs TIMESLOT
GRID N-4
100μs TIMESLOT
GRID N-3
100μs TIMESLOT
GRID N-2
100μs TIMESLOT
GRID N-1
100μs TIMESLOT
GRID 0
Figure10. VFD Multiplex Timing Diagram
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