MAX3775CEE ,Dual-Rate Fibre Channel RepeatersApplicationsMAX3772CEE 0°C to +70°C 16 QSOP-EP1.0625Gbps/2.125Gbps Dual-RateMAX3773CEE 0°C to +70°C ..
MAX3783UCM , 2.7Gbps Dual Mux/Buffer with Loopback
MAX3784AUGE ,+3.3 V, 5 Gbps, PC board equalizerApplicationsChassis Life ExtensionTOP VIEW4.25Gbps Fibre Channel16 15 14 134x Multiplexed 1.25Gbps ..
MAX3784AUTE+ ,5Gbps PCB EqualizerELECTRICAL CHARACTERISTICS(V = +3V to +3.6V, T = 0°C to +85°C. Typical values are at V = +3.3V and ..
MAX3784AUTE+T ,5Gbps PCB EqualizerFeaturesThe MAX3784/MAX3784A 5Gbps equalizers provide♦ Spans 40in (1m) of FR-4 PCBcompensation for ..
MAX3784UGE-T ,5Gbps PCB EqualizerApplicationsChassis Life ExtensionTOP VIEW4.25Gbps Fibre Channel12 11 9104x Multiplexed 1.25Gbps Et ..
MAX735CSA ,-5V/Adjustable, Negative-Output,Inverting, Current-mode PWM Regulatorsapplications.
The MAX735/MAX755 employ a high-performance current-
mode pulse-width modulation ..
MAX735CSA ,-5V/Adjustable, Negative-Output,Inverting, Current-mode PWM Regulatorsapplications,
refer to the MAX635/636/637 data sheet
MAX735CSA+ ,-5V, Inverting, PWM DC-DC ConverterGeneral Description
The MAX735 and MAX755 are CMOS, inverting switch-
mode regulators with inte ..
MAX735CSA+T ,-5V, Inverting, PWM DC-DC ConverterApplications
Board-Level DC-DC Conversion
Battery-Powered Equipment
Computer Peripherals
Ty ..
MAX735CSA-T ,-5V, Inverting, PWM DC-DC Converterfeatures, along with high efficiency and appli-
cations circuits that lend themselves to miniaturi ..
MAX735EPA ,-5V/Adjustable, Negative-Output,Inverting, Current-mode PWM Regulatorsfeatures, along with high efficiency and appli-
cations circuits that lend themselves to miniaturi ..
MAX3772CEE-MAX3773CEE-MAX3773CEE+-MAX3775CEE
Dual-Rate Fibre Channel Repeaters
General DescriptionThe MAX3772–MAX3775 are dual-rate (1.0625Gbps
and 2.125Gbps) fibre channel repeaters. They are opti-
mized for use in fibre channel arbitrated loop applica-
tions and operate from a +3.3V supply. The
MAX3772–MAX3775 exceed fibre channel jitter toler-
ance requirements and can recover data signals with
up to 0.7 unit interval (UI) jitter. The circuit’s fully inte-
grated phase-locked loop (PLL) provides a frequency
lock indication and does not need an external reference
clock. These repeaters provide low-jitter CML clock and
data outputs, and are pin compatible with the MAX3770
repeater (except RATESEL pin and exposed paddle).
The MAX3773/MAX3774 can also be used for imped-
ance transformation between 100Ω(differential) and
150Ω(differential) systems. To reduce the number of
external components, all signal inputs and outputs are
internally terminated. The MAX3772–MAX3775 are
available in 16-pin QSOP-EP packages.
Applications1.0625Gbps/2.125Gbps Dual-Rate
Fibre Channel
Fibre Channel Data Storage Systems
Storage Area Networks
Fibre Channel Hubs
100Ω/150Ω(Differential) Impedance
Transformation
FeaturesPin Selectable 1.0625Gbps/2.125Gbps Dual-Rate
Fibre Channel OperationExceeds Fibre Channel Jitter Tolerance
Requirements1400mV Differential Output Swing+3.0V to +3.6V OperationNo Reference Clock RequiredFrequency Lock Indication290mW Power Consumption (MAX3775) at +3.3V100Ω/150Ω(differential) Input/Output
Terminations
MAX3772–MAX3775
Dual-Rate Fibre Channel Repeaters
Ordering Information
Typical Operating Circuits19-2192; Rev 0; 10/01
Pin Configuration appears at end of data sheet.
Selector Guide appears at end of data sheet.
MAX3772–MAX3775
Dual-Rate Fibre Channel Repeaters
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, 8B/10B data coding, CF= 0.047µF, lock pin loaded with ≥15kΩresistor, all high-speed inputs and outputs
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC........................................................................-0.5V to +5.0V
Pin Voltage Levels (IN±, CF±,
RATESEL, CLKEN, LOCK).....................-0.5V to (VCC+ 0.5V)
Current into LOCK...............................................-1mA to +10mA
CML Output Currents (OUT±, CLK±), ROUT= 75Ω........+22mA
CML Output Currents (OUT±, CLK±), ROUT= 50Ω........+33mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP-EP (derate 18.9mW/°C above +70°C)...702mW
Operating Junction Temperature Range...........-55°C to +150°C
Operating Temperature Range.........................-55°C to +110°C
Storage Temperature Range ............................-55°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
MAX3772–MAX3775
Dual-Rate Fibre Channel Repeaters
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, 8B/10B data coding, CF= 0.047µF, lock pin loaded with ≥15kΩresistor, all high-speed inputs and outputs
MAX3772–MAX3775
Note 1:Supply current includes output currents.
Note 2:Guaranteed by design and characterization.
Note 3:Compliant jitter tolerance pattern in hex (CJTPAT):
Pattern Sequence:Repetitions:
3E AA 2A AA AA6
3E AA A6 A5 A91
87 1E 38 71 E341
87 1E 38 70 BC 78 F4 AA AA AA1
AA AA AA AA AA12
AA A1 55 55 E3 87 1E 38 71 E11
AB 9C 96 86 E61
C1 6A AA 9A A61
Note 4:Meets jitter output specifications with noise applied.
Note 5:K28.7 Pattern: 00 1111 1000.
Note 6:Compliant random pattern in hex (CRPAT):
Pattern Sequence:Repetitions:
3E AA 2A AA AA6
3E AA A6 A5 A91
86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 6516
72 31 9A 95 AB1
C1 6A AA 9A A61
Note 7:Parameter measured with 0.40UI deterministic jitter (patterns other than K28.7), and 0.20UI random jitter (BER = 10 -12)
applied to the input. Jitter is in compliance with the inter-enclosure, fibre channel jitter tolerance (at compliance point αR)
and jitter output (at compliance point αT) specifications (FC-PI rev 10.0). Output jitter is specified as an output total given a
non-zero jitter input.
Note 8:K28.5 Pattern: 00 1111 1010 11 0000 0101
Note 9:Random Pattern in hex (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65
Note 10:Using differential drive over the entire input amplitude range. The input signal bandwidth is limited to 0.75 x (bit-rate) by a 4th-
order Bessel Thompson filter or equivalent. Total jitter (TJ) is the range of the eye pattern where the BER exceeds
10-12. TJ can be estimated as TJ = DJ + 14 x RJ. DJ is deterministic jitter. RJ is a one sigma distribution (RMS) of random jitter.
Note 11:Simulation shows peaking of 0.01dB max. Characterization results limited by test equipment.
Dual-Rate Fibre Channel Repeaters
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, 8B/10B data coding, CF= 0.047µF, lock pin loaded with ≥15kΩresistor, all high-speed inputs and outputs
AC-coupled, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.)
MAX3772–MAX3775
Dual-Rate Fibre Channel Repeaters10k100k1M10M
2.125Gbps JITTER TRANSFER
vs. FREQUENCYMAX3772-75 toc01
FREQUENCY (Hz)
JITTER ATTENUATION (dB)
10k100k1M10M
1.0625Gbps JITTER TRANSFER
vs. FREQUENCYMAX3772-75 toc02
FREQUENCY (Hz)
JITTER ATTENUATION (dB)
10k1M10M
1.0625Gbps JITTER TOLERANCEMAX3772 toc04
FREQUENCY (Hz)
SINUSOIDAL JITTER (UIp-p)
100k
OUTPUT EYE DIAGRAM AT
OUT± (2.125Gbps CRPAT)MAX3772-75 toc05
MAX3772-75 toc06
OUTPUT EYE DIAGRAM AT
OUT± (1.0625Gbps CRPAT)1E-12
1E-10
1E-11
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
2.125Gbps OUTPUT JITTER
BATHTUB PLOTMAX3772-75 toc07
DATA-CROSSING TIME RELATIVE TO
FIRST ZERO CROSSING (UI)
BIT ERROR RATE0.40.20.60.81.0
1E-12
1E-10
1E-11
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1.0625Gbps OUTPUT JITTER
BATHTUB PLOTMAX3772-75 toc08
DATA-CROSSING TIME RELATIVE TO
FIRST ZERO CROSSING (UI)
BIT ERROR RATE0.40.20.60.81.0
Typical Operating Characteristics(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
MAX3772–MAX3775
Detailed DescriptionFigure 2 shows the functional block diagram of the
MAX3772–MAX3775 fibre channel repeaters. They con-
sist of a fully integrated PLL, CML input and output
buffers, and a data latch. The PLL consists of a com-
bined phase detector (PD) and frequency detector
(FD), a loop filter, and a voltage-controlled oscillator
(VCO). The input and output signal buffers employ low-
noise CML architecture and are terminated on-chip.
Phase and Frequency DetectorThe frequency difference between the VCO clock and
the received data is derived by sampling the in-phase
and quadrature VCO outputs on the edges of the input
data signal. The FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the PD produces a voltage proportion-
al to the phase difference between the incoming data
and the internal clock. The PLL drives this error voltage
to zero, aligning the recovered clock to the center of
the incoming eye.
Dual-Rate Fibre Channel Repeaters
Pin DescriptionFigure 1. Example of Output Signal with Matched Output Loads
