MAX3748AETE-T ,Compact 155Mbps to 4.25Gbps Limiting AmplifierApplications#Denotes a RoHS-compliant device that may include lead thatis exempt under the RoHS req ..
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MAX3748AETE-T
Compact 155Mbps to 4.25Gbps Limiting Amplifier
General DescriptionThe MAX3748 multirate limiting amplifier functions as a
data quantizer for SONET, Fibre Channel, and Gigabit
Ethernet optical receivers. The amplifier accepts a wide
range of input voltages and provides constant-level
current-mode logic (CML) output voltages with con-
trolled edge speeds.
A received-signal-strength indicator (RSSI) is available
when the MAX3748 is combined with the MAX3744 SFP
transimpedance amplifier (TIA). A receiver consisting of
the MAX3744 and the MAX3748 can provide up to
19dB RSSI dynamic range. Additional features include
a programmable loss-of-signal (LOS) detect, an option-
al disable function (DISABLE), and an output signal
polarity reversal (OUTPOL). Output disable can be
used to implement squelch.
The combination of the MAX3748 and the MAX3744
allows for the implementation of all the small-form-factor
SFF-8472 digital diagnostic specifications using a stan-
dard 4-pin TO-46 header. The MAX3748 is packaged in
a 3mm x 3mm, 16-pin thin QFN package with an
exposed pad.
ApplicationsGigabit Ethernet SFF/SFP Transceiver Modules
Fibre Channel SFF/SFP Transceiver Modules
Multirate OC-3 to OC-48-FEC SFF/SFP
Transceiver Modules
FeaturesSFP Reference Design Available16-Pin TQFN Package with 3mm x 3mm FootprintSingle 3.3V Supply Voltage86ps Rise and Fall TimeLoss of Signal with Programmable ThresholdRSSI Interface (with MAX3744 TIA)Output DisablePolarity Select8.7psP-PDeterministic Jitter (4.25Gbps)
MAX3748
Compact 155Mbps to 4.25Gbps
Limiting Amplifier
Ordering Information
Typical Operating Circuits19-2717; Rev 6; 6/11
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGE
MAX3748HETE#G16* -40°C to +85°C 16 TQFN-EP**
MAX3748ETE -40°C to +85°C 16 TQFN-EP**
H = hybrid lead-free package. *See Detailed Description for
more information. The MAX3748H is the MAX3748 in a hybrid
lead-free package.
#Denotes a RoHS-compliant device that may include lead that
is exempt under the RoHS requirements.
**EP = Exposed pad.
Functional Diagram and Pin Configuration appear at end of
data sheet.MAX3744 TIA
DS1858
3-INPUT DIAGNOSTIC
MONITOR
3kΩ
0.1μF
IN+
IN-
RSSITHDISABLELOS
0.1μF
OUTPOLCAZ1CAZ2VCC
GND
4.7kΩ TO 10kΩ
LOS
VCC_HOST
OUT+50Ω
0.1μF
OUT-50Ω
0.1μFSERDES
RTH
SUPPLY FILTERHOST FILTER
VCC_RX
4-PIN TO HEADER
HOST BOARDSFP OPTICAL RECEIVER
MAX3748
Typical Operating Circuits continued at end of data sheet.
MAX3748
Compact 155Mbps to 4.25Gbps
Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ωto VCC, CAZ= 0.1µF, typical values are at
+25°C, VCC= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB=
0.75 ✕2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB= 0.75 ✕data rate for data rates > 3.2Gbps.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage (VCC).................................-0.5V to +6.0V
Voltage at IN+, IN-..........................(VCC- 2.4V) to (VCC+ 0.5V)
Voltage at DISABLE, OUTPOL, RSSI,
CAZ1, CAZ2, LOS, TH............................-0.5V to (VCC+ 0.5V)
Current into LOS...................................................-1mA to +9mA
Differential Input Voltage (IN+ - IN-).....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-)...............................................-25mA to +25mA
Continuous Power Dissipation (TA= +70°C)
TQFN (derate 17.7mW above +70°C)..............................1.4W
Operating Junction Temperature Range (TJ)....-55°C to +150°C
Storage Ambient Temperature Range (Ts)........-55°C to +150°C
Lead Temperature (soldering, 10s).................................+260°C
Soldering Temperature (reflow)
TQFN............................................................................+240°C
Hybrid TQFN................................................................+250°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSingle-Ended Input Resistance Single ended to VCC 42 50 58
Input Return Loss Differential, f < 3GHz, DUT is powered on 13 dB
Input Sensitivity VIN-MIN (Note 1) 5 mVP-P
Input Overload VIN-MAX (Note 1) 1200 mVP-P
Single-Ended Output Resistance Single ended to VCC 42 50 58
Output Return Loss Differential, f < 3GHz, DUT is powered on 10 dB
Differential Output Voltage 600 780 1200 mVP-P
Differential Output Signal when
Disabled
Outputs AC-coupled, VIN-MAX applied to
input (Note 2) 10 mVP-P
K28.5 pattern at 4.25Gbps 8.7 25
K28.5 pattern at 3.2Gbps 8.5 25 23- 1 PRBS equivalent pattern at 2.7Gbps
(Note 4) 9.3 30
K28.5 pattern at 2.1Gbps 7.8 25
Deterministic Jitter
(Notes 2, 3) DJ 23- 1 PRBS equivalent pattern at 155Mbps 25 50
psP-P
Input = 5mVP-P 6.5 Random Jitter
(Note 5) Input = 10mVP-P 3 psRMS
20% to 80%, 4.25Gbps
3.1875GHz Bessel input filter
VIN = 20mVP-P
60 Data Output Transition Time
20% to 80% (Note 2) 86 115
ps
Input-Referred Noise 185 μVRMS
CAZ = open 70 Low-Frequency Cutoff CAZ = 0.1μF 0.8 kHz
(Note 6) 32 49 Power-Supply Current ICCLOS disabled 37 mA
Power-Supply Noise Rejection PSNR f < 2MHz 26 dB
MAX3748
Compact 155Mbps to 4.25Gbps
Limiting Amplifier
Note 1:Between sensitivity and overload, all AC specifications are met.
Note 2:Guaranteed by design and characterization.
Note 3:The deterministic jitter caused by this filter is not included in the DJ generation specifications (input).
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ωto VCC, CAZ= 0.1µF, typical values are at
+25°C, VCC= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB=
0.75 ✕2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB= 0.75 ✕data rate for data rates > 3.2Gbps.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOSS OF SIGNAL at 4.25Gbps K28.5 pattern (Note 2) LOS Hysteresis10log (VDEASSERT/VASSERT)1.25 2.2dB
LOS Assert/Deassert Time(Note 8)2100μs
LOS AssertRTH = 280k18.5 mVP-P
LOS DeassertRTH = 280k28mVP-P
LOSS OF SIGNAL at 2.5Gbps (Notes 2, 7) LOS Hysteresis 10log (VDEASSERT/VASSERT)1.25 2.2 dB
LOS Assert/Deassert Time (Note 8) 2 100 μs
Low LOS Assert Level RTH = 20k2.8 4.1 mVP-P
Low LOS Deassert Level RTH = 20k 6.7 11.6 mVP-P
Medium LOS Assert Level RTH = 28010.3 15.2 mVP-P
Medium LOS Deassert Level RTH = 280 25 38.6 mVP-P
High LOS Assert Level RTH = 8022.8 38.3 mVP-P
High LOS Deassert Level RTH = 80 65.2 99.3 mVP-P
LOSS OF SIGNAL at 155Mbps (Note 7)LOS Hysteresis 10log (VDEASSERT/VASSERT) 2.1 dB
LOS Assert/Deassert Time (Note 8) 20 μs
Low LOS Assert Level RTH = 20k 3.5 mVP-P
Low LOS Deassert Level RTH = 20k 5.6 mVP-P
Medium LOS Assert Level RTH = 280 13.3 mVP-P
Medium LOS Deassert Level RTH = 280 21.2 mVP-P
High LOS Assert Level RTH = 80 33.3 mVP-P
High LOS Deassert Level RTH = 80 55.5 mVP-P
RSSIRSSI Current Gain (Note 9) ARSSI ARSSI = IRSSI/ICM_RSSI 0.03
ICM_INPUT < 6.6mA -31 +33Input-Referred RSSI Current
Stability
IRSSI/ARSSI
(Note 10) ICM_INPUT > 6.6mA -73 +90 μA
TTL/CMOS I/OLOS Output High Voltage VOH RLOS = 4.7k to10k to VCC_host (3V) 2.4 V
LOS Output Low Voltage VOL RLOS = 4.7k to10k to VCC_host (3.6V) 0.4 V
LOS Output Current RLOS = 4.7k to10k to VCC_host (3.3V);
IC is powered down 40 μA
DISABLE Input High VIH 2.0 V
DISABLE Input Low VIL 0.8 V
DISABLE Input Current RLOS = 4.7k to 10k to VCC_host 10 μA
MAX3748
Compact 155Mbps to 4.25Gbps
Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ωto VCC, CAZ= 0.1µF, typical values are at
+25°C, VCC= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB=
0.75 ✕2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB= 0.75 ✕data rate for data rates > 3.2Gbps.)
Note 4:223- 1 PRBS pattern was substituted by K28.5 pattern to determine the high-speed portion of the deterministic jitter. The
low-speed portion of the DJ (baseline wander) was obtained by measuring the eye width difference between outputs gen-
erated using K28.5 and 223- 1 PRBS patterns.
Note 5:Random jitter was measured without using a filter at the input.
Note 6:The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate VCC
(see Figure 1).
Note 7:Unless otherwise specified, the pattern for all LOS detect specifications is 223- 1 PRBS.
Note 8:The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2.
Note 9:ICM_INPUTis the input common mode. IRSSIis the current at the RSSI output.
Note 10:Stability is defined as variation over temperature and power supply with respect to the typical gain of the part.
MAX3748
Compact 155Mbps to 4.25Gbps
Limiting Amplifier
Typical Operating Characteristics(TA= +25°C and VCC= 3.3V, unless otherwise specified.)
SUPPLY CURRENT
vs. TEMPERATUREMAX3748 toc01
TEMPERATURE (°C)
CURRENT (mA)806070-1001020304050-30-20
TRANSFER FUNCTION
MAX3748 toc02
DIFFERENTIAL INPUT (mVP-P)
DIFFERENTIAL OUTPUT (mV
P-P432
OUTPUT VOLTAGE vs. INPUT VOLTAGE
RANDOM JITTER vs. TEMPERATURE
(INPUT LEVEL 10mVP-P)MAX3748 toc03
TEMPERATURE (°C)
RANDOM JITTER (ps
RMS80706050403020100-10-20-30
RANDOM JITTER
vs. INPUT AMPLITUDE
MAX3748 toc04
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
RANDOM JITTER (ps
RMS2010
BIT-ERROR RATIO vs. INPUT VOLTAGE
MAX3748 toc05
INPUT VOLTAGE (mVP-P)
BIT-ERROR RATIO (10
DETERMINISTIC JITTER vs. INPUT
COMMON-MODE VOLTAGE (VCC TO VCC - 0.8V)
MAX3748 toc06
COMMON-MODE VOLTAGE (VCC + x)
DETERMINISTIC JITTER (ps
P-P
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3748 toc07
50ps/div
100mV/div
3.2Gbps, 223 - 1 PRBS, 5mVP-P
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)MAX3748 toc08
50ps/div
100mV/div
3.2Gbps, 223 - 1 PRBS, 1200mVP-P
OUTPUT EYE DIAGRAM (MINIMUM INPUT)MAX3748 toc09
100ps/div
100mV/div
2.7Gbps, 223 - 1 PRBS, 5mVP-P
MAX3748
Compact 155Mbps to 4.25Gbps
Limiting Amplifier
Typical Operating Characteristics (continued)(TA= +25°C and VCC= 3.3V, unless otherwise specified.)
OUTPUT EYE DIAGRAM WITH MAXIMUM INPUT
(DATA RATE OF 2.6667Gbps)MAX3748 toc10
50ps/div
100mV/div
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
OUTPUT EYE DIAGRAM AT +100°C
(MINIMUM INPUT)MAX3748 toc11
50ps/div
100mV/div
3.2Gbps, 223 - 1 PRBS, 5mVP-P
ASSERT/DEASSERT LEVELS vs. RTHMAX3748 toc12
RTH (kΩ)
ASSERT/DEASSERT (mV
P-P
ASSERT
DEASSERT
INPUT RETURN GAIN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -40dBm)MAX3748 toc13
FREQUENCY (Hz)
GAIN (dB)
100M10G
OUTPUT
DISABLED
OUTPUT RETURN GAIN vs. FREQUENCY (SDD22)
(INPUT SIGNAL LEVEL = -40dBm)MAX3748 toc14
FREQUENCY (Hz)
GAIN (dB)
100M10G
DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE
(2.667Gbps, K28.5)MAX3748 toc15
INPUT OFFSET VOLTAGE (mVP-P)
DETERMINISTIC JITTER (ps
P-P20-2-46
LOS HYSTERESIS vs. TEMPERATURE
(2.667bps, 210 - 1 PRBS)MAX3748 toc16
TEMPERATURE (°C)
10LOG (DEASSERT/ASSERT) (dB)80706050403020100-10-20-30
RTH = 20kΩRTH = 80Ω
RTH = 280Ω
RSSI CURRENT GAIN vs. INPUT TIA CURRENT
(MAX3744 AND MAX3748)
MAX3748 toc17
INPUT TIA CURRENT (μA)
OUTPUT RSSI CURRENT (
MAX3748
Compact 155Mbps to 4.25Gbps
Limiting Amplifier
Pin Description
PIN NAMEFUNCTION1, 4, 12 VCCSupply Voltage IN+ Noninverted Input Signal, CML IN- Inverted Input Signal, CML
5 TH Loss-of-Signal Threshold Pin. Resistor to ground (RTH) sets the LOS threshold. Connecting this pin to
VCC disables the LOS circuitry and reduces power consumption.
6 DISABLE
Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS
function remains active when the outputs are disabled. If routed through the DS1858/DS1859
controller IC, no additional ESD protection is required.
7 LOS
Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert
threshold set by the TH input. The output is open collector (Figure 5). If routed through the
DS1858/DS1859 controller IC, no additional ESD protection is required.
8, 16 GND Supply Ground
9 OUTPOL Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting
amplifier and connect to VCC for normal operation.
10 OUT- Inverted Data Output, CML
11 OUT+ Noninverted Data Output, CML
13 RSSI
Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced
voltage proportional to photodiode current with the MAX3744 by connecting an external resistor
between this pin and GND.
14 CAZ2
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ1
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1μF. The offset
correction is disabled when the CAZ1 and CAZ2 pins are shorted together.
15 CAZ1
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ2
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1μF. The offset
correction is disabled when the CAZ1 and CAZ2 pins are shorted together.
— EP Exposed Paddle. Connect the exposed paddle to board ground for optimal electrical and thermal
performance.
