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MAX3680EAIMAXIMN/a1888avai+3.3V / 622Mbps / SDH/SONET 1:8 Deserializer with TTL Outputs
MAX3680EAIMAXN/a11avai+3.3V / 622Mbps / SDH/SONET 1:8 Deserializer with TTL Outputs


MAX3680EAI ,+3.3V / 622Mbps / SDH/SONET 1:8 Deserializer with TTL OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical ..
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MAX3680EAI
+3.3V / 622Mbps / SDH/SONET 1:8 Deserializer with TTL Outputs
_________________General Description
The MAX3680 deserializer is ideal for converting
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data in ATM and SDH/SONET applications. Operating
from a single +3.3V supply, this device accepts PECL
serial-clock and data inputs, and delivers TTL clock
and data outputs. It also provides a TTL synchroniza-
tion input that enables data realignment and reframing.
The MAX3680 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 28-pin SSOP
package.
__________________________Applications

622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
______________________________Features
Single +3.3V Supply622Mbps Serial to 77Mbps Parallel Conversion165mW PowerSynchronization Input for Data Realignment and
Reframing
Differential 3.3V PECL Clock and Data InputsTTL Data Outputs and Synchronization Input
MAX3680
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
___________________________________________________________________Typical Operating Circuit
Pin Configuration appears at end of data sheet.
MAX3680
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:
AC characteristics guaranteed by design and characterization.
Terminal Voltage (with respect to GND)
VCC...........................................................................-0.5V to 5V
PECL Inputs (SD+/-, SCLK+/-).................-0.5V to (VCC+ 0.5V)
TTL Input (SYNC).....................................-0.5V to (VCC+ 0.5V)
TTL Outputs (PCLK, PD_).........................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
SSOP (derate 9.52mW/°C above +85°C)......................619mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= +25°C, unless otherwise noted.) (Note 1)
MAX3680
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
__________________________________________Typical Operating Characteristics

(VCC= +3.0V to +3.6V, unless otherwise noted.)
MAX3680
_______________Detailed Description

The MAX3680 deserializer uses an 8-bit shift register,
8-bit parallel output register, 3-bit counter, PECL input
buffers, and TTL input/output buffers to convert
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by eight, causing the out-
put register to latch every eight bits of incoming serial
data.
The synchronization input (SYNC) is used for data
realignment and reframing. When the SYNC signal is
pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
______________________________________________________________Pin Description

Figure 1. Functional Diagram
MAX3680
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs

Figure 2a. Functional Timing Diagram—Normal Operation
MAX3680
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs

Figure 2b. Functional Timing Diagram—SYNC Operation
Figure 3. Timing Parameters
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