IC Phoenix
 
Home ›  MM46 > MAX3420EETG,USB Peripheral Controller with SPI Interface
MAX3420EETG Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
MAX3420EETGMAXIMN/a145avaiUSB Peripheral Controller with SPI Interface


MAX3420EETG ,USB Peripheral Controller with SPI InterfaceApplicationsTime EventsCell Phones PLCs♦ Built-In Endpoint FIFOs:PC Peripherals Set-Top BoxesEP0: C ..
MAX3420EETG+T ,USB Peripheral Controller with SPI InterfaceApplications• Built-In Endpoint FIFOs● Cell Phones• EP0: CONTROL (64 Bytes)● PC Peripherals• EP1: O ..
MAX3421EEHJ+ ,USB Peripheral/Host Controller with SPI InterfaceFeatures in Peripheral Operation♦ Eleven Registers (R21–R31) are Added to the ♦ Built-In Endpoint F ..
MAX3430CSA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX706ESA+ ,Low-Cost, µP Supervisory CircuitsMAX705–MAX708/MAX813L Low-Cost, μP Supervisory Circuits
MAX706ESA+T ,Low-Cost, µP Supervisory CircuitsGeneral Description Beneits and
MAX706ESA-T ,Low-Cost, µP Supervisory CircuitsFeaturesThe MAX705–MAX708/MAX813L microprocessor (µP) ● Supervisory-Function Integration Significan ..
MAX706ESA-T ,Low-Cost, µP Supervisory CircuitsMAX705–MAX708/MAX813L Low-Cost, μP Supervisory Circuits
MAX706MJA ,Low-Cost, uP Supervisory CircuitsFeaturesThe MAX705-MAX708/MAX813L microprocessor (µP) ' µMAX Package: Smallest 8-Pin SOsupervisory ..
MAX706MJA ,Low-Cost, uP Supervisory CircuitsFeaturesThe MAX705-MAX708/MAX813L microprocessor (µP) ' µMAX Package: Smallest 8-Pin SOsupervisory ..


MAX3420EETG
USB Peripheral Controller with SPI Interface
General Description
The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral compliant to USB specification rev 2.0. A
built-in full-speed transceiver features ±15kV ESD pro-
tection and programmable USB connect and discon-
nect. An internal SIE (serial-interface engine) handles
low-level USB protocol details such as error checking
and bus retries. The MAX3420E operates using a regis-
ter set accessed by an SPI interface that operates up to
26MHz. Any SPI master (microprocessor, ASIC, DSP,
etc.) can add USB functionality using the simple 3- or
4-wire SPI interface.
Internal level translators allow the SPI interface to run at
a system voltage between 1.71V and 3.6V. USB timed
operations are done inside the MAX3420E with inter-
rupts provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3420E includes four general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.
The MAX3420E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
TQFP package (7mm x 7mm) and a space-saving 24-
pin TQFN package (4mm x 4mm).
Applications
Features
Microprocessor-Independent USB SolutionComplies with USB Specification Revision 2.0
(Full-Speed Operation)
Integrated Full-Speed USB TransceiverFirmware/Hardware Control of an Internal D+
Pullup Resistor
Programmable 3- or 4-Wire 26MHz SPI InterfaceLevel Translators and VLInput Allow Independent
System Interface Voltage
Internal Comparator Detects VBUS for
Self-Powered Applications
ESD Protection on D+, D-, and VBCOMPInterrupt Output Pin (Level or Programmable
Edge)Allows Polled or Interrupt-Driven SPI
Interface
Intelligent USB Serial Interface Engine (SIE)
Automatically Handles USB Flow Control and
Double Buffering
Handles Low-Level USB Signaling Details
Contains Timers for USB Time-Sensitive
OperationsSo SPI Master Does Not Need to
Time Events
Built-In Endpoint FIFOs:
EP0: CONTROL (64 Bytes)
EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP3: IN, Bulk or Interrupt (64 Bytes)
Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to
Transfer Data Concurrently with USB Transfers
Over the Same Endpoint
SETUP Data Has Its Own 8-Byte FIFO, Simplifying
Firmware
Four General-Purpose Inputs and Four General-
Purpose Outputs
Space-Saving TQFP and TQFN Packages
MAX3420E
USB Peripheral Controller
with SPI Interface

19-3781; Rev 0; 8/05
Cell Phones
PC Peripherals
Microprocessors and
DSPs
Custom USB Devices
Cameras
Desktop Routers
PLCs
Set-Top Boxes
PDAs
MP3 Players
Instrumentation
Ordering Information

*Future product—contact factory for availability.
The MAX3420E connects to any microprocessor using
3 or 4 interface pins (Figure 1). On a simple micro-
processor without SPI hardware, these can be bit-
banged general-purpose I/O pins. Four GPIN and four
GPOUT pins on the MAX3420E more than replace the
µP pins necessary to implement the interface. Although
the MAX3420E SPI hardware includes separate data-in
(MOSI, (Master-Out, Slave-In)) and data-out (MISO,
(Master-In, Slave-Out)) pins, the SPI interface can also
be configured for the MOSI pin to carry bidirectional
data, saving an interface pin. This is referred to as half-
duplex mode.
Two MAX3420E features make it easy to connect to
large, fast chips such as ASICs and DSPs (see Figure
2). First, the SPI interface can be clocked up to 26MHz.
Second, a VLpin and internal level translators allow
running the system interface at a lower voltage than the
3.3V required for VCC.
The MAX3420E provides an ideal method for electrically
isolating a USB interface (Figure3). USB employs flow
control in which the MAX3420E automatically answers
host requests with a NAK handshake, until the micro-
processor completes its data-transfer operations over
the SPI port. This means that the SPI interface can run
at any frequency up to 26MHz. Therefore, the designer
is free to choose the interface operating frequency and
to make opto-isolator choices optimized for cost or per-
formance.
MAX3420E
USB Peripheral Controller
with SPI Interface
Typical Application Circuits

Figure 2. The MAX3420E Connected to a Large Chip
Figure 3. Optical Isolation of USB Using the MAX3420E
Figure 1. The MAX3420E connects to any microprocessor
using 3 or 4 interface pins.
MAX3420E
USB Peripheral Controller
with SPI Interface
Functional Diagram
MAX3420E
USB Peripheral Controller
with SPI Interface
Pin Description

*33pF capacitor will not be required after redesign.
Register Description
The SPI master controls the MAX3420E by reading and
writing 21 registers (Table1). For a complete descrip-
tion of register contents, please refer to the “MAX3420E
Programming Guide.” A register access consists of the
SPI master first writing an SPI command byte, followed
by reading or writing the contents of the addressed
register. All SPI transfers are MSB (most significant bit)
first. The command byte contains the register address,
a direction bit (Read = 0, Write = 1), and the ACKSTAT
bit (Figure4). The SPI master addresses the
MAX3420E registers by writing the binary value of the
register number in the Reg4 through Reg0 bits of the
command byte. For example, to access the IOPINS
(R20) register, the Reg4 through Reg0 bits would be as
follows: Reg4 = 1, Reg3 = 0, Reg2 = 1, Reg1 = 0, Reg0
= 0. The DIR (direction) bit determines the direction for
the data transfer. DIR = 1 means the data byte(s) will
be written to the register, and DIR = 0 means the data
byte(s) will be read from the register. The ACKSTAT bit
sets the ACKSTAT bit in the EPSTALLS (R9) register.
The SPI master sets this bit to indicate that it has fin-
ished servicing a CONTROL transfer. Since the bit is
frequently used, having it in the SPI command byte
improves firmware efficiency. In SPI full-duplex mode,
the MAX3420E clocks out eight USB status bits as the
command byte is clocked in (Figure5). In half-duplex
MAX3420E
USB Peripheral Controller
with SPI Interface
Pin Description (continued)
MAX3420E
mode, these status bits are accessed in the normal
way, as register bits.
The first five registers (R0–R4) access endpoint FIFOs.
To access a FIFO, an initial command byte sets the
register address and then consecutive reads or writes
keep the same register address to access subsequent
FIFO bytes.
The remaining registers (R5–R20) control the operation
of the MAX3420E. Once a register address above R4 is
set in the command byte, successive byte reads or
writes in the same SPI access cycle (SSlow) increment
the register address after every byte read or written. This
incrementing operation continues until R20 is accessed.
Subsequent byte reads or writes continue to access
R20. Note that this auto-incrementing action stops with
the next SPI cycle, which establishes a new register
address. Addressing beyond R20 is ignored.
USB Peripheral Controller
with SPI Interface
Note:
The acc (access) column indicates how the SPIMaster can access the register.
R = Read, RC = Read or Clear, RSC = Read, Set, or Clear.
Writing to an R register (Read-Only) has no effect.
Writing a 1 to an RC bit (Read or Clear) clears the bit.
Writing a zero to an RC bit has no effect.
MAX3420E
USB Peripheral Controller
with SPI Interface
Pin Configurations
MAX3420E
USB Peripheral Controller
with SPI Interface
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
VCC.........................................................................-0.3V to +4V.............................................................................-0.3V to +4V
VBCOMP .................................................................-0.3V to +6V
D+, D-, XI, XO ............................................-0.3V to (VCC + 0.3V)
SCLK, MOSI, MISO, SS, RES, GPOUT3–GPOUT0,
GPIN3–GPIN0, GPX, INT..........................-0.3V to (VL+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin TQFN (derate 20.8mW/°C above +70°C).......1667mW
32-Pin TQFP (derate 20.7mW/°C above +70°C)........1653mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX3420E
USB Peripheral Controller
with SPI Interface
ELECTRICAL CHARACTERISTICS (continued)

(VCC
+2.5V, TA
MAX3420E
USB Peripheral Controller
with SPI Interface
Note 1:
Parameters are 100% production tested at TA= +25°C, and guaranteed by correlation over temperature.
Note 2:
Design guaranteed by bench testing. Limits are not production tested.
Note 3:
At VL= 1.71V to 2.5V, derate all of the SPI timing characteristics by 50%. Not production tested.
Note 4:
The minimum period is derived from SPI timing parameters.
Note 5:
Time-to-exit suspend is dependent on the crystal used.
Note 6:
Redesign in progress to meet USB specification.
TIMING CHARACTERISTICS

(VCC= +3V to +3.6V, VL= +1.71V to +3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, VL=
+2.5V, TA= +25°C.) (Note 1)
*33pF capacitor will not be required after redesign.
MAX3420E
USB Peripheral Controller
with SPI Interfaceest Circuits and Timing Diagrams

Figure 6. Rise and Fall Times
Figure 7. Load for D+/D- AC Measurements
Figure8. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))
MAX3420E
USB Peripheral Controller
with SPI Interface
Typical Operating Characteristics

(VCC
Detailed Description

The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral that complies with the USB specification rev
2.0. ESD protection of ±15kV is provided on D+, D-,
and VBCOMP. The MAX3420E features an internal USB
transceiver and an internal 1.5kΩresistor that connects
between D+ and VCCunder the control of a register bit
(CONNECT). This allows a USB peripheral to control
the logical connection to the USB host.Any SPI master
can communicate with the MAX3420E through the SPI
slave interface that operates in SPI mode (0,0) or (1,1).
An SPI master accesses the MAX3420E by reading and
writing to internal registers. A typical data transfer con-
sists of writing a first byte that sets a register address
and direction with additional bytes reading or writing
data to the register or internal FIFO.
The MAX3420E contains 384 bytes of endpoint buffer
memory, implementing the following endpoints:EP0: 64-byte bidirectional CONTROL endpointEP1: 2 x 64-byte double-buffered BULK/INT
OUT endpointEP2: 2 x 64-byte double-buffered BULK/INT IN
endpointEP3: 64-byte BULK/INT IN endpoint
The choice to use EP1–EP3 as BULK or INTERRUPT
endpoints is strictly a function of the endpoint descrip-
tors that the SPI master returns to the USB host during
enumeration.
The MAX3420E register set and SPI interface is optimized
to reduce SPI traffic. An interrupt output pin, INT, notifies
the SPI master when USB service is required: when a
packet arrives, a packet is sent, or the host suspends or
resumes bus activity. Double-buffered endpoints help
sustain bandwidth by allowing data to move concurrently
over USB and the SPI interface.
VCC

Power the USB transceiver by applying a positive 3.3V
supply to VCC. Bypass VCCto GND with a 1.0µF
ceramic capacitor as close to the VCCpin as possible.
The MAX3420E digital core is powered though the VL
pin. VL also acts as a reference level for the SPI inter-
face and all other inputs and outputs. Connect VLto the
system’s logic-level power supply. Internal level transla-
tors and VLallow the SPI interface and all general-pur-
pose inputs and outputs to operate at a system voltage
between 1.71V and 3.6V.
VBCOMP

The MAX3420E features a USB VBUSdetector input,
VBCOMP. The VBCOMP pin can withstand input volt-
ages up to 6V. Bypass VBCOMP to GND with a 1.0µF
ceramic capacitor. According to USB specification rev
2.0, a self-powered USB device must not power the
1.5kΩpullup resistor on D+ if the USB host turns off
VBUS. VBCOMP is internally connected to a voltage
comparator so that the SPI master can detect the loss
of VBUS(through an interrupt (INT) or checking a bit
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED