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MAX2104
Direct-Conversion Tuner IC for Digital DBS Applications
General DescriptionThe MAX2104 low-cost direct-conversion tuner IC is
designed for use in digital direct-broadcast satellite
(DBS) television set-top box units. Its direct-conversion
architecture reduces system cost compared to devices
with IF-based architectures. The MAX2104 directly con-
verts L-band signals to baseband signals using a
broadband I/Q downconverter. The operating frequency
range extends from 925MHz to 2175MHz.
The IC includes an LNA gain control, I and Q downcon-
verting mixers, lowpass filters with gain control and fre-
quency control, a local oscillator (LO) buffer with a 90°
quadrature network, and a charge-pump based PLL for
frequency control. The MAX2104 also has an on-chip
LO, requiring only an external varactor-tuned LC tank
for operation. The output of the LO drives the internal
quadrature generator and dual modulus prescaler. An
on-chip crystal amplifier drives a reference divider as
well as a buffer amplifier to drive off-chip circuitry. The
MAX2104 is offered in a 48-pin TQFP-EP package.
ApplicationsDirecTV, PrimeStar, EchoStar DBS Tuners
DVB-Compliant DBS Tuners
Broadband Systems
LMDS
FeaturesLow-Cost ArchitectureOperates from Single 5V Supply925MHz to 2175MHz Input Frequency RangeOn-Chip Quadrature Generator, Dual-Modulus
Prescaler (/32, /33)On-Chip Crystal AmplifierPLL Mixer with Gain-Controlled Charge PumpInput Levels: -25dBm to -65dBm per CarrierOver 40dB Gain Control RangeNoise Figure = 11.5dB; IIP3 = 7dBm (at 1550MHz)Automatic Baseband Offset CorrectionLoopthrough Replaces External SplitterCrystal Output Buffer
MAX2104
Direct-Conversion Tuner IC for
Digital DBS ApplicationsPLLIN-
PLLIN+
MOD-
MOD+
GND
IOUT+
IOUT-
VCC
QOUT+
QOUT-
FDOUB
FLCLK
VCC
CFLT
XTL-
XTL+
GND
VCC
RFIN-
RFIN+
GND
GND
QDC-
QDC+14151617181920212223244746454443424140393837
IDC-IDC+GNDGND
RFOUT
CPG1
XTLOUT
CPG2
GC1GC2
INSELFBGNDV
TANK+VRLOTANK-GNDGNDV
PSOUT-PSOUT+
TQFPMAX2104
TOP VIEW
19-1431; Rev 4; 6/05
*Contact factory for availability.
**EP = Exposed paddle.
+Denotes lead-free package.
Functional Diagram appears at end of data sheet.
Pin Configuration
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX2104CCM*0°C to +70°C48 TQFP-EP**C48E-10
MAX2104CCM+0°C to +70°C48 TQFP-EP**C48E-10
MAX2104
Direct-Conversion Tuner IC for
Digital DBS Applications
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= 4.75V to 5.25V, VFB= 2.4V, CIOUT_= CQOUT_= 10pF, fFLCLK= 2MHz, RFIN_ = floating, RIOUT_= RQOUT_= 10kΩ,
VFDOUB= VINSEL= VCPG1= VCPG2= 2.4V, VPLLIN+= VMOD+= 1.3V, VPLLIN-= VMOD-= 1.1V, TA= +25°C. Typical values are at
VCC= 5.0V and TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND .............................................................-0.5V to +7V
All Other Pins to GND.................................-0.3V to (VCC+ 0.3V)
RF1+ to RF1-, RF2+ to RF2-, TANK+ to TANK-,
IDC+ to IDC-, QDC+ to QDC- ............................................±2V
IOUT_, QOUT_ to GND Short-Circuit Duration ......................10s
PSOUT+, PSOUT- to GND Short-Circuit Duration .................10s
Continuous Current (any pin)..............................................20mA
Continuous Power Dissipation (TA= +70°C)
(derate 30.4mW/°C above +70°C)..................................2.43W
Operating Temperature Range...............................0°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
VCPG1= VCPG2= 0.5V
(VMOD+-VMOD-) = -200mV
(VMOD+-VMOD-) = 200mV
Referenced to VCMO
Referenced to VCMO
RSOURCE= 50kΩ, VFLCLK = 1.65V
Referenced to VCMI
Referenced to VCMI
CONDITIONSCharge-Pump Output High
Measured at FBReference Divider Ratio33Prescaler Ratio3232150215Output Voltage High (Note 3)-215-150Output Voltage Low (Note 3)2.162.42.64VCMOCommon-Mode Output Voltage-55Input Current (Note 1)100Input Voltage High (Note 2)-100Input Voltage Low (Note 2)1.081.21.32VCMICommon-Mode Input Voltage4.755.25VCCOperating Supply Voltage-1+1FLCLK Input Current (Note 1)1.45FLCLK Input Voltage Low1.85FLCLK Input Voltage High2.4VIHDigital Input Voltage High0.5VILDigital Input Voltage Low-15+10IINDigital Input Current
UNITSMINTYPMAXSYMBOLPARAMETER190275ICCOperating Supply Current
VCPG1= 0.5V, VCPG2= 2.4V0.240.30.36
VCPG1= 2.4V, VCPG2= 0.5V
VCPG1= VCPG2= 2.4V
0.480.60.72mA
STANDARD DIGITAL INPUTS (FDOUB, INSEL, CPG1, CPG2)
SLEW-RATE-LIMITED DIGITAL INPUTS
DIFFERENTIAL DIGITAL INPUTS (MOD+, MOD-, PLLIN+, PLLIN-)
DIFFERENTIAL DIGITAL OUTPUTS (PSOUT+, PSOUT-)
FREQUENCY SYNTHESIZER
MAX2104
Direct-Conversion Tuner IC for
Digital DBS Applications
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= 4.75V to 5.25V, VFB= 2.4V, CIOUT_= CQOUT_= 10pF, fFLCLK= 2MHz, RFIN_ = floating, RIOUT_= RQOUT_= 10kΩ,
VFDOUB= VINSEL= VCPG1= VCPG2= 2.4V, VPLLIN+= VMOD+= 1.3V, VPLLIN-= VMOD-= 1.1V, TA= +25°C. Typical values are at
VCC= 5.0V and TA= +25°C, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS(VCC = 4.75V to 5.25V, VIOUT_= VQOUT_ = 0.59VP-P, CIOUT_= CQOUT_= 10pF, fFLCLK= 2MHz, RIOUT_= RQOUT_= 10kΩ,
VFDOUB= VINSEL= VCPG1= VCPG2= 2.4V, VPLLIN+= VMOD+= 1.3V, VPLLIN-= VMOD-= 1.1V, TA= +25°C. Typical values are at
VCC= 5.0V and TA= +25°C, unless otherwise noted.)
VCPG1= VCPG2= 0.5V
VCPG1= 0.5V, VCPG2= 2.4V
CONDITIONSCharge-Pump Output Low
Measured at FB
UNITSMINTYPMAXSYMBOLPARAMETER
VCPG1= 2.4V, VCPG2= 0.5V
VCPG1= VCPG2= 2.4V
-0.72-0.6-0.48mA
VGC_= 1V to 4V-50+50IGC_Analog Control Input CurrentµA
Charge-Pump Output Current
Matching Positive to Negative%Measured at FB-55
Charge-Pump Output LeakagenAMeasured at FB-2525
Offset Voltage (Note 1)mV
Differential Output Voltage
SwingVP-PRL= 2kΩdifferential1
Common-Mode Output Voltage
(Note 1)V0.650.85
-50+50
Charge-Pump Output Current
Drive (Note 1)µAMeasured at CP100
ANALOG CONTROL INPUTS (GC_)
BASEBAND OUTPUTS (IOUT+, IOUT-, QOUT+, QOUT-)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
RF FRONT ENDRFIN_ Input Frequency RangefRFIN9252175MHz
VGC1 = VGC2 = +4V (min gain)-20dBmRFIN_ Input Power for 0.59Vp-p
Baseband Levels
Single
carrierVGC1 = VGC2 = +1V (max gain)-68-65dBm
fLO = 2175MHz5
fLO = 1550MHz7RFIN_ Input Third-Order Intercept
(Note 4)IP3RFIN_PRFIN_ = -25dBm per
tonefLO = 950MHz8
dBm
RFIN_ Input Second-Order
Intercept (Note 5)IP2RFIN_PRFIN_ = -25dBm per tone,
fLO = 951MHz15.5dBm
Output-Referred 1dB
Compression Point (Note 6)P1dBOUT_PRFIN_ = -40dBm,
signals within filter bandwidth2dBV
Noise FigureNF
PRFIN_ = -65dBm, fRFIN_ = 1550MHz,
VGC1 = 1V, VGC2 adjusted 0.59Vp-p
baseband level
11.5dB
fRFIN_ = 925MHz10RFIN_ Return Loss (Note 7)fRFIN_ = 2175MHz10dB
LO 2nd H ar moni c Rejection (N ote 8) Average level of VIOUT_, VQOUT_27dBc
LO H al f H ar m oni c Rej ecti on ( N ote 9) Average level of VIOUT_, VQOUT_3138dBc
MAX2104
Direct-Conversion Tuner IC for
Digital DBS Applications
AC ELECTRICAL CHARACTERISTICS (continued)(VCC = 4.75V to 5.25V, VIOUT_= VQOUT_ = 0.59VP-P, CIOUT_= CQOUT_= 10pF, fFLCLK= 2MHz, RIOUT_= RQOUT_= 10kΩ,
VFDOUB= VINSEL= VCPG1= VCPG2= 2.4V, VPLLIN+= VMOD+= 1.3V, VPLLIN-= VMOD-= 1.1V, TA= +25°C. Typical values are at
VCC= 5.0V and TA= +25°C, unless otherwise noted.)f = 925MHzRFOUT Noise Figure (Note 11)f = 925MHz
dBmRFOUT Output Third-Order
Intercept Point (Note 11)
1.8f = 1550MHz
2.5f = 2175MHz
0.5f = 925MHzRFIN_ to RFOUT Gain (Note 11)
Includes effects from baseband filters,
measured at 125kHz baseband4degreesQuadrature Phase Error
Includes effects from baseband filters,
measured at 125kHz baseband1.2dBQuadrature Gain Error
fFLCLK= 2.0625MHz, fC = 31.4MHz
fFLCLK= 1.25MHz, fC = 19.3MHz
fFLCLK= 0.5MHz, fC = 8MHz
-0.5+0.5Deviation from ideal 7th order, Butterworth,
up to 0.7 x fCdBBaseband Frequency Response
(Note 1)
750CIDC_= CQDC_= 0.22µFHzBaseband Highpass Frequency
(Note 1)fIN_BAND= 100Hz to 22.5MHz,
fOUT_BAND= 67.5MHz to 112.5MHzdBRatio of In-Filter-Band
to Out-of-Filter-Band Noise
PARAMETERSYMBOLMINTYPMAXUNITS-10+10LPF -3dB Cutoff-Frequency
Accuracy (Note 1)-10+10
-5.5+5.5
CONDITIONS833Controlled by FLCLK signalMHzLPF -3dB Cutoff-Frequency Range
(Note 1)925MHz < f < 2175MHzdBRFOUT Return Loss (Notes 1, 11)
11.5f = 2175MHzf = 1550MHz
f = 2175MHz
f = 1550MHzIOUT_, QOUT_ΩOutput Real Impedance (Note 1)
LO Leakage Power (Notes 7, 10)-66dBmMeasured at RFIN_
RFOUT PORT (LOOPTHROUGH)
BASEBAND CIRCUITS
MAX2104
Direct-Conversion Tuner IC for
Digital DBS Applications
Note 1:Minimum and maximum values are guaranteed by design and characterization over supply voltage.
Note 2:With external 100Ωtermination resistor.
Note 3:Driving differential load of 10kΩ|| 15pF.
Note 4:Two signals are applied to RFIN_ at fLO- 100MHz and fLO- 199MHz. VGC2= 1V; VGC1is set such that the baseband out-
puts are at 590mVP-P. IM products are measured at baseband outputs but are referred to RF inputs.
Note 5:Two signals are applied to RFIN_ at 1200MHz and 2150MHz. VGC2= 1V, VGC1 is set such that the baseband outputs are
at 590mVP-P. IM products are measured at baseband outputs but are referred to RF inputs.
Note 6:PRFIN_= -40dBm so that front end IM contributions are minimized.
Note 7:Using L64733/L64734 demo board from LSI Logic.
Note 8:Downconverted level, in dBc, of carrier present at fLOx 2, fLO= 1180MHz, fVCO= 590MHz, VFDOUB= 2.4V.
Note 9:Downconverted level, in dBc, of carrier present at fO / 2, fLO= 2175MHz, fVCO= 1087.5MHz, VFDOUB= 2.4V.
Note 10:Leakage is dominated by board parasitics.
Note 11:VCPG1= VCPG2= VFDOUB= VINSEL= 0.5V, fFLCLK= 0.5MHz.
Note 12:Measured at tuned frequency with PLL locked. All phase noise measurements assume tank components have a Q > 50.
AC ELECTRICAL CHARACTERISTICS (continued)(VCC = 4.75V to 5.25V, VIOUT_= VQOUT_ = 0.59VP-P, CIOUT_= CQOUT_= 10pF, fFLCLK= 2MHz, RIOUT_= RQOUT_= 10kΩ,
VFDOUB= VINSEL= VCPG1= VCPG2= 2.4V, VPLLIN+= VMOD+= 1.3V, VPLLIN-= VMOD-= 1.1V, TA= +25°C. Typical values are at
VCC= 5.0V and TA= +25°C, unless otherwise noted.)
LOCAL OSCILLATOR
SYNTHESIZERPARAMETERSYMBOLMINTYPMAXUNITS
At 100kHz offset, fLO= 2175MHz
dBc/HzLO Phase Noise (Notes 7, 12)-75At 10kHz offset, fLO= 2175MHzFigure 1
fRFIN_= 2150MHzdBRFIN_ to LO Input Isolation
(Note 10)
5901180MHzLO Tuning Range (Note 1)7.26MHzCrystal Frequency Range (Note 1)
0.7511.5Load = 10pF ||10kΩ, fXTLOUT = 6MHz VP-PXTLOUT Output Voltage SwingXTLOUT Output Voltage DC
At 1kHz offset, fLO= 2175MHz
MOD+, MOD- Hold Time (Note 1)tHMFigure 1
CONDITIONSMOD+, MOD- Setup Time (Note 1)tSUM
SYNTHESIZER
LOCAL OSCILLATOR
MAX2104
Direct-Conversion Tuner IC for
Digital DBS Applications
NAMEFUNCTIONPIN
Pin DescriptionCFLTExternal Bypass for Internal Bias. Bypass this pin with a 0.1µF ceramic chip capacitor to GND.XTL-Inverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements.XTL+Noninverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements.
5, 9, 10,
15, 16, 32,
40, 41, 46
GNDGround. Connect each of these pins to a solid ground plane. Use multiple vias to reduce inductance
where possible.RFIN-RF Inverting Input. Bypass RFIN- with 47pF capacitor in series with a 75Ωresistor to GND.RFIN+RF Noninverting Input. Connect to 75Ωsource with a 47pF ceramic chip capacitor.QDC-Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC- to QDC+ (pin 12).QDC+Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC+ to QDC- (pin 11).IDC-Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC- to IDC+ (pin 14).IDC+Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC+ to IDC- (pin 13).RFOUTBuffered RF Output. Enabled when INSEL is low.CPG1Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See the
DC Electrical Characteristicssection for available gain settings.XTLOUTBuffered Crystal Oscillator OutputCPG2Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See the
DC Electrical Characteristicssection for available gain settings.GC1Gain Control Input for RF Front End. High-impedance analog input, with an input range of 1V to 4V. See
the AC Electrical Characteristicssection for transfer function.GC2Gain Control Input for Baseband Signals. High-impedance analog input, with an input range of 1V to 4V.
See the AC Electrical Characteristicssection for transfer function.INSELLoopthrough Mode Enable. High-impedance digital input. Drive low to enable the RFOUT buffer and
disable the internal downconverters. Connect to VCCfor normal tuner operation.FLCLKBaseband Filter Cutoff Adjust. Connect to a slew-rate-limited clock source. See the AC Electrical
Characteristicssection for transfer function.FDOUBLO Frequency Doubler. High-impedance digital input. Drive high to enable the LO frequency doubler.
Drive low to disable the doubling function.QOUT-Baseband Quadrature Output. Connect to inverting input of high-speed ADC.QOUT+Baseband Quadrature Output. Connect to noninverting input of high-speed ADC.IOUT-Baseband In-Phase Output. Connect to inverting input of high-speed ADC.IOUT+Baseband In-Phase Output. Connect to noninverting input of high-speed ADC.MOD+PECL Modulus Control. A PECL high on MOD+ sets the dual-modulus prescaler to divide by 32. A PECL
logic low sets the divide ratio to 33. Drive with a differential PECL signal with MOD- (pin 34).
1, 6, 19,
29, 39, 45VCCVCCPower-Supply Input. Connect each pin to a +5V ±5% low-noise supply. Bypass each VCCpin to the
nearest GND with a ceramic chip capacitor.
