MAX19712 ,10-Bit, 22Msps, Full-Duplex, Analog Front-Endapplications operating in full-duplex ♦ Ultra-Low Power50.4mW at f = 22MHz, FD Mode(FD) mode. Optim ..
MAX19713ETN+ ,10-Bit, 45Msps, Full-Duplex, Analog Front-EndApplicationsV 51 20 AD7DDQDN 52 19 AD6● WiMAX CPEs ● Portable Communication QDP 53 18 AD5● 801.11a/ ..
MAX1971EEE ,Dual / 180 Out-of-Phase / 1.4MHz / 750mA Step- Down Regulator with POR and RSI/PFOELECTRICAL CHARACTERISTICS(V = V = V = 5V, R = 100kΩ to IN, R = 100kΩ to IN, V = 0, C = 0.1µF, FBSE ..
MAX1971EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOMAX1970/MAX1971/MAX197219-2297; Rev 1; 2/09Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulat ..
MAX1972EEE ,Dual / 180 Out-of-Phase / 1.4MHz / 750mA Step- Down Regulator with POR and RSI/PFOFeaturesThe MAX1970/MAX1971/MAX1972 dual-output current- Current-Mode, 1.4MHz Fixed-Frequency PWMm ..
MAX1972EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOFeaturesThe MAX1970/MAX1971/MAX1972 dual-output current-♦ Current-Mode, 1.4MHz Fixed-Frequency PWMm ..
MAX494CSD ,Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op AmpsGeneral Description ________
MAX494CSD+ ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op AmpsGeneral Description ________
MAX494CSD+T ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op AmpsApplications *Dice are specified at TA = +25°C, DC parameters only.__________Typical Operating Circ ..
MAX494CSD-T ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op AmpsApplications *Dice are specified at TA = +25°C, DC parameters only.__________Typical Operating Circ ..
MAX494EPD ,Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op AmpsMAX492/MAX494/MAX49519-0265; Rev 2; 9/96Single/Dual/Quad, Micropower,Single-Supply Rail-to-Rail Op ..
MAX494ESD ,Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op AmpsFeatures' Low-Voltage Single-Supply Operation (+2.7V to +6V)The dual MAX492, quad MAX494, and singl ..
MAX19712
10-Bit, 22Msps, Full-Duplex, Analog Front-End
General DescriptionThe MAX19712 is an ultra-low-power, highly integrated
mixed-signal analog front-end (AFE) ideal for wideband
communication applications operating in full-duplex
(FD) mode. Optimized for high dynamic performance
and ultra-low power, the device integrates a dual 10-bit,
22Msps receive (Rx) ADC; dual 10-bit, 22Msps transmit
(Tx) DAC; three fast-settling 12-bit aux-DAC channels
for ancillary RF front-end control; and a 10-bit, 333ksps
housekeeping aux-ADC. The typical operating power in
FD mode is 50.4mW at a 22MHz clock frequency.
The Rx ADCs feature 54.7dB SINAD and 75.6dBc SFDR
at 5.5MHz input frequency with a 22MHz clock frequen-
cy. The analog I/Q input amplifiers are fully differential
and accept 1.024VP-Pfull-scale signals. Typical I/Q
channel matching is ±0.01°phase and ±0.01dB gain.
The Tx DACs feature 72.9dBc SFDR at fOUT= 2.2MHz
and fCLK= 22MHz. The analog I-Q full-scale output volt-
age range is ±400mV differential. The output DC com-
mon-mode voltage is from 0.89V to 1.36V. The I/Q
channel offset is adjustable to optimize radio lineup side-
band/carrier suppression. Typical I-Q channel matching
is ±0.01dB gain and ±0.1°phase.
Two independent 10-bit parallel, high-speed digital
buses used by the Rx ADC and Tx DAC allow full-
duplex operation for frequency-division duplex applica-
tions. The Rx ADC and Tx DAC can be disabled
independently to optimize power management. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADCchannels.
The MAX19712 operates on a single 2.7V to 3.3V analog
supply and 1.8V to 3.3V digital I/O supply. The
MAX19712 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 56-pin,
thin QFN package. The Selector Guideat the end of the
data sheet lists other pin-compatible versions in this AFE
family. For time-division duplex (TDD) applications, refer
to the MAX19705–MAX19708 AFE family of products.
Applications
FeaturesDual 10-Bit, 22Msps Rx ADC and Dual 10-Bit,22Msps Tx DACUltra-Low Power
50.4mW at fCLK= 22MHz, FD Mode
39.9mW at fCLK= 22MHz, Slow Rx Mode33.9mW at fCLK= 22MHz, Slow Tx Mode
Low-Current Standby and Shutdown ModesProgrammable Tx DAC Common-Mode DC Level
and I/Q Offset TrimExcellent Dynamic PerformanceSNR = 54.8dB at fIN= 5.5MHz (Rx ADC)
SFDR = 72.9dBc at fOUT= 2.2MHz (Tx DAC)Three 12-Bit, 1μs Aux-DACs10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
Data AveragingExcellent Gain/Phase Match
±0.01°Phase, ±0.01dB Gain (Rx ADC) at fIN= 5.5MHzMultiplexed Parallel Digital I/OSerial-Interface ControlVersatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx DisableMiniature 56-Pin Thin QFN Package (7mm x 7mm x 0.8mm)
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End19-0528; Rev 0; 5/06
EVALUATION KIT
AVAILABLE
Ordering Information
PART*PIN-PACKAGEPKG CODEMAX19712ETN56 Thin QFN-EP**T5677-1
MAX19712ETN+56 Thin QFN-EP**T5677-1
*All devices are specified over the -40°C to +85°C operating range.
Functional Diagram and Selector Guide appear at end ofTOP VIEW
MAX19712
THIN QFNAD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
OGND
OVDD
DA0
DA1
DA2
DA3
REFN
NOTE: THE PIN 1 INDICATOR IS “+” FOR LEAD-FREE DEVICES.COM
REFIN
QDP
QDN
VDD
GND
IDP
IDN
VDD
DAC1
DAC2
DAC3
ADC123456789101112131441403938373635343332313029
GND
AD0AD1V
QAP
QAN
GND
CLK
GND
IANIAP
REFP
DA6DA5DA4DA7DA8DA9DOUTDINSCLKV
GNDV
ADC2
EXPOSED PADDLE (GND)
CS/WAKE
Pin ConfigurationWCDMA Handsets
801.11a/b/g WLAN
RFIDReaders
VoIPTerminals
Portable Communication
Equipment
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND, OVDDto OGND..............................-0.3V to +3.6V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND.....................-0.3V to VDD
ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V)
REFP, REFN, REFIN, COM to GND...........-0.3V to (VDD + 0.3V)
AD0–AD9, DA0–DA9, SCLK, DIN, CS/WAKE,
CLK, DOUT to OGND.........................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
56-Pin Thin QFN-EP (derate 27.8mW/°C above +70°C)2.22W
Thermal Resistance θJA..................................................36°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSAnalog Supply VoltageVDD2.73.03.3V
Output Supply VoltageOVDD1.8VDDV
FD mode: fCLK = 22MHz, fOUT = 2.2MHz
on both DAC channels; fIN = 5.5MHz on
both ADC channels; aux-DACs ON and at
midscale, aux-ADC ON
FD mode: fCLK = 15.36MHz, fOUT =
2.2MHz on both DAC channels; fIN =
5.5MHz on both ADC channels; aux-DACs
ON and at midscale, aux-ADC ON
SPI2-Tx mode: fCLK = 22MHz, fOUT =
2.2MHz on both DAC channels; Rx ADC
OFF; aux-DACs ON and at midscale,
aux-ADC ON
SPI1-Rx mode: fCLK = 22MHz, fIN =
5.5MHz on both ADC channels; Tx DAC
OFF (Tx DAC outputs at 0V); aux-DACs
ON and at midscale, aux-ADC ON
VDD Supply Current
SPI4-Tx mode: fCLK = 22MHz, fOUT =
2.2MHz on both DAC channels; Rx ADC
ON (output tri-stated); aux-DACs ON and
at midscale, aux-ADC ON
16.419
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSPI3-Rx mode: fCLK = 22MHz, fIN =
5.5MHz on both channels; Tx DAC ON (Tx
DAC outputs at midscale); aux-DACs ON
and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
Idle mode: fCLK = 22MHz; aux-DACs ON
and at midscale, aux-ADC ON7.810
VDD Supply Current
Shutdown mode: CLK = 0 or OVDD,
or aux-ADC OFF0.55µA
FD mode: fCLK = 22MHz, fOUT = 2.2MHz
on both DAC channels; fIN = 5.5MHz on
both ADC channels; aux-DACs ON and at
midscale, aux-ADC ON
SPI1-Rx and SPI3-Rx modes: fCLK =
22MHz, fIN = 5.5MHz on both ADC
channels; DAC input bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
SPI2-Tx and SPI4-Tx modes: fCLK =
22MHz, fOUT = 2.2MHz on both DAC
channels; ADC output bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OVDD; aux-
DACs ON and at midscale, aux-ADC ON0.1
Idle mode: fCLK = 22MHz; aux-DACs ON
and at midscale, aux-ADC ON37
OVDD Supply Current
Shutdown mode: CLK = 0 or OVDD,
or aux-ADC OFF0.1
Rx ADC DC ACCURACYResolutionN10Bits
Integral NonlinearityINL±0.6LSB
Differential NonlinearityDNL±0.45LSB
Offset ErrorResidual DC offset error-5±0.13+5%FS
Gain ErrorIncludes reference error-5±0.8+5%FS
DC Gain Matching-0.15±0.04+0.15dB
Offset Matching±9LSB
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSGain Temperature Coefficient±30ppm/°C
Offset (VDD ±5%)±0.1Power-Supply RejectionPSRRGain (VDD ±5%)±0.05LSB
Rx ADC ANALOG INPUTInput Differential RangeVIDDifferential or single-ended inputs±0.512V
Input Common-Mode Voltage
RangeVCMVDD / 2V
RINSwitched capacitor load245kΩInput ImpedanceCIN5pF
Rx ADC CONVERSION RATEMaximum Clock FrequencyfCLK(Note 2)22MHz
Channel IA5Data LatencyChannel QA5.5
Clock
Cycles
Rx ADC DYNAMIC CHARACTERISTICS (Note 3)fIN = 5.5MHz5354.8Signal-to-Noise RatioSNRfIN = 12.5MHz54.7dB
fIN = 5.5MHz52.954.7Signal-to-Noise and DistortionSINADfIN = 12.5MHz54.6dB
fIN = 5.5MHz65.975.6Spurious-Free Dynamic RangeSFDRfIN = 12.5MHz76.3dBc
fIN = 5.5MHz-72.8-64.3Total Harmonic DistortionTHDfIN = 12.5MHz-71.3dBc
fIN = 5.5MHz-78.9Third-Harmonic DistortionHD3fIN = 12.5MHz-76.7dBc
Intermodulation DistortionIMDfIN1 = 1MHz, AIN1 = -7dBFS;
fIN2 = 1.8MHz, AIN2 = -7dBFS-71dBc
Third-Order Intermodulation
DistortionIM3fIN1 = 1MHz, AIN1 = -7dBFS;
fIN2 = 1.8MHz, AIN2 = -7dBFS-78dBc
Aperture Delay3.5ns
Aperture Jitter2psRMS
Overdrive Recovery Time1.5x full-scale input2ns
Rx ADC INTERCHANNEL CHARACTERISTICSCrosstalk RejectionfIN X ,Y = 5.5M H z, AIN X ,Y = - 0.5d BFS ,
fIN Y ,X = 1M H z, AIN Y ,X = - 0.5d BFS ( N ote 4) -91dB
Amplitude MatchingfIN = 5.5MHz, AIN = -0.5dBFS (Note 5)±0.01dB
Phase MatchingfIN = 5.5MHz, AIN = -0.5dBFS (Note 5)±0.01D eg r ees
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Tx DAC DC ACCURACYResolutionN10Bits
Integral NonlinearityINL±0.3LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 6)-0.75±0.2+0.75LSB
Residual DC OffsetVOS-4±0.03+4mV
Full-Scale Gain Error-40±0.8+40mV
Tx DAC DYNAMIC PERFORMANCEDAC Conversion RatefCLK(Note 2)22MHz
In-Band Noise DensityNDfOUT = 2.2MHz-129d BFS /H z
Third-Order Intermodulation
DistortionIM3fOUT1 = 2MHz, fOUT2 = 2.2MHz-70dBc
Glitch Impulse10pV•s
Spurious-Free Dynamic Range to
NyquistSFDRfOUT = 2.2MHz6172.9dBc
Total Harmonic Distortion to
NyquistTHDfOUT = 2.2MHz-71-60.5dBc
Signal-to-Noise Ratio to NyquistSNRfOUT = 2.2MHz59.3dB
Tx DAC INTERCHANNEL CHARACTERISTICSI-to-Q Output IsolationfOUTX,Y = 2MHz, fOUTY,X = 2.2MHz88dB
Gain Mismatch Between I and Q
ChannelsMeasured at DC-0.4±0.01+0.4dB
Phase Mismatch Between I and Q
ChannelsfOUT = 2.2MHz±0.1D eg r ees
Differential Output Impedance800Ω
Tx DAC ANALOG OUTPUTFull-Scale Output VoltageVFS±400mV
Bits CM1 = 0, CM0 = 0 (default)1.291.361.42
Bits CM1 = 0, CM0 = 11.141.21.27
Bits CM1 = 1, CM0 = 00.961.051.15Output Common-Mode VoltageVCOMD
Bits CM1 = 1, CM0 = 10.780.891.03
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICSReceive Transmit IsolationADC fINI = fINQ = 5.5MHz, DAC fOUTI =
fOUTQ = 2.2MHz85dB
AUXILIARY ADCs (ADC1, ADC2)ResolutionN10Bits
AD1 = 0 (default)2.048Full-Scale ReferenceVREFAD1 = 1VDDV
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAnalog Input Range0 to
VREFV
Analog Input ImpedanceMeasured at DC500kΩ
Input-Leakage CurrentMeasured at unselected input from 0 to
VREF±0.1µA
Gain ErrorGEIncludes reference error, AD1 = 0-5+5%FS
Zero-Code ErrorZE±2mV
Differential NonlinearityDNL±0.6LSB
Integral NonlinearityINL±0.6LSB
Supply Current210µA
AUXILIARY DACs (DAC1, DAC2, DAC3)ResolutionN12Bits
Integral NonlinearityINLFrom code 100 to code 4000±1.25LSB
Differential NonlinearityDNLGuaranteed monotonic over code 100 to
code 4000 (Note 6)-1.0±0.65+1.2LSB
Output-Voltage LowVOLRL > 200kΩ0.2V
Output-Voltage HighVOHRL > 200kΩ2.57V
DC Output ImpedanceDC output at midscale4Ω
Settling TimeFrom code 1024 to code 3072, within ±10
LSB 1µs
Glitch ImpulseFrom code 0 to code 409524nV•s
Rx ADC–Tx DAC TIMING CHARACTERISTICSCLK Rise to Channel-I Output
Data ValidtDOIFigure 3 (Note 6)5.58.211.5ns
CLK Fall to Channel-Q Output
Data ValidtDOQFigure 3 (Note 6)6.59.513.0ns
I-DAC DATA to CLK Fall Setup
TimetDSIFigure 5 (Note 6)10ns
Q-DAC DATA to CLK Rise
Setup TimetDSQFigure 5 (Note 6)10ns
CLK Fall to I-DAC Data Hold TimetDHIFigure 5 (Note 6)0ns
CLK Rise to Q-DAC Data
Hold TimetDHQFigure 5 (Note 6)0ns
CLK Duty Cycle50%
CLK Duty-Cycle Variation±15%
Digital Output Rise/Fall Time20% to 80%2.4ns
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 2)Falling Edge of CS/WAKE to Rising
Edge of First SCLK TimetCSS10ns
DIN to SCLK Setup TimetDS10ns
DIN to SCLK Hold TimetDH0ns
SCLK Pulse-Width HightCH25ns
SCLK Pulse-Width LowtCL25ns
SCLK PeriodtCP50ns
SCLK to CS/WAKE Setup TimetCS10ns
CS/WAKE High Pulse WidthtCSW80ns
CS/WAKE High to DOUT
Active HightCSDBit AD0 set200ns
CS/WAKE High to DOUT Low
(Aux-ADC Conversion Time)tCONVBit AD0 set, no averaging, fCLK = 22MHz,
CLK divider = 84.3µs
DOUT Low to CS/WAKE Setup
TimetDCSBit AD0, AD10 set200ns
SCLK Low to DOUT Data OuttCDBit AD0, AD10 set14.5ns
CS/WAKE High to DOUT High
ImpedancetCHZBit AD0, AD10 set200ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)From shutdown to Rx mode, ADC settles
to within 1dB SINAD500
From shutdown to Tx mode, DAC settles to
within 10 LSB error26.2
From aux-ADC enable to aux-ADC start
conversion10
From shutdown to aux-DAC output valid28
Shutdown Wake-Up Time
(With CLK)tWAKE,SD
From shutdown to FD mode, ADC settles
to within 1dB SINAD, DAC settles to within
10 LSB error
Fr om i d l e to Rx m od e, AD C settl es to w i thi n
1d B S IN AD 7.2
From idle to Tx mode, DAC settles to 10
LSB error5.1Idle Wake-Up Time
(With CLK)tWAKE,ST0
From idle to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
7.2
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSFrom standby to Rx mode, ADC settles to
within 1dB SINAD7.1
From standby to Tx mode, DAC settles to
10 LSB error22.8Standby Wake-Up Time
(With CLK)tWAKE,ST1
From standby to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
Enable Time from Tx to Rx,
Fast ModetENABLE,RXADC settles to within 1dB SINAD0.1µsnab l e Ti m e fr om Rx to Tx,
Fast M od etENABLE,TXDAC settles to within 10 LSB error0.1µs
Enable Time from Tx to Rx,
Slow ModetENABLE,RXADC settles to within 1dB SINAD7.5µsnab l e Ti m e fr om Rx to Tx,l ow M od etENABLE,TXDAC settles to within 10 LSB error5.1µs
INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally)Positive ReferenceVREFP - VCOM0.256V
Negative ReferenceVREFN - VCOM-0.256V
Common-Mode Output VoltageVCOMVDD / 2
- 0.15VDD / 2VDD / 2
+ 0.15V
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
Maximum REFP/REFN/COM
Sink CurrentISINK2mA
Differential Reference OutputVREFVREFP - VREFN+0.490+0.512+0.534V
Differential Reference Temperature
CoefficientREFTC±30ppm/°C
BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally)Reference Input VoltageVREFIN1.024V
Differential Reference OutputVDIFFVREFP - VREFN0.512V
Common-Mode Output VoltageVCOMVDD / 2V
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
Maximum REFP/REFN/COM
Sink CurrentISINK2mA
REFIN Input Current-0.7µA
REFIN Input Resistance500kΩ
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMINto TMAX, unless otherwise noted. Typical values are
at TA= +25°C.) (Note 1)
Note 1:Specifications from TA= +25°C to +85°C guaranteed by production tests. Specifications at TA< +25°C guaranteed by
design and characterization.
Note 2:The minimum clock frequency (fCLK) for the MAX19712 is 2MHz (typ). The minimum aux-ADC sample rate clock frequency
(ACLK) is determined by fCLKand the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK> 2MHz / 128 =
15.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum con-
version time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 2MHz = 768µs.
Note 3:SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4:Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tones.
Note 5:Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
Note 6:Guaranteed by design and characterization.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9–DA0)Input High ThresholdVINH0.7 x OVDDV
Input Low ThresholdVINL0.3 x OVDDV
CLK, SCLK, DIN, CS/WAKE = OGND or
OVDD-1+1
DA9–DA0 = OVDD-1+1Input LeakageDIIN
DA9–DA0 = OGND-5+5
Input CapacitanceDCIN5pF
DIGITAL OUTPUTS (AD9–AD0, DOUT)Output-Voltage LowVOLISINK = 200µA0.2 x OVDDV
Output-Voltage HighVOHISOURCE = 200µA0.8 x OVDDV
Tri-State Leakage CurrentILEAK-1+1µA
Tri-State Output CapacitanceCOUT5pF
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
Rx ADC CHANNEL-IA FFT PLOT
(8192 SAMPLES)MAX19712 toc01
AMPLITUDE (dBFS)
FREQUENCY (MHz)
fIN = 5.4489746MHz
AIN = -0.542dBFS
SINAD = 54.545dB
SNR = 54.615dB
THD = -72.492dBc
SFDR = 77.245dBc
FUNDAMENTAL
Rx ADC CHANNEL-QA FFT PLOT
(8192 SAMPLES)MAX19712 toc02
AMPLITUDE (dBFS)
FREQUENCY (MHz)
fIN = 5.4489746MHz
AIN = -0.515dBFS
SINAD = 54.609dB
SNR = 54.69dB
THD = -71.915dBc
SFDR = 76.817dBc
FUNDAMENTAL
Rx ADC CHANNEL-IA TWO-TONE FFT PLOT
(8192 SAMPLES)MAX19712 toc03
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2fIN2 - fIN1
2fIN1 - fIN2
fIN1 = 1.807373MHz
fIN2 = 2.1135254MHz
AIN1 = AIN2 = -7dBFS
IMD = -71.85dBc
fIN1fIN2
Rx ADC CHANNEL-QA TWO-TONE FFT PLOT
(8192 SAMPLES)MAX19712 toc04
AMPLITUDE (dBFS)
FREQUENCY (MHz)
2fIN2 - fIN1
2fIN1 - fIN2
fIN1 = 1.807373MHz
fIN2 = 2.1135254MHz
AIN1 = AIN2 = -7dBFS
IMD = -71.73dBc
fIN2fIN1
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCYANALOG INPUT FREQUENCY (MHz)
SNR (dB)
MAX19712 toc05102030405060708090100
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT FREQUENCYANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
MAX19712 toc06102030405060708090100
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY-THD (dBc)
MAX19712 toc07102030405060708090100
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCYSFDR (dBc)
MAX19712 toc08102030405060708090100
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT AMPLITUDESNR (dB)
MAX19712 toc09
fIN = 5.4489746MHz
Typical Operating Characteristics(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT AMPLITUDEANALOG INPUT AMPLITUDE (dBFS)
SINAD (dB)
MAX19712 toc10
fIN = 5.4489746MHz
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT AMPLITUDEANALOG INPUT AMPLITUDE (dBFS)
-THD (dBc)
MAX19712 toc11
fIN = 5.4489746MHz
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT AMPLITUDEANALOG INPUT AMPLITUDE (dBFS)
SFDR (dBc)
MAX19712 toc12
fIN = 5.4489746MHz
Rx ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING FREQUENCYSAMPLING FREQUENCY (MHz)
SNR (dB)
MAX19712 toc13246810121416182022
fIN = 5.4489746MHz
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING FREQUENCYSAMPLING FREQUENCY (MHz)
SINAD (dB)
MAX19712 toc14246810121416182022
fIN = 5.4489746MHz
Rx ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING RATESAMPLING FREQUENCY (MHz)
-THD (dBc)
MAX19712 toc15246810121416182022
fIN = 5.4489746MHz
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING FREQUENCYSFDR (dBc)
MAX19712 toc16246810121416182022
fIN = 5.4489746MHz
Rx ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLESNR (dB)
MAX19712 toc17404550556065
fIN = 5.468363MHz
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLESINAD (dB)
MAX19712 toc18404550556065
fIN = 5.468363MHz
Typical Operating Characteristics (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
Rx ADC TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLECLOCK DUTY CYCLE (%)
-THD (dBc)
MAX19712 toc19404550556065IA
fIN = 5.468363MHz
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLECLOCK DUTY CYCLE (%)
SFDR (dBc)
MAX19712 toc20404550556065IA
fIN = 5.468363MHz
Rx ADC OFFSET ERROR
vs. TEMPERATUREMAX19712 toc21
TEMPERATURE (°C)
OFFSET ERROR (%FS)3560-1510
Tx DAC SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING FREQUENCY
SAMPLING FREQUENCY (MHz)
SFDR (dBc)
MAX19712 toc2346810121416182022
fOUT = fCLK / 10
Rx ADC GAIN ERROR
vs. TEMPERATUREMAX19712 toc22
TEMPERATURE (°C)
GAIN ERROR (%FS)
Tx DAC SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT FREQUENCY
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
MAX19712 toc24
Tx DAC SPURIOUS-FREE DYNAMIC
RANGEvs. OUTPUT AMPLITUDE
SFDR (dBc)
MAX19712 toc25
fOUT = 2.2MHz
Tx DAC CHANNEL-ID SPECTRAL PLOTAMPLITUDE (dBFS)
MAX19712 toc26
fOUT = 2.2MHz
Tx DAC CHANNEL-QD SPECTRAL PLOTAMPLITUDE (dBFS)
MAX19712 toc27
fOUT = 2.2MHz
Typical Operating Characteristics (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
Tx DAC CHANNEL-QD TWO-TONE
SPECTAL PLOTFREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19712 toc29
fOUT1 = 4MHz,
fOUT2 = 4.5MHz
SUPPLY CURRENT
vs. SAMPLING FREQUENCYSAMPLING FREQUENCY (MHz)
IVDD
(mA)
MAX19712 toc30
fIN = 5.5MHz,
FD MODE
fOUT = 2.2MHz,
Rx ADC INTEGRAL NONLINEARITYDIGITAL OUTPUT CODE
INL (LSB)
MAX19712 toc311282563845126407688961024
Rx ADC DIFFERENTIAL NONLINEARITY
DIGITAL OUTPUT CODE
DNL (LSB)
MAX19712 toc321282563845126407688961024
Tx DAC INTEGRAL NONLINEARITY
DIGITAL INPUT CODE
INL (LSB)
MAX19712 toc331282563845126407688961024
Tx DAC DIFFERENTIAL NONLINEARITY
DNL (LSB)
MAX19712 toc341282563845126407688961024
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
REFP
- V
REFN
(V)
MAX19712 toc35
VREFP - VREFN
AUX-DAC INTEGRAL NONLINEARITYINL (LSB)
MAX19712 toc365121024153620482560307235844096
Tx DAC CHANNEL-ID TWO-TONE
SPECTAL PLOT
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19712 toc28
fOUT1 = 4MHz,
fOUT2 = 4.5MHz
Typical Operating Characteristics (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
AUX-ADC INTEGRAL NONLINEARITYDIGITAL OUTPUT CODE
INL (LSB)
MAX19712 toc381282563845126407688961024
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX19712 toc40
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)10.10.01
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
OUTPUT VOLTAGE (V)
MAX19712 toc41
MAX19712toc42
AUX-DAC SETTLING TIME400ns/div
AUX-DAC
OUTPUT
CS/WAKE1V/div
500mV/div
STEP FROM CODE 1024 TO CODE 3072
ypical Operating Characteristics (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP= CREFN= CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
AUX-ADC DIFFERENTIAL NONLINEARITYDIGITAL OUTPUT CODE
DNL (LSB)
MAX19712 toc391282563845126407688961024
AUX-DAC DIFFERENTIAL NONLINEARITY
DIGITAL INPUT CODE
DNL (LSB)
MAX19712 toc375121024153620482560307235844096
1.0
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
Pin Description
Detailed DescriptionThe MAX19712 integrates a dual, 10-bit Rx ADC and a
dual, 10-bit Tx DAC while providing ultra-low power
and high dynamic performance at 22Msps conversion
ential and accept 1.024VP-P full-scale signals. The Tx
DAC analog outputs are fully differential with ±400mV
full-scale output, selectable common-mode DC level,
and adjustable channel ID–QD offset trim.
PINNAMEFUNCTIONREFPPositive Reference Voltage Input Terminal. Bypass with a 0.33µF capacitor to GND as close to REFP
as possible.
2, 8, 11, 39,
41, 47, 51VDDAnalog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with
a 0.1µF capacitor.IAPChannel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.IANChannel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.
5, 7, 12, 40, 50GNDAnalog Ground. Connect all GND pins to ground plane.CLKConversion Clock Input. Clock signal for both receive ADCs and transmit DACs.QANChannel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.QAPChannel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP.
13–22AD0–AD9Receive ADC Digital Outputs. AD9 is the most significant bit (MSB) and AD0 is the least significant
bit (LSB).OGNDOutput-Driver GroundOVDDOutput-Driver Power Supply. Supply range from +1.8V to VDD. Bypass OVDD to OGND with a
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
25–34DA0–DA9Transmit DAC Digital Inputs. DA9 is the most significant bit (MSB) and DA0 is the least significant bit
(LSB). DA0–DA9 are internally pulled up to OVDD.DOUTAux-ADC Digital OutputDIN3-Wire Serial-Interface Data Input. Data is latched on the rising edge of SCLK.SCLK3-Wire Serial-Interface Clock InputCS/WAKE3-Wire Serial-Interface Chip-Select/WAKE Input. When the MAX19712 is in shutdown, CS/WAKE
controls the wake-up function. See the Wake-Up Function section.ADC2Selectable Auxiliary ADC Analog Input 2ADC1Selectable Auxiliary ADC Analog Input 1DAC3Auxiliary DAC3 Analog Output (VOUT = 0 at Power-Up)DAC2Auxiliary DAC2 Analog Output (VOUT = 0 at Power-Up)DAC1Auxiliary DAC1 Analog Output (AFC DAC, VOUT = 1.1V at Power-Up)IDNTx DAC Channel-ID Differential Negative OutputIDPTx DAC Channel-ID Differential Positive OutputQDNTx DAC Channel-QD Differential Negative OutputQDPTx DAC Channel-QD Differential Positive OutputREFINReference Input. Connect to VDD for internal reference.COMCommon-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.REFNNegative Reference Voltage Input Terminal. Rx ADC conversion range is ±(VREFP - VREFN). Bypass
REFN to GND with a 0.33µF capacitor.EPExposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
MAX19712The MAX19712 integrates three 12-bit auxiliary DACs
(aux-DACs) and a 10-bit, 333ksps auxiliary ADC (aux-
ADC) with 4:1 input multiplexer. The aux-DAC channels
feature 1µs settling time for fast AGC, VGA, and AFC
level setting. The aux-ADC features data averaging to
reduce processor overhead and a selectable clock-
divider to program the conversion rate.
The MAX19712 includes a 3-wire serial interface to con-
trol operating modes and power management. The seri-
al interface is SPI™ and MICROWIRE™ compatible.
The MAX19712 serial interface selects shutdown, idle,
standby, FD, transmit (Tx), and receive (Rx) modes, as
well as controls aux-DAC and aux-ADC channels.
The MAX19712 features two independent, high-speed,
10-bit buses for the Rx ADC and Tx DAC, which allow
full-duplex (FD) operation for frequency-division duplex
applications. Each bus can be disabled to optimize
power management through the 3-wire interface. The
MAX19712 operates from a single 2.7V to 3.3V analog
supply and a 1.8V to 3.3V digital supply.
Dual 10-Bit Rx ADCThe ADC uses a seven-stage, fully differential, pipelined
architecture that allows for high-speed conversion while
minimizing power consumption. Samples taken at the
inputs move progressively through the pipeline stages
every half clock cycle. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for channel IA and 5.5 clock cycles for channel
QA. The ADC full-scale analog input range is ±VREF
with a VDD/ 2 (±0.8V) common-mode input range. VREF
is the difference between VREFPand VREFN. See the
Reference Configurationssection for details.
Input Track-and-Hold (T/H) CircuitsFigure 1 displays a simplified diagram of the Rx ADC
input track-and-hold (T/H) circuitry. Both ADC inputs
(IAP, QAP, IAN, and QAN) can be driven either differen-
S3b
S3a
COM
S5b
S5a
QAP
QAN
OUT
OUT
C2a
C2b
S4c
S4a
S4bC1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLDHOLDCLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACKTRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
IAP
IAN
OUT
OUT
C2a
C2b
S4c
S4a
S4bC1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX19712
MICROWIRE is a trademark of National Semiconductor Corp.
SPI is a trademark of Motorola, Inc.
10-Bit, 22Msps, Full-Duplex
Analog Front-End
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-Endtially or single-ended. Match the impedance of IAP and
IAN, as well as QAP and QAN, and set the input signal
common-mode voltage within the VDD/2 (±0.8V) Rx
ADC range for optimum performance.
Rx ADC System Timing RequirementsFigure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channels IA
and QA are sampled on the rising edge of the clock sig-
nal (CLK) and the resulting data is multiplexed at the
AD0–AD9 outputs. Channel IA data is updated on the ris-
ing edge and channel QA data is updated on the falling
edge of CLK. Including the delay through the output
latch, the total clock-cycle latency is 5 clock cycles for
channel IA and 5.5 clock cycles for channel QA.
Digital Output Data (AD0–AD9)AD0–AD9 are the Rx ADC digital logic outputs of the
MAX19712. The logic level is set by OVDDfrom 1.8V to
VDD. The digital output coding is offset binary (Table 1).
Keep the capacitive load on the digital outputs AD0–AD9
as low as possible (< 15pF) to avoid large digital currents
feeding back into the analog portion of the MAX19712
and degrading its dynamic performance. Buffers on the
digital outputs isolate the outputs from heavy capacitive
loads. Adding 100Ωresistors in series with the digital out-
puts close to the MAX19712 will help improve ADC per-
formance. Refer to the MAX19712EVKIT schematic for an
example of the digital outputs driving a digital buffer
through 100Ωseries resistors.
During SHDN, IDLE, STBY, SPI2, and SPI4 states, digital
outputs AD0–AD9 are tri-stated.
Dual 10-Bit Tx DACsThe dual 10-bit digital-to-analog converters (Tx DACs)
operate with clock speeds up to 22MHz. The Tx DAC
digital inputs, DA0–DA9, are multiplexed on a single
10-bit transmit bus. The voltage reference determines
the Tx DAC full-scale voltage at IDP, IDN and QDP,
QDN analog outputs. See the Reference Configurations
section for setting the reference voltage.
Figure 2. Rx ADC Transfer Function
INPUT VOLTAGE (LSB)-510-509
2 x VREF1 LSB = VREF = VREFP - VREFN
VREFVREF
REF
REF1-511+510+512+511-512+509
(COM)
(COM)
OFFSET BINAR
Y OUTPUT CODE (LSB)
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0011
11 1111 1111
11 1111 1110
11 1111 1101
01 1111 1111
10 0000 0000
10 0000 0001
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT
VOLTAGEDIFFERENTIAL INPUT (LSB)OFFSET BINARY (AD0–AD9)OUTPUT DECIMAL CODEVREF x 512/512511 (+Full Scale - 1 LSB)11 1111 11111023
VREF x 511/512510 (+Full Scale - 2 LSB)11 1111 11101022
VREF x 1/512+110 0000 0001513
VREF x 0/5120 (Bipolar Zero)10 0000 0000512
-VREF x 1/512-101 1111 1111511
-VREF x 511/512-511 (-Full Scale + 1 LSB)00 0000 00011
-VREF x 512/512-512 (-Full Scale)00 0000 00000
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-EndFigure 3. Rx ADC System Timing Diagram
tDOQ
tCLtCH
tCLK
tDOI
5 CLOCK-CYCLE LATENCY (IA)
5.5 CLOCK-CYCLE LATENCY (QA)
D0–D9D0QD1ID1QD2ID2QD3ID3QD4ID4QD5ID5QD6ID6Q
CLK
Table 2. Tx DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC= 1.024V, External Reference Mode VREFDAC= VREFIN, VFS= 400 for 800mVP-P
Full Scale)
The Tx DAC (IDN, IDP, QDN, QDP) are biased at an
adjustable common-mode DC level and designed to
drive a differential input stage with ≥70kΩinput imped-
ance. This simplifies the analog interface between RF
quadrature upconverters and the MAX19712. Many RF
upconverters require a 0.89V to 1.36V common-mode
bias. The MAX19712 common-mode DC bias eliminates
discrete level-setting resistors and code-generated level
shifting while preserving the full dynamic range of each
Tx DAC. The Tx DAC differential analog outputs can-
internally generated common-mode DC level.Table 2
shows the Tx DAC output voltage vs. input codes. Table
10 shows the selection of DC common-mode levels.
See Figure 4 for an illustration of the Tx DAC analog
output levels.
The Tx DAC also features independent DC offset trim on
each ID–QD channel. This feature is configured through
the SPI interface. The DC offset correction is used to opti-
mize sideband and carrier suppression in the Tx signal
path (see Table 9).
DIFFERENTIAL OUTPUT VOLTAGE (V)OFFSET BINARY (DA0–DA9)INPUT DECIMAL CODE11 1111 11111023
11 1111 11101022
10 0000 0001513
10 0000 0000512
01 1111 1111511
00 0000 00011
00 0000 00000VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×
