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MAX19707ETMMAXIMN/a21avai10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
MAX19707ETM+ |MAX19707ETMMAXIMN/a23avai10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
MAX19707ETM+ |MAX19707ETMMAXIM/DALLASN/a8avai10-Bit, 45Msps, Ultra-Low-Power Analog Front-End


MAX19707ETM+ ,10-Bit, 45Msps, Ultra-Low-Power Analog Front-EndELECTRICAL CHARACTERISTICS(V = 3V, OV = 1.8V, internal reference (1.024V), C ≈ 10pF on all digital ..
MAX19707ETM+ ,10-Bit, 45Msps, Ultra-Low-Power Analog Front-EndFeaturesThe MAX19707 is an ultra-low-power, mixed-signal ana- ♦ Dual, 10-Bit, 45Msps Rx ADC and Dua ..
MAX19708ETM+T ,10-bit, 11Msps, Ultra-Low-Power Analog Front-EndFeatures♦ Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit,The MAX19708 is an ultra-low-power, mixed-sign ..
MAX1970EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOApplicationsPART TEMP RANGE PIN-PACKAGExDSL Modems USB-Powered DevicesMAX1970EEE -40°C to +85°C 16 ..
MAX1970EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOELECTRICAL CHARACTERISTICS(V = V = V = 5V, R = 100kΩ to IN, R = 100kΩ to IN, V = 0, C = 0.1µF, FBSE ..
MAX1970EEE+T ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOFeaturesThe MAX1970/MAX1971/MAX1972 dual-output current-♦ Current-Mode, 1.4MHz Fixed-Frequency PWMm ..
MAX4944LELA+ ,Overvoltage-Protection Controllers with Internal FETApplicationsACOK 4 5 GNDMAX4949Cell Phones PDAs and Palmtop DevicesµDFN2mm × 2mmDigital Still Camer ..
MAX4945AELA+ ,Overvoltage-Protection Controllers with Internal FETFeaturesThe MAX4943–MAX4946/MAX4949 family of overvolt- ♦ Input Voltage Protection Up to +28Vage-pr ..
MAX4945LELA+T ,Overvoltage-Protection Controllers with Internal FETFeaturesThe MAX4943–MAX4946/MAX4949 family of overvolt- ♦ Input Voltage Protection Up to +28Vage-pr ..
MAX4946ELA+ ,Overvoltage-Protection Controllers with Internal FETELECTRICAL CHARACTERISTICS(V = +5V (MAX4943/MAX4944_/MAX4945_/MAX4949), V = +3V (MAX4946), T = -40° ..
MAX4947ETG+ ,Hex SPDT Data SwitchApplications♦ Wide Supply Capability1.8V to 5.5V Supply Voltage RangeUSB Signal Switching Cell Phon ..
MAX494CSD ,Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op AmpsGeneral Description ________


MAX19707ETM-MAX19707ETM+
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
General Description
The MAX19707 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for power-sensitive com-
munication equipment. Optimized for high dynamic
performance at ultra-low power, the device integrates a
dual, 10-bit, 45Msps receive (Rx) ADC; dual, 10-bit,
45Msps transmit (Tx) DAC; three fast-settling 12-bit
aux-DAC channels for ancillary RF front-end control;
and a 10-bit, 333ksps housekeeping aux-ADC. The typ-
ical operating power in Tx-Rx FAST mode is 84.6mW at
a 45MHz clock frequency.
The Rx ADCs feature 54.2dB SNR and 71.2dBc SFDR
at fIN= 5.5MHz and fCLK= 45MHz. The analog I/Q
input amplifiers are fully differential and accept
1.024VP-Pfull-scale signals. Typical I/Q channel match-
ing is ±0.03°phase and ±0.01dB gain.
The Tx DACs feature 73.2dBc SFDR at fOUT= 2.2MHz
and fCLK= 45MHz. The analog I/Q full-scale output volt-
age is ±400mV differential. The Tx DAC common-mode
DC level is programmable from 0.71V to 1.05V. The I/Q
channel offset is programmable to optimize radio lineup
sideband/carrier suppresion. The typical I/Q channel
matching is ±0.01dB gain and ±0.07°phase.
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADC channels.
The MAX19707 operates on a single 2.7V to 3.3V ana-
log supply and 1.8V to 3.3V digital I/O supply. The
MAX19707 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package. The Selector Guide at the end of the
data sheet lists other pin-compatible versions in this
AFE family.
Applications
Features
Dual, 10-Bit, 45Msps Rx ADC and Dual, 10-Bit,
45Msps Tx DAC
Ultra-Low Power
84.6mW at fCLK= 45MHz, Fast Mode
77.1mW at fCLK= 45MHz, Slow Mode
Low-Current Standby and Shutdown Modes
Programmable Tx DAC Common-Mode DC Level
and I/Q Offset Trim
Excellent Dynamic Performance
SNR = 54.2dB at fIN= 5.5MHz (Rx ADC)
SFDR = 73.2dBc at fOUT= 2.2MHz (Tx DAC)
Three 12-Bit, 1µs Aux-DACs10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
Data Averaging
Excellent Gain/Phase Match
±0.03°Phase, ±0.01dB Gain (Rx ADC) at
fIN= 5.5MHz
Multiplexed Parallel Digital I/OSerial-Interface ControlVersatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx Disable
Miniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End

19-3826; Rev 1; 6/07
EVALUATION KIT
AVAILABLE
Ordering Information
PART*PIN-PACKAGEPKG CODE

MAX19707ETM48 Thin QFN-EP**T4877-4
MAX19707ETM+48 Thin QFN-EP**T4877-4
*All devices are specified over the -40°C to +85°C operating
range.
**EP = Exposed paddle.
+Denotes lead-free package.
Functional Diagram and Selector Guide appear at end of
data sheet.

OVDD
OGNDVDD
IDN
IDP
GND
VDD
QDN
QDP
REFN
EXPOSED PADDLE (GND)REFIN
DAC1
COM
DAC237345678910
ADC1
ADC2V
GNDV
SCLKDIN
T/RSHDNDOUTDAC3
THIN QFN

MAX19707
TOP VIEW
REFP
IAP
IAN
GND
CLK
GND
QANQAP
GND123534333231302928272625
Pin Configuration

WiMAX CPEs
802.11a/b/g WLAN
VoIP Terminals
Portable Communication
Equipment
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND, OVDDto OGND..............................-0.3V to +3.6V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND.....................-0.3V to VDD
ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V)
REFP, REFN, REFIN, COM to GND-0.3V to (VDD + 0.3V)D0–D9,
DOUT, T/R, SHDN, SCLK, DIN, CS,
CLK to OGND.....................................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 27.8mW/°C above +70°C).....2.22W
Thermal Resistance θJA..................................................36°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS

Analog Supply VoltageVDD2.73.03.3V
Output Supply VoltageOVDD1.8VDDV
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx):
fCLK = 45MHz, fOUT = 2.2MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx):
fCLK = 45MHz, fOUT = 2.2MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx):
fCLK = 45MHz, fIN = 5.5MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
VDD Supply Current
Ext2-Rx, Ext3-Rx, and SPI1-Rx states;
receive ADC operating mode (Rx):
fCLK = 45MHz, fIN = 5.5MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
25.7
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
Idle mode: fCLK = 45MHz; aux-DACs ON
and at midscale, aux-ADC ON12.115VDD Supply Current
Shutdown mode: CLK = 0 or OVDD1µA
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): fCLK = 45MHz,
fIN = 5.5MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
7.7mA
OVDD Supply Current
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
operating mode (Tx), fCLK = 45MHz, fOUT
= 2.2MHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
485µAtand b y m od e: C LK = 0 or OV D D ; aux- D AC s
ON and at midscale, aux-ADC ON1
Idle mode: fCLK = 45MHz; aux-DACs ON
and at midscale, aux-ADC ON76
Shutdown mode: CLK = 0 or OVDD1
Rx ADC DC ACCURACY

ResolutionN10Bits
Integral NonlinearityINL±1.6LSB
Differential NonlinearityDNL±0.7LSB
Offset ErrorResidual DC offset error-5±0.5+5%FS
Gain ErrorInclude reference error-5.5±1.0+5.5%FS
DC Gain Matching-0.15±0.01+0.15dB
Offset Matching±13LSB
Gain Temperature Coefficient±30ppm/°C
Offset error (VDD ±5%)±0.4LSBPower-Supply RejectionPSRRGain error (VDD ±5%)±0.1%FS
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx ADC ANALOG INPUT

Input Differential RangeVIDDifferential or single-ended inputs±0.512V
Input Common-Mode Voltage
RangeVCMVDD / 2V
RINSwitched capacitor load120kΩInput ImpedanceCIN5pF
Rx ADC CONVERSION RATE

Maximum Clock FrequencyfCLK(Note 2)45MHz
Channel I5Data Latency (Figure 3)Channel Q5.5
Clock
Cycles
Rx ADC DYNAMIC CHARACTERISTICS (Note 3)

fIN = 5.5MHz, fCLK = 45MHz52.554.2Signal-to-Noise RatioSNRfIN = 22MHz, fCLK = 45MHz54.1dB
fIN = 5.5MHz, fCLK = 45MHz52.254.1Signal-to-Noise Plus DistortionSINADfIN = 22MHz, fCLK = 45MHz54dB
fIN = 5.5MHz, fCLK = 45MHz62.171.2Spurious-Free Dynamic RangeSFDRfIN = 22MHz, fCLK = 45MHz70.4dBc
fIN = 5.5MHz, fCLK = 45MHz-78.1Third-Harmonic DistortionHD3fIN = 22MHz, fCLK = 45MHz-73.1dBc
Intermodulation DistortionIMDf1 = 1.8MHz, -7dBFS;
f2 = 1MHz, -7dBFS-68.6dBc
Third-Order Intermodulation
DistortionIM3f1 = 1.8MHz, -7dBFS;
f2 = 1MHz, -7dBFS-79.2dBc
fIN = 5.5MHz, fCLK = 45MHz-68.4-61.5Total Harmonic DistortionTHDfIN = 22MHz, fCLK = 45MHz-68.8dBc
Aperture Delay3.5ns
Overdrive Recovery Time1.5x full-scale input2ns
Rx ADC INTERCHANNEL CHARACTERISTICS

Crosstalk RejectionfIN X,Y = 5.5MH z at - 0.5d BFS , fIN X,Y = 1.8MH z
at - 0.5d BFS ( N ote 4) -90dB
Amplitude MatchingfIN = 5.5MHz at -0.5dBFS (Note 5)±0.01dB
Phase MatchingfIN = 5.5MHz at -0.5dBFS (Note 5)±0.03D eg r ees
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Tx DAC DC ACCURACY

ResolutionN10Bits
Integral NonlinearityINL±0.3LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 6)-1±0.2+1LSB
TA ≥ +25°C-4±1+4Residual DC OffsetVOSTA < +25°C-4.5±1+4.5mV
TA ≥ +25°C-30+30Full-Scale Gain ErrorIncl ud e r efer ence er r or p eak- to- p eak er r or ) TA < +25°C-40+40mV
Tx DAC DYNAMIC PERFORMANCE

DAC Conversion RatefCLK(Note 2)45MHz
In-Band Noise DensityNDfOUT = 2.2MHz, fCLK = 45MHz-130.6dBc/Hz
Third-Order Intermodulation
DistortionIM3f1 = 2MHz, f2 = 2.2MHz80dBc
Glitch Impulse10pV•s
Spurious-Free Dynamic Range to
NyquistSFDRfCLK = 45MHz, fOUT = 2.2MHz6073.2dBc
Total Harmonic Distortion to
NyquistTHDfCLK = 45MHz, fOUT = 2.2MHz-71-59dB
Signal-to-Noise Ratio to NyquistSNRfCLK = 45MHz, fOUT = 2.2MHz57.1dB
Tx DAC INTERCHANNEL CHARACTERISTICS

I-to-Q Output IsolationfOUTX,Y = 2MHz, fOUTX,Y = 2.2MHz85dB
TA ≥ +25°C-0.3±0.01+0.3Gain Mismatch Between DAC
OutputsMeasured at DCTA < +25°C-0.42+0.42dB
Phase Mismatch Between DAC
OutputsfOUT = 2.2MHz, fCLK = 45MHz±0.07D eg r ees
Differential Output Impedance800Ω
Tx DAC ANALOG OUTPUT

Full-Scale Output VoltageVFS±400mV
Bits CM1 = 0, CM0 = 0 (default)1.01.051.1
Bits CM1 = 0, CM0 = 10.95
Bits CM1 = 1, CM0 = 00.80Output Common-Mode VoltageVCOM
Bits CM1 = 1, CM0 = 10.71
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICS

Receive Transmit IsolationADC fINI = fINQ = 5.5MHz, DAC fOUTI =
fOUTQ = 2.2MHz, fCLK = 45MHz85dB
AUXILIARY ADC (ADC1, ADC2)

ResolutionN10Bits
AD1 = 0 (default)2.048Full-Scale ReferenceVREFAD1 = 1VDDV
Analog Input Range0 to
VREFV
Analog Input ImpedanceAt DC500kΩ
Input-Leakage CurrentMeasured at unselected input from 0 to
VREF±0.1µA
Gain ErrorGEIncludes reference error-5+5%FS
Zero-Code ErrorZE2mV
Differential NonlinearityDNL±0.53LSB
Integral NonlinearityINL±0.45LSB
Supply Current210µA
AUXILIARY DACs (DAC1, DAC2, DAC3)

ResolutionN(Note 6)12Bits
Integral NonlinearityINL±1.25LSB
Differential NonlinearityDNLGuaranteed monotonic over codes 100 to
4000 (Note 6)-1.0±0.65+1.1LSB
Gain ErrorGERL > 200kΩ±0.7%FS
Zero-Code ErrorZE±0.6%FS
Output-Voltage LowVOLRL > 200kΩ0.1V
Output-Voltage HighVOHRL > 200kΩ2.56V
DC Output ImpedanceDC output at midscale4Ω
Settling TimeFrom 1/4 FS to 3/4 FS, within ±10 LSB 1µs
Glitch ImpulseFrom 0 to FS transition24nV•s
Rx ADC–Tx DAC TIMING CHARACTERISTICS

CLK Rise to Channel-I Output Data
ValidtDOIFigure 3 (Note 6)5.46.58.1ns
CLK Fall to Channel-Q Output
Data ValidtDOQFigure 3 (Note 6)7.38.811.1ns
I-DAC DATA to CLK Fall Setup
TimetDSIFigure 5 (Note 6)9ns
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Q-DAC DATA to CLK Rise Setup
TimetDSQFigure 5 (Note 6)9ns
CLK Fall to I-DAC Data Hold TimetDHIFigure 5 (Note 6)-4ns
CLK Rise to Q-DAC Data Hold
TimetDHQFigure 5 (Note 6)-4ns
CLK Duty Cycle50%
CLK Duty-Cycle Variation±15%
Digital Output Rise/Fall Time20% to 80%2.6ns
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6)

Falling Edge of CS to Rising Edge
of First SCLK TimetCSS10ns
DIN to SCLK Setup TimetDS10ns
DIN to SCLK Hold TimetDH0ns
SCLK Pulse-Width HightCH25ns
SCLK Pulse-Width LowtCL25ns
SCLK PeriodtCP50ns
SCLK to CS Setup TimetCS10ns
CS High Pulse WidthtCSW80ns
CS High to DOUT Active HightCSDBit AD0 set200ns
CS High to DOUT Low (Aux-ADC
Conversion Time)tCONV
Bit AD0 set, no averaging (see Table 14),
fCLK = 45MHz,
CLK divider = 16 (see Table 15)
4.27µs
DOUT Low to CS Setup TimetDCSBit AD0, AD10 set200ns
SCLK Low to DOUT Data OuttCDBit AD0, AD10 set14.5ns
CS High to DOUT High ImpedancetCHZBit AD0, AD10 set200ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)

From shutdown to Rx mode, ADC settles
to within 1dB SINAD85.2
Shutdown Wake-Up TimetWAKE,SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error28.2
Fr om i d l e to Rx m od e w i th C LK p r esentur i ng i d l e, AD C settl es to w i thi n 1d B S IN AD 9.8
Idle Wake-Up Time (With CLK)tWAKE,ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error6.4
From standby to Rx mode, ADC settles to
within 1dB SINAD13.7
Standby Wake-Up TimetWAKE,ST1
From standby to Tx mode, DAC settles to
10 LSB error24
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Enable Time from Tx to Rx, (Ext2-
Tx to Ext2-Rx, Ext4-Tx to Ext4-Rx,
and SPI4-Tx to SPI3-Rx States)
tENABLE, RXADC settles to within 1dB SINAD500ns
Enable Time from Rx to Tx, (Ext1-
Rx to Ext1-Tx, Ext4-Rx to Ext4-Tx,
and SPI3-Rx to SPI4-Tx States)
tENABLE, TXDAC settles to within 10 LSB error500ns
Enable Time from Tx to Rx, (Ext1-
Tx to Ext1-Rx, Ext3-Tx to Ext3-Rx,
and SPI1-Tx to SPI2-Rx States)
tENABLE, RXADC settles to within 1dB SINAD4.1µs
Enable Time from Rx to Tx, (Ext2-
Rx to Ext2-Tx, Ext3-Rx to Ext3-Tx,
and SPI1-Rx to SPI2-Tx States)
tENABLE, TXDAC settles to within 10 LSB error7.0µs
INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally)

Positive ReferenceVREFP - VCOM0.256V
Negative ReferenceVREFN - VCOM-0.256V
Common-Mode Output VoltageVCOMVDD / 2
- 0.15VDD / 2VDD / 2
+ 0.15V
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
Maximum REFP/REFN/COM
Sink CurrentISINK2mA
Differential Reference OutputVREFVREFP - VREFN+0.489+0.512+0.534V
Differential Reference Temperature
CoefficientREFTC±10ppm/°C
BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally)

Reference Input VoltageVREFIN1.024V
Differential Reference OutputVDIFFVREFP - VREFN0.512V
Common-Mode Output VoltageVCOMVDD / 2V
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
Maximum REFP/REFN/COM
Sink CurrentISINK2mA
REFIN Input Current-0.7µA
REFIN Input Resistance500kΩ
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0–D9, T/R, SHDN)

Input High ThresholdVINH0.7 x OVDDV
Input Low ThresholdVINL0.3 x OVDDV
Input LeakageDIIND0–D9, CLK, SCLK, DIN, CS, T/R,
SHDN = OGND or OVDD-1+1µA
Input CapacitanceDCIN5pF
DIGITAL OUTPUTS (D0–D9, DOUT)

Output-Voltage LowVOLISINK = 200µA0.2 x OVDDV
Output-Voltage HighVOHISOURCE = 200µA0.8 x OVDDV
Tri-State Leakage CurrentILEAK-1+1µA
Tri-State Output CapacitanceCOUT5pF
Note 1:
Specifications from TA= +25°C to +85°C are guaranteed by production tests. Specifications from TA= +25°C to -40°C are
guaranteed by design and characterization.
Note 2:
The minimum clock frequency (fCLK) for the MAX19707 is 7.5MHz (typical). The minimum aux-ADC sample rate clock fre-
quency (ACLK) is determined by fCLKand the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK >
7.5MHz / 128 = 58.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI™.
The maximum conversion time (for no averaging, NAVG = 1) will be, tCONV (max) = (12 x 1 x 128) / 7.5MHz = 205µs.
Note 3:
SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4:
Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second
channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel
FFT test tone.
Note 5:
Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
Note 6:
Guaranteed by design and characterization.
SPI is a trademark of Motorola, Inc.
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
Rx ADC CHANNEL-IA FFT PLOT

MAX19707 toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 45.006848MHz
fIA = 13.00155MHz
16,384-POINT
DATA RECORD
Rx ADC CHANNEL-QA FFT PLOT

MAX19707 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 45.006848MHz
fQA = 13.00155MHz
16,384-POINT
DATA RECORD
Rx ADC CHANNEL-IA
TWO-TONE FFT PLOT

MAX19707 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 45.006848MHz
f1 = 1.4MHz
f2 = 1.8MHz
AIA = -7dBFS
PER TONE
8192-POINT
DATA RECORD
Rx ADC CHANNEL-QA
TWO-TONE FFT PLOT

MAX19707 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 45.006848MHz
f1 = 1.4MHz
f2 = 1.8MHz
AQA = -7dBFS
PER TONE
8192-POINT
DATA RECORD
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY

MAX19707 toc05
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)602040100
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT FREQUENCY

MAX19707 toc06
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)602040
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX19707 toc07
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)602040
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX19707 toc08
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)602040
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT AMPLITUDE
MAX19707 toc09
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB)-6-9-12-15-18
fIN = 13.00155MHzQA
Typical Operating Characteristics

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT AMPLITUDE

MAX19707 toc10
ANALOG INPUT AMPLITUDE (dBFS)
SINAD (dB)-6-9-12-15-18
fIN = 13.00155MHz
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT AMPLITUDE

MAX19707 toc11
ANALOG INPUT AMPLITUDE (dBFS)
THD (dBc)-6-9-12-15-18
fIN = 12.4980346MHz
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT AMPLITUDE

MAX19707 toc12
ANALOG INPUT AMPLITUDE (dBFS)
SFDR (dBc)-6-9-12-15-18
fIN = 12.4980346MHz1525351020304045
Rx ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE

MAX19707 toc13
SAMPLING RATE (MHz)
SNR (dB)
fIN = 12.4980346MHz1525351020304045
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING RATE

MAX19707 toc14
SAMPLING RATE (MHz)
SINAD (dB)
fIN = 12.4980346MHz
Rx ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
MAX19707 toc15
SAMPLING RATE (MHz)
THD (dBc)
fIN = 12.4980346MHz1525351020304045
Rx ADC SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING RATE

MAX19707 toc16
SAMPLING RATE (MHz)
SFDR (dBc)
fIN = 12.4980346MHz
Rx ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE

MAX19707 toc17
CLOCK DUTY CYCLE (%)
SNR (dB)554565
fIN = 12.4980346MHz
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE

MAX19707 toc18
CLOCK DUTY CYCLE (%)
SINAD (dB)554565
fIN = 12.4980346MHz
Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End

Rx ADC GAIN ERROR
vs. TEMPERATURE
MAX19707 toc22
TEMPERATURE (°C)
GAIN ERROR (%FS)
Rx ADC TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
MAX19707 toc19
CLOCK DUTY CYCLE (%)
THD (dBc)554565
fIN = 12.4980346MHz
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE

MAX19707 toc20
CLOCK DUTY CYCLE (%)
SFDR (dBc)554565
fIN = 12.4980346MHz
Rx ADC OFFSET ERROR
vs. TEMPERATURE
MAX19707 toc21
TEMPERATURE (°C)
OFFSET ERROR (%FS)
Tx DAC SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING RATE
MAX19707 toc23
SAMPLING RATE (MHz)
SFDR (dBc)
fOUT = fCLK / 10468210121416182022
Tx DAC SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT FREQUENCY

MAX19707 toc24
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
Tx DAC SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT AMPLITUDE
MAX19707 toc25
OUTPUT AMPLITUDE (dBFS)
SFDR (dBc)
fOUT = 2.2MHz
Tx DAC CHANNEL-ID SPECTRAL PLOT

MAX19707 toc26
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fID = 5.498MHz
Tx DAC CHANNEL-QD SPECTRAL PLOT

MAX19707 toc27
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fQD = 5.498MHzypical Operating Characteristics (continued)
(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End

SUPPLY CURRENT vs. SAMPLING RATE
MAX19707 toc28
SAMPLING RATE (MHz)
SUPPLY CURRENT (mA)
IVDD
Ext4-Rx MODE
Rx ADC INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE

MAX19707 toc29
DIGITAL OUTPUT CODE
INL (LSB)
Rx ADC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX19707 toc30
DIGITAL OUTPUT CODE
DNL (LSB)
Tx DAC INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX19707 toc31
DIGITAL INPUT CODE
INL (LSB)
Tx DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX19707 toc32
DIGITAL INPUT CODE
DNL (LSB)
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX19707 toc34
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)10.10.01
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX19707 toc35
OUTPUT SINK CURRENT (mA)
OUTPUT VOLTAGE (V)10.10.01
AUX-DAC SETTLING TIME
MAX19707 toc36
500ns/div
500mV/div
STEP FROM 1/4FS TO 3/4FS
Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE

MAX19707 toc33
TEMPERATURE (°C)
REFP
- V
REFN
(V)60-151035
VREFP - VREFN
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
AUX-DAC INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE

MAX19707 toc37
DIGITAL INPUT CODE
INL (LSB)
AUX-DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX19707 toc38
DIGITAL INPUT CODE
DNL (LSB)
AUX-ADC INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX19707 toc39
DIGITAL OUTPUT CODE
INL (LSB)
AUX-ADC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX19707 toc40
DIGITAL OUTPUT CODE
DNL (LSB)
PINNAMEFUNCTIONREFPUpper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
2, 8, 11, 31,
33, 39, 43VDDAnalog Supply Voltage. Supply range from 2.7V to 3.3V. Bypass VDD to GND with a combination of
a 2.2µF capacitor in parallel with a 0.1µF capacitor.IAPChannel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.IANChannel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.
5, 7, 12, 32, 42GNDAnalog Ground. Connect all GND pins to ground plane.CLKConversion Clock Input. Clock signal for both receive ADCs and transmit DACs.QANChannel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.
Pin Descriptionypical Operating Characteristics (continued)

(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
PINNAMEFUNCTION
QAPChannel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP.
13–18, 21–24D0–D9Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most
significant bit (MSB) and D0 is the least significant bit (LSB).OGNDOutput-Driver GroundOVDDOutput-Driver Power Supply. Supply range from 1.8V to VDD. Bypass OVDD to OGND with a
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.SHDNActive-Low Shutdown Input. Apply logic-low to place the MAX19707 in shutdown.DOUTAux-ADC Digital OutputT/RTransmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A
logic-high input sets the device in transmit mode.DIN3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK.SCLK3-Wire Serial-Interface Clock InputCS3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface.ADC2Analog Input for Auxiliary ADCADC1Analog Input for Auxiliary ADCDAC3Analog Output for Auxiliary DAC3DAC2Analog Output for Auxiliary DAC2DAC1Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up)
40, 41IDN, IDPDAC Channel-ID Differential Voltage Output
44, 45QDN, QDPDAC Channel-QD Differential Voltage OutputREFINReference Input. Connect to VDD for internal reference. Bypass to GND with a 0.1µF capacitor.COMCommon-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.REFNNegative Reference I/O. Rx ADC conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a
0.33µF capacitor.EPExposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
Pin Description (continued)

MICROWIRE is a trademark of National Semiconductor Corp.
Detailed Description

The MAX19707 integrates a dual, 10-bit Rx ADC and a
dual, 10-bit Tx DAC while providing ultra-low power
and high dynamic performance at a 45Msps conver-
sion rate. The Rx ADC analog input amplifiers are fully
differential and accept 1.024VP-P full-scale signals. The
Tx DAC analog outputs are fully differential with
±400mVfull-scale output, selectable common-mode
DC level, and adjustable I/Q offset trim.
The MAX19707 integrates three 12-bit auxiliary DAC
(aux-DAC) channels and a 10-bit, 333ksps auxiliary
ADC (aux-ADC) with 4:1 input multiplexer. The aux-DAC
channels feature 1µs settling time for fast automatic
gain-control (AGC), variable-gain amplifier (VGA), and
automatic frequency-control (AFC) level setting. The
aux-ADC features data averaging to reduce processor
overhead and a selectable clock-divider to program the
conversion rate.
The MAX19707 includes a 3-wire serial interface to
control operating modes and power management. The
serial interface is SPI and MICROWIRE™ compatible.
The MAX19707 serial interface selects shutdown, idle,
standby, transmit (Tx), and receive (Rx) modes, as well
as controls aux-DAC and aux-ADC channels.
The Rx ADC and Tx DAC share a common digital I/O to
reduce the digital interface to a single, 10-bit parallel
multiplexed bus. The 10-bit digital bus operates on a
single 1.8V to 3.3V supply.
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End

Figure 1. Rx ADC Internal T/H Circuits
S3b
S3a
COM
S5b
S5a
QAP
QAN
OUT
OUT
C2a
C2b
S4c
S4a
S4bC1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLDHOLDCLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACKTRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
IAP
IAN
OUT
OUT
C2a
C2b
S4c
S4a
S4bC1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX19707
Dual, 10-Bit Rx ADC

The ADC uses a seven-stage, fully differential, pipelined
architecture that allows for high-speed conversion while
minimizing power consumption. Samples taken at the
inputs move progressively through the pipeline stages
every half clock cycle. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for channel IA and 5.5 clock cycles for channel
QA. The ADC full-scale analog input range is ±VREF
with a VDD/ 2 ±0.2V common-mode input range. VREF
is the difference between VREFPand VREFN. See the
Reference Configurationssection for details.
Input Track-and-Hold (T/H) Circuits

Figure 1 displays a simplified diagram of the Rx ADC
input track-and-hold (T/H) circuitry. Both ADC inputs
(IAP, QAP, IAN, and QAN) can be driven either differ-
entially or single-ended. Match the impedance of IAP
and IAN, as well as QAP and QAN, and set the input
signal common-mode voltage within the Rx ADC range
of VDD/2 (±200mV) for optimum performance.
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
Rx ADC System Timing Requirements

Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel I
(CHI) and channel Q (CHQ) are sampled on the rising
edge of the clock signal (CLK) and the resulting data is
multiplexed at the D0–D9 outputs. CHI data is updated
on the rising edge and CHQ data is updated on the
falling edge of the CLK. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for CHI and 5.5 clock cycles for CHQ.
Digital Input/Output Data (D0–D9)

D0–D9 are the Rx ADC digital logic outputs when the
MAX19707 is in receive mode. This bus is shared with
the Tx DAC digital logic inputs and operates in half-
duplex mode. D0–D9 are the Tx DAC digital logic inputs
when the MAX19707 is in transmit mode. The logic level
is set by OVDDfrom 1.8V to VDD. The digital output cod-
ing is offset binary (Table 1). Keep the capacitive load
on the digital outputs D0–D9 as low as possible (< 15pF)
to avoid large digital currents feeding back into the ana-
log portion of the MAX19707 and degrading its dynamic
performance. Buffers on the digital outputs isolate the out-
puts from heavy capacitive loads. Adding 100Ωresistors
in series with the digital outputs close to the MAX19707
helps improve Rx ADC and Tx DAC performance. Refer
to the MAX19707EVKIT schematic for an example of the
digital outputs driving a digital buffer through 100Ωseries
resistors.
During SHDN, IDLE, and STBY states, D0–D9 are inter-
nally pulled up to prevent floating digital inputs. To ensure
no current flows through D0–D9 I/O, the external bus
needs to be either tri-stated or pulled up to OVDDand
should not be pulled to ground.
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT
VOLTAGEDIFFERENTIAL INPUT (LSB)OFFSET BINARY (D0–D9)OUTPUT DECIMAL CODE

VREF x 512/512511 (+Full Scale - 1 LSB)11 1111 11111023
VREF x 511/512510 (+Full Scale - 2 LSB)11 1111 11101022
VREF x 1/512+110 0000 0001513
VREF x 0/5120 (Bipolar Zero)10 0000 0000512
-VREF x 1/512-101 1111 1111511
-VREF x 511/512-511 (-Full Scale +1 LSB)00 0000 00011
-VREF x 512/512-512 (-Full Scale)00 0000 00000
Figure 2. Rx ADC Transfer Function
INPUT VOLTAGE (LSB)-510-509
2 x VREF1 LSB = VREF = VREFP - VREFN
VREFVREF
REF
REF1-511+510+512+511-512+509
(COM)
(COM)
OFFSET BINAR
Y OUTPUT CODE (LSB)
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0011
11 1111 1111
11 1111 1110
11 1111 1101
01 1111 1111
10 0000 0000
10 0000 0001
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End

Figure 3. Rx ADC System Timing Diagram
tDOQ
tCLtCH
tCLK
tDOI
5 CLOCK-CYCLE LATENCY (CHI)
5.5 CLOCK-CYCLE LATENCY (CHQ)
D0–D9D0QD1ID1QD2ID2QD3ID3QD4ID4QD5ID5QD6ID6Q
CHI
CHQ
CLK
Table 2. Tx DAC Output Voltage vs. Input Codes

(Internal Reference Mode VREFDAC= 1.024V, External Reference Mode VREFDAC= VREFIN; VFS= ±400 for 800mVP-P
Full Scale)
DIFFERENTIAL OUTPUT VOLTAGE (V)OFFSET BINARY (D0–D9)INPUT DECIMAL CODE

11 1111 11111023
11 1111 11101022
10 0000 0001513
10 0000 0000512
01 1111 1111511
00 0000 00011
00 0000 00000VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×−VREFDAC
1023()×−VREFDAC
1023()×−
Dual, 10-Bit Tx DAC

The dual, 10-bit digital-to-analog converter (Tx DAC)
operates with clock speeds up to 45MHz. The Tx DAC
digital inputs, D0–D9, are multiplexed on a single 10-bit
bus. The voltage reference determines the Tx DAC full-
scale output voltage. See the Reference Configurations
section for details on setting the reference voltage.
The Tx DAC outputs at IDN, IDP and QDN, QDP are
biased at a 0.7V to 1.05V adjustable DC common-
mode bias and designed to drive a differential input
stage with ≥70kΩinput impedance. This simplifies the
analog interface between RF quadrature upconverters
and the MAX19707. Many RF upconverters require a
0.7V to 1.05V common-mode bias. The Tx DAC DC
common-mode bias eliminates discrete level-setting
resistors and code-generated level shifting while pre-
serving the full dynamic range of each Tx DAC. The Tx
DAC differential analog outputs cannot be used in sin-
gle-ended mode because of the internally generated
common-mode DC level. Table 2 shows the Tx DAC
output voltage vs. input codes. Table 10 shows the
selection of DC common-mode levels. See Figure 4 for
an illustration of the Tx DAC analog output levels.
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End

The Tx DAC also features independent DC offset cor-
rection of each I/Q channel. This feature is configured
through the SPI interface. The DC offset correction is
used to optimize sideband and carrier suppression in
the Tx signal path (see Table 9).
Figure 4. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs
Tx DAC
I-CH
Tx DAC
Q-CH
FULL SCALE = 1.25V
VCOM = 1.05V
ZERO SCALE = 0.85V
COMMON-MODE LEVEL
SELECT CM1 = 0, CM0 = 0
VCOM = 1.05V
VDIFF = ±400mV
EXAMPLE:

Tx RFIC INPUT REQUIREMENTS
• DC COMMON-MODE BIAS =
0.9V (MIN), 1.3V (MAX)
• BASEBAND INPUT = ±400mV
DC-COUPLED
MAX19707
ic,good price


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