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MAX153MAXIMN/a134avai1Msps, µP Compatible, 8-Bit ADC with 1µA Power Down


MAX153 ,1Msps, µP Compatible, 8-Bit ADC with 1µA Power DownApplications● Cellular TelephonesVDD● Portable Radios20VREF+ 12● Battery-Powered Systems18PWRDN4-BI ..
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MAX4168EUB ,High-Output-Drive, Precision, Low-Power, Single-Supply, Rail-to-Rail I/O Op Amps with ShutdownApplicationsPortable Headphone Speaker DriversPin ConfigurationsLaptop/Notebook ComputersSound Port ..
MAX4168EUB ,High-Output-Drive, Precision, Low-Power, Single-Supply, Rail-to-Rail I/O Op Amps with Shutdownapplications and other low-voltage, battery-poweredReduces Supply Current to 38µA Placessystems. Th ..
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MAX4169ESD ,Quad, high-output-drive, precision, low-power, single-supply +2.7V to +6.5V, Rail-to-Rail I/O op amp.ApplicationsOrdering Information continued at end of data sheet.Portable Head-Phone Speaker Drivers ..
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MAX153
1Msps, µP Compatible, 8-Bit ADC with 1µA Power Down
MAX1531Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
General Description

The MAX153 high-speed, microprocessor (µP)-compatible,
8-bit analog-to-digital converter (ADC) uses a half-flash
technique to achieve a 660ns conversion time, and digitiz-
es at a rate of 1M samples per second (Msps). It operates
with single +5V or dual ±5V supplies and accepts either
unipolar or bipolar inputs. A POWERDN (power-down)
pin reduces current consumption to a typical value of 1µA
(with 5V supply). The part returns from power-down to
normal operating mode in less than 200ns, providing large
reductions in supply current in applications with burst-
mode input signals.
The MAX153 is DC and dynamically tested. Its µP interface
appears as a memory location or input/output port that
requires no external interface logic. The data outputs use
latched, three-state buffered circuitry for direct connection
to a µP data bus or system input port. The ADC’s input/
reference arrangement enables ratiometric operation.
Applications
Cellular Telephones● Portable Radios● Battery-Powered Systems● Burst-Mode Data Acquisition● Digital-Signal Processing● Telecommunications● High-Speed Servo Loops
Features
660ns Conversion TimePower-Up/Power-Down in 200nsInternal Track/Hold1Msps ThroughputLow Power
40mW (Operating Mode)
5µW (Power-Down Mode)1MHz Full-Power Bandwidth20-Pin Narrow DIP, SO, and SSOP PackagesNo External Clock RequiredUnipolar/Bipolar InputsSingle +5V or Dual ±5V SuppliesRatiometric Reference Inputs
Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX153.related.
Functional Diagram

4-BIT
FLASH
ADC
4-BIT
FLASH
ADC
(4 LSB)
TIMING AND CONTROL
CIRCUITRY
MAX153

GNDMODEWR/RDYCSRDINTVSS
THREE-
STATE
DRIVERS
D0–D7
DATA
OUT
PINS
2–5,
VREF+
VREF-VIN
PWRDN
4-BIT
DAC
VREF+637719
VDD
MAX1531Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
Electrical Characteristics

(VDD = +5V ±5%, VGND = 0V; Unipolar Input Range: VSS = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: VSS = -5V ±5%,
VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), TA = TMIN to TMAX,
unless otherwise noted.)
(All voltages referenced to GND.)
VDD ..........................................................................-0.3V to +7V
VSS ..........................................................................+0.3V to -7V
Digital Input Voltage ............................... +0.3V to (VDD + 0.3V)
Digital Output Voltage.............................. -0.3V to (VDD + 0.3V)
VREF+, VREF+, VIN ........................(VSS - 0.3V) to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
PDIP (derate 11.11mW/°C above + 70°C). .................889mW
SO(W) (derate 10.00mW/°C above +70°C..................800mW SSOP (derate 8.00mW/°C above +70°C) ...................640mWOperating Temperature Ranges
MAX153C ...................................................................0 to +70°CMAX153E ...........................................................-40°C to +85°CStorage Temperature Range ............................-65°C to +150°CLead Temperature (soldering, 10s) .................................+300°CSoldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings

PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ACCURACY
ResolutionN8Bits
Total Unadjusted ErrorTUEUnipolar range±1LSB
Differential NonlinearityDNLNo missing codes guaranteed±1LSB
Zero-Code ErrorBipolar input range±1LSB
Full-Scale ErrorBipolar input range±1LSB
DYNAMIC SPECIFICATIONS (Note 1)
Signal-to-Noise Plus Distortion NoiseSINADfSAMPLE = 1MHz, fIN = 195.8kHz45dB
Total Harmonic DistortionTHDfSAMPLE = 1MHz, fIN = 195.8kHz-50dB
Peak Harmonic or Spurious NoisefSAMPLE = 1MHz, fIN = 195.8kHz-50dB
Conversion Time (WR-RD Mode) (Note 2)tCWRTA = +25°C, tRD < tINTL, CL = 20pF660ns
Conversion Time (RD Mode)tCRDTA = +25°C700ns
TA = TMIN to TMAX875
Full-Power BandwidthVIN = 5VP-P1MHz
Input Slew Rate3.1415V/µs
ANALOG INPUT
Input Voltage RangeVINVREF-VREF+V
Input Leakage CurrentIIN-5V ≤ VIN ≤ +5V±3µA
Input CapacitanceCIN22pF
REFERENCE INPUT
Reference ResistanceRREF124kΩ
VREF+ Input Voltage RangeVREF-VDDV
MAX1531Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
Electrical Characteristics (continued)

(VDD = +5V ±5%, VGND = 0V; Unipolar Input Range: VSS = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: VSS = -5V ±5%,
VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), TA = TMIN to TMAX,
unless otherwise noted.)
Note 1:
Bipolar input range, VIN = ±2.5VP-P. WR-RD mode.
Note 2:
See Figure 1 for load circuit. Parameter defined as the time required for the output to cross +0.8V or +2.4V.
Note 3:
Guaranteed by design.
Note 4:
Tested with CS, RD, PWRDN at CMOS logic levels. Power-down current increases to several hundred) µA at TTL levels.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOGIC INPUTS
Input High VoltageVINHCS, WR, RD, PWRDN2.4VMODE3.5
Input Low VoltageVINLCS, WR, RD, PWRDN0.8VMODE1.5
Input High CurrentIINH
CS, RD, PWRDN1WR3
MODE50200
Input Low CurrentIINLCS, WR, RD, PWRDN±1µA
Input Capacitance (Note 3)CINCS, WR, RD, PWRDN, MODE58pF
LOGIC OUTPUTS
Output Low VoltageVOLISINK = 1.6mA, INT, D0–D70.4VRDY, ISINK = 2.6mA0.4
Output High VoltageVOHISOURCE = 360µA, INT, D0–D74V
Floating State CurrentILKGD0–D7, RDY±3µA
Floating Capacitance (Note 3)COUTD7–D0, RDY58pF
POWER REQUIREMENTS
Positive Supply VoltageVDD±5% for speciied accuracy5V
Negative Supply Voltage (Unipolar Operation)VSSGNDV
Negative Supply Voltage (Bipolar Operation)VSS±5% for speciied accuracy-5V
VDD Supply CurrentIDDVCS = VRD = 0V,
VPWRDN = 5V
MAX153C815MAX153E820
Power-Down VDD CurrentVCS = VRD = 5V, VPWRDN = 0V (Note 4)1100µA
VSS Supply CurrentISSVCS = VRD = 0V, VPWRDN = 5V25100µA
Power-Down VSS CurrentVCS = VRD = 5V, VPWRDN = 0V12100µA
Power-Supply RejectionPSRVDD = 4.75V to 5.25V, VREF+ = 4.75V
(max), unipolar mode±1/16±1/4LSB
MAX1531Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
TIMING CHARACTERISTICS (Note 5)

(VDD = +5V ±5%, VSS = 0V for Unipolar Input Range, VSS = -5V ±5% for Bipolar Input Range, 100% production tested, TA = +25°C,
unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

CS TO RD/WR Setup TimetCSS0ns
CS to RD/WR Hold TimetCSH0ns
CS to RDY Delay (Note 6)tRDYCL = 50pF70nsTA = TMIN to TMAX, CL = 50pF85
Data-Access Time (RD Mode) (Note 2)tACC0
CL = 20pFtCRD + 25TA = TMIN to TMAX, CL = 20pFtCRD + 30
CL = 100pFtCRD + 50
TA = TMIN to TMAX, CL = 100pFtCRD + 65
RD to INT Delay (RD Mode)tINTHCL = 50pF5080nsTA = TMIN to TMAX, CL = 50pF85
Data-Hold Time (Note 7)tDH60nsTA = TMIN to TMAX70
Delay Time Between
Conversions (Acquisition Time)tP160nsTA = TMIN to TMAX185
Write Pulse WidthtWR
0.25010TA = TMIN to TMAX0.28010
Delay Time Between WR
and RD PulsestRD250ns
TA = TMIN to TMAX350
RD Pulse Width (WR-RD Mode)
Determined by tACC1tREAD1Figure 6160nsTA = TMIN to TMAX, Figure 6205
Data-Access Time
(WR-RD Mode (Note 2)
tRD < tINL
tACC1
CL = 20pF, Figure 6160TA = TMIN to TMAX, CL = 20pF, Figure 6205
CL = 100pF, Figure 6185
TA = TMIN to TMAX, CL = 100pF, Figure 6235
RD to INT DelaytRI
150TA = TMIN to TMAX185
WR to INT DelaytINTLCL = 50pF380500ns
TA = TMIN to TMAX, CL = 50pF610
RD Pulse Width (WR-RD Mode)
Determinted by tACC2
tRD > tINTL
tREAD2Figure 565
TA = TMIN to TMAX, Figure 575
Data-Access Time (WR-RD Mode) (Note 2)
tRD > tINTL
tACC2
CL = 20pF, Figure 565TA = TMIN to TMAX, CL = 20pF, Figure 575
CL = 100pF, Figure 590
TA = TMIN to TMAX, CL = 100pF, Figure 5110
MAX1531Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
TIMING CHARACTERISTICS (Note 5) (continued)

(VDD = +5V ±5%, VSS = 0V for Unipolar Input Range, VSS = -5V ±5% for Bipolar Input Range, 100% production tested, TA = +25°C,
unless otherwise noted.)
Note 5:
Input control signals are specified with tr = tt = 5ns, 10% to 90% of +5V and timed from a 1.6V voltage level.
Note 6: RL = 5.1kΩ pullup resistor.
Note 7:
See Figure 2 for load circuit. Parameter defined as the time required for data lines to change 0.5V.
Figure 1. Load Circuits for Data-Access Time TestFigure 2. Load Circuits for Data-Hold Time Test
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

WR to INT Delay
(Pipelined Mode)tIHWRCL = 50pF80nsTA = TMIN to TMAX, CL = 50pF100
Data-Access Time After
INT (Note 2)tID
CL = 20pF30TA = TMIN to TMAX, CL = 20pF35
CL = 100pF45
TA = TMIN to TMAX, CL = 100pF603kΩ
DGND
A. HIGH-Z TO VOHB. HIGH-Z TO VOL
3kΩ
DGND
+5V
10pF3kΩ
DGND
A. VOH TO HIGH-Z B. VOL TO HIGH-Z
10pF
3kΩ
DGND
+5V
MAX1531Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
Typical Operating Characteristics
CONVERSION TIME
vs. AMBIENT TEMPERATURE

MAX153 toc01
TEMPERATURE (°C)
tCRD
(NORMALIZED TO VALUE AT +25°C)
VDD = +5.25V
VDD = +4.75V
VDD = +5V
SIGNAL-TO-NOISE RATIO

MAX153 toc03
FREQUENCY (kHz)
TA = +25°C
INPUT FREQUENCY
= 195.8ksps (±2.5V)
SAMPLE FREQUENCY
= 1MHz
SNR = 49.1dB
RATIO (dB)
EFFECTIVE BITS vs. INPUT
FREQUENCY, WR-RD MODE

MAX153 toc02
FREQUENCY (kHz)10010
EFFECTIVE BITS
ROOMCOLD -55°C
ISAMPLE = 1MHz
VIN = ±2.5V
HOT +125°C
INTERMODULATION DISTORTION
MAX153 toc04
FREQUENCY (kHz)
TA = +25°CINPUT FREQUENCY
= 94.97kHz
= 84.72kHz (±2.5V)
SAMPLE FREQUENCY
= 500kHz
IMD: 2ND-ORDER TERMS
= -66.2dB
3RD-OREDER TERMS
= -60.0dB
RATIO (dB)
MAX1531Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
Pin Description
Pin Coniguration

*See the Digital Interface section.
PINNAMEFUNCTION
VINAnalog Input. Range is VREF- > VIN < VREF+.D0Three-State Data Output (LSB)
3–5D1–D3Three-State Data OutputsWR/RDYWRITE Control Input/READY Status Output*MODEMODE Selection Input. Internally pulled low with a 50µA current source. MODE = 0 activates read mode. MODE = 1 actives write-read mode*RDREAD Input. Must be low to access data*.INTINTERRUPT Output goes low to indicate end of conversion*. GNDGroundVREF-Lower Limit of Reference Span. Sets the zero-code voltage. Range is VSS < VREF- < VREF+.VREF+Upper Limit to Reference Span. Sets the full-scale input voltage. Range is VREF- < VREF+ < VDD.CSCHIP SELECT Input. Must be low for the device to recognize WR or RD inputs.
14–16D4–D6Three-State Data OutputsD7Three-State Data Output (MSB)PWRDNPOWERDOWN Input. Reduces supply current when low. CS must be high during power-down.VSSNegative Supply. Unipolar: VSS = 0V, Bipolar: VSS = -5V.VDDPositive Supply, +5V
VDD
VSS
PWRDN
D7 (MSB)D2
D0 (LSB)
VIN
TOP VIEW
MAX153
RD
WR/RDY7D4MODE10VREF-GND9VREF+INT
PDIP/SO(W)/SSOP
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