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MAX1278ETCMAXIMN/a2avai1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs with Internal Reference


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MAX1278ETC
1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs with Internal Reference
General Description
The MAX1276/MAX1278 are low-power, high-speed, seri-
al-output, 12-bit, analog-to-digital converters (ADCs) that
operate at up to 1.8Msps and have an internal reference.
These devices feature true-differential inputs, offering bet-
ter noise immunity, distortion improvements, and a wider
dynamic range over single-ended inputs. A standard
SPI™/QSPI™/MICROWIRE™interface provides the clock
necessary for conversion. These devices easily interface
with standard digital signal processor (DSP) synchronous
serial interfaces.
The MAX1276/MAX1278 operate from a single +4.75V to
+5.25V supply voltage. The MAX1276/MAX1278 include
a 4.096V internal reference. The MAX1276 has a unipolar
analog input, while the MAX1278 has a bipolar analog
input. These devices feature a partial power-down mode
and a full power-down mode for use between conver-
sions, which lower the supply current to 2mA (typ) and
1µA (max), respectively. Also featured is a separate
power-supply input (VL), which allows direct interfacing to
+1.8V to VDDdigital logic. The fast conversion speed,
low-power dissipation, excellent AC performance, and DC
accuracy (±1.25 LSB INL) make the MAX1276/MAX1278
ideal for industrial process control, motor control, and
base-station applications.
The MAX1276/MAX1278 come in a 12-pin TQFN pack-
age, and are available in the extended (-40°C to +85°C)
temperature range.
Applications

Data AcquisitionCommunications
Bill ValidationPortable Instruments
Motor Control
Features
1.8Msps Sampling RateOnly 55mW (typ) Power DissipationOnly 1µA (max) Shutdown CurrentHigh-Speed, SPI-Compatible, 3-Wire Serial Interface70dB S/(N + D) at 525kHz Input FrequencyInternal True-Differential Track/Hold (T/H)Internal 4.096V ReferenceNo Pipeline DelaysSmall 12-Pin TQFN Package
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference

AIN+
N.C.
SCLK
N.C.
GNDREFRGND
CNVST
DOUT
MAX1276
MAX1278
AIN-
VDD
TQFN

TOP VIEW
PARTTEMP RANGEPIN-
PACKAGEINPUT
MAX1276ETC+T
-40°C to +85°C12 TQFNUnipolar
MAX1278ETC+T
-40°C to +85°C12 TQFNBipolar
Pin Configuration
Ordering Information

MAX1276
MAX1278
DOUTAIN+
4.7μF
10μF10μF
4.75V TO +5.25V
0.01μF
0.01μF0.01μF
+1.8V TO VDD
AIN-
REF
VDD
DIFFERENTIAL
INPUT
VOLTAGE
RGND
GND
CNVST
SCLK
μC/DSP
Typical Operating Circuit

19-3364; Rev 1; 4/09
SPI/QSPI are trademarks of Motorola, Inc.
EVALUATION KIT
AVAILABLE

+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL= VDD, fSCLK= 28.8MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted. Typical values are at = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6Vto GND................-0.3V to the lower of (VDD+ 0.3V) and +6V
Digital Inputs
to GND.................-0.3V to the lower of (VDD+ 0.3V) and +6V
Digital Output
to GND....................-0.3V to the lower of (VL+ 0.3V) and +6V
Analog Inputs and
REF to GND..........-0.3V to the lower of (VDD+ 0.3V) and +6V
RGND to GND.......................................................-0.3V to +0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
12-Pin TQFN (derate 16.9mW/°C above +70°C)......1349mW
Operating Temperature Range
MAX127_ ETC................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY

Resolution12Bits
Relative AccuracyINL(Notes 1, 2)-1.25+1.25LSB
Differential NonlinearityDNL(Notes 1, 3)-1.0+1.0LSB
Offset Error±6.0LSB
Offset-Error Temperature
Coefficient±1ppm/°C
Gain ErrorOffset nulled±6.0LSB
Gain Temperature Coefficient±2ppm/°C
DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.)

Signal-to-Noise Plus DistortionSINAD(Note 1)6970dB
Total Harmonic DistortionTHDUp to the 5th harmonic (Note 1)-80-76dB
Spurious-Free Dynamic RangeSFDR(Note 1)-83-76dB
Intermodulation DistortionIMDfIN1 = 250kHz, fIN2 = 300kHz-78dB
Full-Power Bandwidth-3dB point, small-signal method20MHz
Full-Linear BandwidthS/(N + D) > 68dB, single ended2.0MHz
CONVERSION RATE

Minimum Conversion TimetCONV(Note 4)0.556µs
Maximum Throughput Rate1.8Mspsi ni m um Thr oug hp ut Rate( N ote 5) 10ksps
Track-and-Hold Acquisition TimetACQ(Note 6)104ns
Aperture Delay5ns
Aperture Jitter(Note 7)30ps
External Clock FrequencyfSCLK28.8MHz
ANALOG INPUTS (AIN+, AIN-)

AIN+ - AIN-, MAX12760VREFDifferential Input Voltage RangeVINAIN+ - AIN-, MAX1278-VREF / 2+VREF / 2V
Absolute Input Voltage Range0VDDV
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL= VDD, fSCLK= 28.8MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted. Typical values are at= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

DC Leakage Current±1µA
Input CapacitancePer input pin16pF
Input Current (Average)Time averaged at maximum throughput rate75µA
REFERENCE OUTPUT (REF)

REF Output Voltage RangeStatic, TA = +25°C4.0864.0964.106V
Voltage Temperature Coefficient±50ppm/°C
ISOURCE = 0 to 2mA0.3Load RegulationISINK = 0 to 200µA0.5mV/mA
Line RegulationVDD = 4.75V to 5.25V, static0.5mV/V
DIGITAL INPUTS (SCLK, CNVST)

Input Voltage LowVIL0.3 x VLV
Input Voltage HighVIH0.7 x VLV
Input Leakage CurrentIILOutput high impedance±0.2±10µA
POWER REQUIREMENTS

Analog Supply VoltageVDD4.755.25V
Digital Supply VoltageVL1.8VDDV
Static, fSCLK = 28.8MHz811
Static, no SCLK57Analog Supply Current,
Normal ModeIDD
Operational, 1.8Msps1013
fSCLK = 28.8MHz2Analog Supply Current,
Partial Power-Down ModeIDDNo SCLK2mA
fSCLK = 28.8MHz1Analog Supply Current,
Full Power-Down ModeIDDNo SCLK0.31µA
Operational, full-scale input at 1.8Msps12.5
Static, fSCLK = 28.8MHz0.41
Partial/full power-down mode,
fSCLK = 28.8MHz0.20.5Digital Supply Current (Note 8)
Static, no SCLK, all modes0.11µA
Positive-Supply RejectionPSRVDD = 5V ±5%, full-scale input±0.2±3.0mV
DIGITAL OUTPUT (DOUT)

Output Load CapacitanceCOUTFor stated timing performance30pF
Output Voltage LowVOLISINK = 5mA, VL ≥ 1.8V0.4V
Output Voltage HighVOHISOURCE = 1mA, VL ≤ 1.8VVL - 0.5VV
Output Leakage CurrentIOLOutput high impedance±0.2±10µA
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Note 1:
-40°C performance is guaranteed by design.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 3:
No missing codes over temperature.
Note 4:
Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 5:
At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 6:
The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNVST. The ICidles in acquisition mode between conversions.
Note 7:
Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 8:
Digital supply current is measured with the VIHlevel equal to VL, and the VILlevel equal to GND.
TIMING CHARACTERISTICS

(VDD= +5V ±5%, VL= VDD, fSCLK= 28.8MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted. Typical values are at = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

SCLK Pulse-Width HightCHVL = 1.8V to VDD15.6ns
SCLK Pulse-Width LowtCLVL = 1.8V to VDD15.6ns
CL = 30pF, VL = 4.75V to VDD14
CL = 30pF, VL = 2.7V to VDD17SCLK Rise to DOUT TransitiontDOUT
CL = 30pF, VL = 1.8V to VDD24
DOUT Remains Valid After SCLKtDHOLDVL = 1.8V to VDD4ns
CNVST Fall to SCLK FalltSETUPVL = 1.8V to VDD10ns
CNVST Pulse WidthtCSWVL = 1.8V to VDD20ns
Power-Up Time; Full Power-DowntPWR-UP2ms
Restart Time; Partial Power-DowntRCV16Cycles
CNVST
SCLK
DOUT
tDHOLD
tDOUT
tSETUP
tCSW
tCLtCH
Figure 1. Detailed Serial-Interface Timing
GND
6kΩCL
DOUTDOUT
GND
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
6kΩ
Figure 2. Load Circuits for Enable/Disable Times
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Typical Operating Characteristics

(VDD= +5V, VL= VDD, fSCLK= 28.8MHz, fSAMPLE= 1.8Msps, TA= -40°C to +85°C, unless otherwise noted. Typical values are
meas- ured at TA= +25°C.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1276)

MAX1276/78 toc01
DIGITAL OUTPUT CODE
INL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1278)
MAX1276/78 toc02
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1276)
MAX1276/78 toc03
DIGITAL OUTPUT CODE
DNL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1278)
MAX1276/78 toc04
DIGITAL OUTPUT CODE
DNL (LSB)
OFFSET ERROR
vs. TEMPERATURE (MAX1276)
MAX1276/78 toc05
TEMPERATURE (°C)
OFFSET ERROR (LSB)35-1510
OFFSET ERROR
vs. TEMPERATURE (MAX1278)
MAX1276/78 toc06
TEMPERATURE (°C)
OFFSET ERROR (LSB)35-1510
GAIN ERROR
vs. TEMPERATURE (MAX1276)
MAX1276/78 toc07
TEMPERATURE (°C)
GAIN ERROR (LSB)3510-15
GAIN ERROR
vs. TEMPERATURE (MAX1278)
MAX1276/78 toc08
TEMPERATURE (°C)
GAIN ERROR (LSB)3510-15
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1276)
MAX1276/78 toc09
ANALOG INPUT FREQUENCY (kHz)
DYNAMIC PERFORMANCE (dB)
SNR
SINAD
Typical Operating Characteristics (continued)
(VDD= +5V, VL= VDD, fSCLK= 28.8MHz, fSAMPLE= 1.8Msps, TA= -40°C to +85°C unless otherwise noted. Typical values are
meas- ured at TA= +25°C.)
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1278)

MAX1276/78 toc10
ANALOG INPUT FREQUENCY (kHz)
DYNAMIC PERFORMANCE (dB)
SNR
SINAD
THD vs. INPUT FREQUENCY

MAX1276/78 toc11
ANALOG INPUT FREQUENCY (kHz)
THD (dB)
MAX1278
MAX1276
SFDR vs. INPUT FREQUENCY

MAX1276/78 toc12
ANALOG INPUT FREQUENCY (kHz)
SFDR (dB)
MAX1278
MAX1276
FFT PLOT (MAX1276)

MAX1276/78 toc13
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fIN = 500kHz
SINAD = 71.0dB
SNR = 71.1dB
THD = -87.1dB
SFDR = 90.2dB
FFT PLOT (MAX1278)

MAX1276/78 toc14
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fIN = 500kHz
SINAD = 71.2dB
SNR = 71.3dB
THD = -95.5dB
SFDR = 90.5dB
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE

MAX1276/78 toc15
SOURCE IMPEDANCE (Ω)
THD (dB)
fIN = 500kHz
fIN = 100kHz
MAX1276/MAX1278
TWO-TONE IMD PLOT (MAX1276)

MAX1276/78 toc16
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fSAMPLE = 2Msps
fIN1 = 250.039kHz
fIN2 = 300.059kHz
IMD = -84.2dB
fIN1fIN2
TWO-TONE IMD PLOT (MAX1278)

MAX1276/78 toc17
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fSAMPLE = 2Msps
fIN1 = 250.039kHz
fIN2 = 300.059kHz
IMD = -81.8dB
fIN1fIN2
VDD/VL FULL POWER-DOWN SUPPLY
CURRENT vs. TEMPERATURE

MAX1276/78 toc18
TEMPERATURE (°C)
SUPPLY CURRENT (3510-15
VDD, fSCLK = 28.8MHz
VDD, NO SCLK
VL, NO SCLK
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
VL PARTIAL/FULL POWER-DOWN SUPPLY
CURRENT vs. TEMPERATURE

MAX1276/78 toc19
TEMPERATURE (°C)
SUPPLY CURRENT (3510-15
VL = 5V, fSCLK = 28.8MHz
VL = 3V, fSCLK = 28.8MHz
VDD SUPPLY CURRENT
vs. TEMPERATURE

MAX1276/78 toc20
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
CONVERSION, fSCLK = 28.8MHz
PARTIAL POWER-DOWN
VDD SUPPLY CURRENT
vs. CONVERSION RATE

MAX1276/78 toc21
fSAMPLE (kHz)
SUPPLY CURRENT (mA)
Typical Operating Characteristics (continued)
(VDD= +5V, VL= VDD, fSCLK= 28.8MHz, fSAMPLE= 1.8Msps, TA= -40°C to +85°C unless otherwise noted. Typical values are
meas- ured at TA= +25°C.)
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)

(VDD= +5V, VL= VDD, fSCLK= 28.8MHz, fSAMPLE= 1.8Msps, TA= -40°C to +85°C unless otherwise noted. Typical values are
meas- ured at TA= +25°C.)
VL SUPPLY CURRENT
vs. TEMPERATURE

MAX1276/78 toc22
TEMPERATURE (°C)
L SUPPLY CURRENT (mA)3510-15
CONVERSION, fSCLK = 28.8MHz
FULL/PARTIAL POWER-DOWN, fCLK = 28.8MHz
VL SUPPLY CURRENT
vs. CONVERSION RATE

MAX1276/78 toc23
fSAMPLE (kHz)
L SUPPLY CURRENT (mA)
VL = 5V
VL = 3V
VL = 1.8V
REFERENCE VOLTAGE
vs. TEMPERATURE

MAX1276/78 toc24
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)3510-15
REFERENCE VOLTAGE
vs. LOAD CURRENT (SOURCE)
MAX1276/78 toc25
LOAD CURRENT (mA)
REFERENCE VOLTAGE (V)642
REFERENCE VOLTAGE
vs. LOAD CURRENT (SINK)
MAX1276/78 toc26
REFERENCE VOLTAGE (V)
0500
MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Pin Description
PINNAMEFUNCTION
AIN-Negative Analog InputREFReference Voltage Output. Internal 4.096V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.RGNDReference Ground. Connect RGND to GND.
4VDDPositive Analog Supply Voltage (+4.75V to +5.25V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.
5, 11N.C.No ConnectionGNDGround. GND is internally connected to EP.
7VLPositive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.DOUTSerial Data Output. Data is clocked out on the rising edge of SCLK.CNVSTConvert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.SCLKSerial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.AIN+Positive Analog InputEPExposed Paddle. EP is internally connected to GND.
Detailed Description

The MAX1276/MAX1278 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1276/MAX1278.
RGND
AIN +
GND
DOUT
SCLK
CNVSTCONTROL
LOGIC AND
TIMING
AIN -VDD
REF
12-BIT
SAR
ADC
MAX1276
MAX1278
TRACK AND
HOLD
OUTPUT
BUFFER
REF
4.096V
Figure 3. Functional Diagram
CIN+RIN+
RIN-CIN-
VAZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
ACQUISITION MODE
CIN+RIN+
RIN-CIN-
VAZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
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