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MAX1246BCEEMAXIMN/a90avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
MAX1246BCPEN/a10avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
MAX1247ACEEMAXIMN/a9avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
MAX1247ACPEMAXIMN/a2avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
MAX1247BCEEN/a10avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
MAX1247AEEEMAXIMN/a4avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
MAX1247BCPEMAXIMN/a2avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
MAX1247BEEEMAXIMN/a5avai+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16


MAX1246BCEE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16General Description ________
MAX1246BCEE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16Applications__________Typical Operating CircuitPortable Data LoggingMedical Instruments+3VPen Digit ..
MAX1246BCPE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16Applications+3VPortable Data Logging Data AcquisitionVCH0 V DDDD 0.1μFMedical Instruments Battery- ..
MAX1247ACEE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16FeaturesThe MAX1246/MAX1247 12-bit data-acquisition systems' 4-Channel Single-Ended or 2-Channel co ..
MAX1247ACEE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16ELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f ..
MAX1247ACPE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16FeaturesThe MAX1246/MAX1247 12-bit data-acquisition systems' 4-Channel Single-Ended or 2-Channel co ..
MAX3668EHJ+ ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power ControlELECTRICAL CHARACTERISTICS(V = +3.14V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3668EHJ+T ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power Controlapplications up to 622Mbps. It accepts differentialPECL inputs, provides bias and modulation curren ..
MAX3668EHJ+T ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power ControlApplicationsMAX3668EHJ+ -40°C to +85°C 32 TQFP (5mm x 5mm)622Mbps SDH/SONET Access NodesMAX3668E/D ..
MAX3669EHJ ,+3.3V / 622Mbps SDH/SONET Laser Driver with Current Monitors and APCELECTRICAL CHARACTERISTICS(V = +3.14V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3669EHJ ,+3.3V / 622Mbps SDH/SONET Laser Driver with Current Monitors and APCApplicationsNote A: Dice are designed to operate over a -40°C to +140°C622Mbps SDH/SONET Access Nod ..
MAX3669EHJ+ ,+3.3V, 622Mbps SDH/SONET Laser Driver with Current Monitors and APCFeaturesThe MAX3669 is a complete, +3.3V laser driver with auto-♦♦ +3.3V or +5.0V Single-Supply Ope ..


MAX1246BCEE-MAX1246BCPE-MAX1247ACEE-MAX1247ACPE-MAX1247AEEE-MAX1247BCEE-MAX1247BCPE-MAX1247BEEE
+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
_______________General Description
The MAX1246/MAX1247 12-bit data-acquisition systems
combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. The MAX1246 oper-
ates from a single +2.7V to +3.6V supply; the MAX1247
operates from a single +2.7V to +5.25V supply. Both
devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and Microwire™ devices without external logic. A
serial strobe output allows direct connection to TMS320-
family digital signal processors. The MAX1246/MAX1247
use either the internal clock or an external serial-interface
clock to perform successive-approximation analog-to-
digital conversions.
The MAX1246 has an internal 2.5V reference, while the
MAX1247 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDNpin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX1246/MAX1247, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
The MAX1246/MAX1247 are available in a 16-pin DIP and
a small QSOP that occupies the same board area as an
8-pin SO.
For 8-channel versions of these devices, see the
MAX146/MAX147 data sheet.
________________________Applications

Portable Data LoggingData Acquisition
Medical InstrumentsBattery-Powered Instruments
Pen DigitizersProcess Control
____________________________Features
4-Channel Single-Ended or 2-Channel
Differential Inputs
Single-Supply Operation:
+2.7V to +3.6V (MAX1246)
+2.7V to +5.25V (MAX1247)
Internal 2.5V Reference (MAX1246)Low Power:1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
1µA (power-down mode)
SPI/QSPI/Microwire/TMS320-Compatible
4-Wire Serial Interface
Software-Configurable Unipolar or Bipolar Inputs16-Pin QSOP Package (same area as 8-pin SO)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
__________Typical Operating Circuit

SPI and QSPI are registered trademarks of Motorola, Inc. Microwire is a registered trademark of National Semiconductor Corp.
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500V
applied to VREF pin; TA= TMINto TMAX;unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND.................................................-0.3V to 6V
AGND to DGND......................................................-0.3V to 0.3V
CH0–CH3, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF to AGND...........................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND..............................................-0.3V to 6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C).........842mW
QSOP (derate 8.36mW/°C above +70°C)...................667mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
MAX1246_C_E/MAX1247_C_E..........................0°C to +70°C
MAX1246_E_E/MAX1247_E_E........................-40°C to +85°C
MAX1246_MJE/MAX1247_MJE....................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500V
applied to VREF pin; TA= TMINto TMAX;unless otherwise noted.)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500V
applied to VREF pin; TA= TMINto TMAX;unless otherwise noted.)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
__________________________________________Typical Operating Characteristics

(VDD= 3.0V, VREF = 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
TIMING CHARACTERISTICS

(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); TA= TMINto TMAX; unless otherwise noted.)
Note 1:
Tested at VDD= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX1246—internal reference, offset nulled; MAX1247—external reference (VREF = +2.500V), offset nulled.
Note 4:
Ground “on” channel; sine wave applied to all “off” channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
The common-mode range for the analog inputs is from AGND to VDD.
Note 7:
Guaranteed by design. Not subject to production testing.
Note 8:
External load should not change during conversion for specified accuracy.
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note10:
Measured as |VFS(2.7V) - VFS(VDD, MAX)|.
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
____________________________Typical Operating Characteristics (continued)

(VDD= 3.0V, VREF = 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
____________________________Typical Operating Characteristics (continued)

(VDD= 3.0V, VREF= 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
______________________________________________________________Pin Description
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
_______________Detailed Description

The MAX1246/MAX1247 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX1246/
MAX1247.
Pseudo-Differential Input

The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH3, and IN-is switched to COM. In
differential mode, IN+ and IN-are selected from two
pairs: CH0/CH1 and CH2/CH3. Configure the channels
with Tables 2 and 3. Please note that the codes for
CH0–CH3 in the MAX1246/MAX1247 correspond to the
codes for CH2–CH5 in the eight-channel (MAX146/
MAX147) versions.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN-(the selected analog input) to AGND.
During the acquisition interval, the channel selected
as the positive input (IN+) charges capacitor CHOLD.
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
input control word has been entered. At the end of the
acquisition interval, the T/H switch opens, retaining
charge on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 12-bit resolution. This action is equiv-
alent to transferring a 16pF x [(VIN+) -(VIN-)] charge
from CHOLDto the binary-weighted capacitive DAC,
which in turn forms a digital representation of the analog
input signal.
Track/Hold

The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
Circuit,the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 12-bit conversion result). See Figure
19 for MAX1246/MAX1247 QSPI connections.
Simple Software Interface

Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.Use a general-purpose I/O line on the CPU to pull low.Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.Pull CShigh.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital Output

In unipolar input mode, the output is straight binary
(Figure 16). For bipolar inputs, the output is two’s com-
plement (Figure 17). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Clock Modes

The MAX1246/MAX1247 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX1246/MAX1247. The T/H acquires the input signal
as the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 6–9 show the timing characteristics
common to both modes.
External Clock

In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 5). SSTRB and DOUT go into a high-impedance
state when CSgoes high; after the next CSfalling edge,
SSTRB outputs a logic low. Figure 7 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial clock interruptions could cause the conversion
interval to exceed 120µs.
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
Table 2.Channel Selection in Single-Ended Mode (SGL/D
DIIFF= 1)
Table 3.Channel Selection in Differential Mode (SGL/DDIIFF= 0)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
Internal Clock

In internal clock mode, the MAX1246/MAX1247 generate
their own conversion clocks internally. This frees the µP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN= FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8). CSdoes
not need to be held low once a conversion is started.
Pulling CShigh prevents data from being clocked into
the MAX1246/MAX1247 and three-states DOUT, but it
does not adversely affect an internal clock mode
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