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MAX1202AEAPMAXIMN/a20avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
MAX1202AEPPMAXIMN/a2avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
MAX1202BCAPMAXIMN/a11avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
MAX1202BEAPMAXIMN/a5avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
MAX1203ACAPMAXIMN/a20avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
MAX1203AEAPMAXIMN/a31avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
MAX1203BCAPMAXIMN/a21avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
MAX1203BCPPMAXIMN/a35avai5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE


MAX1203BCPP ,5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACEApplications2CH1 19 SCLK5V/3V Mixed-Supply Systems CH2 3 18 CSCH3 4 MAX1202Data Acquisition 17 DINM ..
MAX1204AEAP+ ,5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital InterfaceApplications5V/3V Mixed-Supply SystemsTOP VIEW +Data AcquisitionCH0 1 20 VDDProcess ControlCH1 2 19 ..
MAX1204BCAP ,5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACEApplicationsTOP VIEW5V/3V Mixed-Supply Systems20CH0 1 VDDData AcquisitionCH1 2 19 SCLKProcess Cont ..
MAX1205EMH+ ,+5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADCFeaturesThe MAX1205 is a 14-bit, monolithic, analog-to-digital♦ Monolithic, 14-Bit, 1Msps ADCconver ..
MAX1209ETL+ ,12-Bit, 80Msps, 3.3V IF-Sampling ADCfeatures a 3µW power-down to ±1.15Vmode to conserve power during idle periods.♦ Common-Mode Referen ..
MAX120CAG ,500ksps, 12-Bit ADCs with Track/Hold And RefrenceELECTRICAL CHARACTERISTICS (VDD = +4 75V to +5 25V, Vss = -10EV to -15.75V, (CLN = 8MHZ for MAX120 ..
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP+ ,Upstream CATV Amplifier
MAX3510EEP+T ,Upstream CATV Amplifier
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MAX1202AEAP-MAX1202AEPP-MAX1202BCAP-MAX1202BEAP-MAX1203ACAP-MAX1203AEAP-MAX1203BCAP-MAX1203BCPP
5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACE
General Description
The MAX1202/MAX1203 are 12-bit data-acquisition
systems specifically designed for use in applications
with mixed +5V (analog) and +3V (digital) supply volt-
ages. They operate with a single +5V analog supply or
dual ±5V analog supplies, and combine an 8-channel
multiplexer, high-bandwidth track/hold, and serial inter-
face with high conversion speed and low power con-
sumption.
A 4-wire serial interface connects directly to
SPI™/MICROWIRE™ devices without external logic,
and a serial strobe output allows direct connection to
TMS320-family digital signal processors. The
MAX1202/MAX1203 use either the internal clock or an
external serial-interface clock to perform successive-
approximation analog-to-digital conversions. The serial
interface operates at up to 2MHz.
The MAX1202 features an internal 4.096V reference,
while the MAX1203 requires an external reference. Both
parts have a reference-buffer amplifier that simplifies
gain trim. They also have a VL pin that is the power
supply for the digital outputs. Output logic levels (3V,
3.3V, or 5V) are determined by the value of the voltage
applied to this pin.
These devices provide a hard-wired SHDNpin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the devices. A
quick turn-on time enables the MAX1202/MAX1203 to
be shut down between conversions, allowing the user
to optimize supply currents. By customizing power-
down between conversions, supply current can drop
below 10µA at reduced sampling rates.
The MAX1202/MAX1203 are available in 20-pin SSOP
and DIP packages, and are specified for the commer-
cial, extended, and military temperature ranges.
Applications

5V/3V Mixed-Supply Systems
Data Acquisition
High-Accuracy Process Control
Battery-Powered Instruments
Medical Instruments
Features
8-Channel Single-Ended or 4-Channel
Differential Inputs
Operates from Single +5V or Dual ±5V SuppliesUser-Adjustable Output Logic Levels
(2.7V to 5.25V)
Low Power:1.5mA (operating mode)
2µA (power-down mode)
Internal Track/Hold, 133kHz Sampling RateInternal 4.096V Reference (MAX1202)SPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
Software-Configurable Unipolar/Bipolar Inputs20-Pin DIP/SSOP
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Pin Configuration
Typical Operating Circuit appears at end of data sheet.

SPI is a registered trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND................................................................-0.3V to 6V...............................................................-0.3V to (VDD+ 0.3V)
VSSto GND.................................................................0.3V to -6V
VDDto VSS................................................................-0.3V to 12V
CH0–CH7 to GND............................(VSS- 0.3V) to (VDD+ 0.3V)
CH0–CH7 Total Input Current...........................................±20mA
REF to GND................................................-0.3V to (VDD+ 0.3V)
REFADJ to GND.........................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND.................................-0.3V to (VDD+ 0.3V)
Digital Outputs to GND.................................-0.3V to (VL + 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C)...........889mW
SSOP (derate 8.00mW/°C above +70°C).....................640mW
CERDIP (derate 11.11mW°C above +70°C).................889mW
Operating Temperature Ranges
MAX1202_C_P/MAX1203_C_P............................0°C to +70°C
MAX1202_E_P/MAX1203_E_P..........................-40°C to +85°C
MAX1202BMJP/MAX1203BMJP.....................-55°C to +125°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, VREF= 4.096V applied to REF pin; = TMIN toTMAX; unless otherwise noted.)
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, VREF= 4.096V applied to REF pin; = TMIN toTMAX; unless otherwise noted.)
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, VREF= 4.096V applied to REF pin; = TMIN toTMAX; unless otherwise noted.)
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, VREF= 4.096V applied to REF pin; = TMIN toTMAX; unless otherwise noted.)
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
TIMING CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V, VSS= 0V or -5V ±5%, TA= TMINto TMAX,unless otherwise noted.)
Note 1:
Tested at VDD= 5.0V; VSS= 0V; unipolar-input mode.
Note 2:
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 3:
MAX1202—internal reference, offset nulled; MAX1203—external reference (VREF= 4.096V), offset nulled.
Note 4:
On-channel grounded; sine wave applied to all off-channels.
Note 5:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
Common-mode range for analog inputs is from VSSto VDD.
Note 8:
External load should not change during the conversion for specified accuracy.
Note 9:
Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;
REFADJ = GND. Shutdown supply current is also dependent on VIH(Figure 12c).
Note 10:
Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CShigh). When the outputs are
active (CSlow), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11:
Measured at VSUPPLY+ 5% and VSUPPLY - 5% only.
Note 12:
Measured at VL = 2.7V and VL = 3.6V.
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
__________________________________________Typical Operating Characteristics

(VDD= 5V ±5%; VL = 2.7V to 3.6V; VSS= 0V; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle
(133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, VREF= 4.096V applied to REF pin; TA = +25°C;
unless otherwise noted.)
______________________________________________________________Pin Description
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
____________________________Typical Operating Characteristics (continued)

(VDD= 5V ±5%; VL = 2.7V to 3.6V; VSS= 0V; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle
(133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, VREF= 4.096V applied to REF pin; TA = +25°C;
unless otherwise noted.)
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
_______________Detailed Description

The MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to 3V microproces-
sors (µPs).Figure 3 is the MAX1202/MAX1203 block
diagram.
Pseudo-Differential Input

Figure 4 shows the ADC’s analog comparator’s sam-
pling architecture. In single-ended mode, IN+ is inter-
nally switched to CH0–CH7 and IN-is switched to
GND. In differential mode, IN+ and IN-are selected
from pairs of CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels using Tables 3
and 4.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable (typi-
cally within ±0.5LSB, within ±0.1LSB for best results)
with respect to GND during a conversion. To do this,
connect a 0.1µF capacitor from IN-(of the selected
analog input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on CHOLDas a
sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution.
This action is equivalent to transferring a charge of
16pF x [(VIN+) -(VIN-)] from CHOLDto the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable TimeFigure 3. Block Diagram
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Track/Hold

The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN-is con-
nected to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN-con-
nects to the “-” input if the converter is set up for differen-
tial inputs, and the difference of ‰|N+ -IN-‰ is sampled.
The positive input connects back to IN+, at the end of
the conversion, and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
acquisition time increases and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following:
tACQ= 9 x (RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1.5µs. Source
impedances below 1kWdo not significantly affect the
ADC’s AC performance. Higher source impedances can
be used if an input capacitor is connected to the analog
inputs, as shown in Figure 5. Note that the input capaci-
tor forms an RC filter with the input source impedance,
limiting the ADC’s signal bandwidth.
Table 1a.Unipolar Full Scale and Zero
Scale
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Input Bandwidth

The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth. Therefore it is possible to digi-
tize high-speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Range and Input Protection

Internal protection diodes, which clamp the analog
inputs to VDDand VSS, allow the analog input pins to
swing from (VSS-0.3V) to (VDD+ 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV, or
be lower than VSSby 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels more than 2mA.

The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Quick Look

Use the circuit of Figure 5 to quickly evaluate the
MAX1202/MAX1203’s analog performance. The
MAX1202/MAX1203 require a control byte to be written
to DIN before each conversion. Tying DIN to +3V feeds
in control byte $FF hex, which triggers single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result shifts out of DOUT. Varying the ana-
log input to CH7 alters the sequence of bits from
DOUT. A total of 15 clock cycles per conversion is
required. All SSTRB and DOUT output transitions occur
on SCLK’s falling edge.
How to Start a Conversion

Clocking a control byte into DIN starts conversion on
the MAX1202/MAX1203. With CSlow, each rising edge
on SCLK clocks a bit from DIN into the MAX1202/
MAX1203’s internal shift register. After CSfalls, the first
logic “1” bit defines the control byte’s MSB. Until this
first “start” bit arrives, any number of logic “0” bits can
be clocked into DIN with no effect. Table 2 shows the
control-byte format.
The MAX1202/MAX1203 are fully compatible with
SPI/MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE and
SPI both transmit and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
Table 1b.Bipolar Full Scale, Zero Scale,
and Negative Full Scale
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
MAX1202/MAX1203, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Table 2. Control-Byte Format
Table 3. Channel Selection in Single-Ended Mode (SGL/DDIIFF= 1)
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