MAX1101CWG ,Single-Chip / 8-Bit CCD Digitizer with Clamp and 6-Bit PGAELECTRICAL CHARACTERISTICS(V = V = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µ ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsential analog input range is ±2.2V when using the internal • 117dB SNR at 1ksps referen ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCElectrical Characteristics(V = +3.0V to +3.6V, V = +2.7V to V , f = 24.576MHz, f = 16ksps, V = +2.5 ..
MAX11040KGUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsDRDYOUTAIN1+24-BIT DIGITALADC FILTERAIN1-● Power-Protection Relay Equipment REGISTERS A ..
MAX11044ETN+ ,4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCsELECTRICAL CHARACTERISTICS(V = +4.75V to +5.25V, V = +2.70V to +5.25V, V = V = V = 0V, V = internal ..
MAX11045ETN+ ,4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCsELECTRICAL CHARACTERISTICS(V = +4.75V to +5.25V, V = +2.70V to +5.25V, V = V = V = 0V, V = internal ..
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA+ ,±80V Fault-Protected, Fail-Safe, 1/4-Unit Load, +3.3V RS-485 Transceiver
MAX3430ESA+T ,±80V Fault-Protected, Fail-Safe, 1/4-Unit Load, +3.3V RS-485 Transceiver
MAX3440EESA ,15kV ESD-Protected / 60V Fault-Protected / 10Mbps / Fail-Safe RS-485/J1708 Transceivers
MAX3440EESA+ ,±15kV ESD-Protected, ±60V Fault-Protected, 10Mbps, Fail-Safe RS-485/J1708 Transceivers
MAX1101CWG
Single-Chip / 8-Bit CCD Digitizer with Clamp and 6-Bit PGA
_______________General DescriptionThe MAX1101 is a highly integrated IC designed pri-
marily for digitizing the output of a linear CCD array. It
provides the components required for all necessary
analog functions, including clamp circuitry for black-
level correction or correlated double sampling (CDS), a
three-input multiplexer (mux), and an 8-bit analog-to-
digital converter (ADC).
The MAX1101 operates with a sample rate up to 1MHz
and with a wide range of linear CCDs. The logic inter-
face is serial, and a single input sets the bidirectional
data line as either data in or data out, thus minimizing
the I/O pins required for communication.
Packaged in a 24-pin SO, the MAX1101 is available in
the commercial (0°C to +70°C) temperature range.
________________________ApplicationsScanners
Fax Machines
Digital Copiers
CCD Imaging
____________________________Features1.0 Million Pixels/sec Conversion RateBuilt-In Clamp Circuitry for Black-Level
Correction or Correlated Double Sampling64-Step PGA, Programmable from Gain = -2 to -10Auxiliary Mux Inputs for Added VersatilityCompatible with a Large Range of CCDs8-Bit ADC IncludedSpace-Saving, 24-Pin SO Package
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
___________________________________________________Typical Operating Circuit19-1166; Rev 0; 12/96
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= VREFBIAS= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, CEXT= 47nF, TA= TMINto TMAX,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND............................................................-0.3V to +12V
All Pins to GND...........................................-0.3V to (VDD+ 0.3V)
Current into Every Pin (except VDD).................................±20mA
Current into VDD...............................................................±50mA
Continuous Power Dissipation (TA= +70°C)
SO (derate 11.76mW/°C above +70°C)......................941mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
ELECTRICAL CHARACTERISTICS (continued)(VDD= VREFBIAS= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, CEXT= 47nF, TA= TMINto TMAX,
unless otherwise noted.)
Note 1:Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as
performance may degrade, particularly at high temperatures.
Note 2:Production test equipment settling time prohibits leakage measurements below 1nA.
Lab equipment has shown the MAX1101 switch input leakage below 1pA at TA= +25°C, and below 50pA at TA= +70°C.
Note 3:Not a test parameter. Recommended for optimal performance.
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
______________________________________________________________Pin Description
_______________Detailed Description
OverviewThe MAX1101 directly processes the pixel stream from
a monochrome CCD, and removes black level, offset,
and noise errors through an internal clamp circuit,
which can be used as a correlated double sampler
(CDS). It uses a 6-bit, programmable-gain amplifier
(PGA) to adjust gain. A three-input multiplexer (mux)
selects either the PGA output or two unassigned inputs
(AIN1, AIN2). The processed analog signal is digitized
by an 8-bit, half-flash analog-to-digital converter (ADC),
and output serially through the DATA pin.
Digital data is input and output through the bidirectional
serial pin (DATA) synchronously with the external serial
clock (SCLK). When MODE = 0, the mux channels and
the PGA gain can be programmed via DATA. With MODE
= 1 (high), ADC serial data is output through this pin.
Figure 1. MAX1101 Functional Diagram
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
Programmable-Gain AmplifierThe PGA amplifies the differential video signal from the
CCD (at CCDIN). Gain is settable with the 6-bit con-
trol word from -2 to -10 in 64 steps, in increments of
-0.125. The PGA also provides for periodic DC restora-
tion of the capacitively coupled input.
As shown in Figure 2, the switched-capacitor amplifier’s
gain is set by the ratio CI/CF. The input is sampled on
the CIcapacitors, which is a set of equal capacitors.
The 6-bit gain control word determines the number
of capacitors used. Thus the PGA gain is set from
-2 to -10.
A voltage equal to VREF-is applied to the PGA’s nonin-
verting input. This offsets the PGA output to be within
the range of the ADC (VREF-toVREF+).
Clamp CircuitAs shown in Figure 2, the CCD output is connected to
the MAX1101 input (CCDIN) through an external
capacitor, which removes the potentially large DC
common-mode voltages from the input signal.
Whenever CLAMP is high, the CLAMP switch is closed
and CEXTis charged to VREF+. It can be actuated
either once per pixel (sampling reset level) or less fre-
quently (such as for restoring optical black level once
per line), as required by the application.
VIDSAMP controls the sampling of the video signal
and offset nulling of the PGA. To null out the offset,
VIDSAMP causes switches S1 and S1P to close, plac-
ing the amplifier in a unity-gain configuration, as shown
in Figure 3a. This configuration causes the amplifier’s
offset voltage to be stored on CF. In the next portion of
the cycle, when VIDSAMP returns low, the S1 switches
are opened and S2 is closed (Figure 3b). This is the
standard inverting op-amp configuration. The only dif-
ference is that capacitors are used to set the gain, and
the amplifier’s offset voltage has been stored on these
capacitors and is thus canceled. The amplifier’s output
is [CF/CI] x VVIDEO+ VREF-. The CDS function is shown
in Figure 4.
ADCThe ADC uses a recycling half-flash conversion tech-
nique in which a 4-bit flash ADC section achieves an
8-bit result in two steps (Figure 5). Using 15 compara-
tors, the flash ADC compares the unknown input
voltage to the reference ladder (using REF+ and REF-)
and provides the upper four data bits.
An internal digital-to-analog converter (DAC) uses the
four most significant bits (MSBs) to generate the analog
result from the first flash conversion and a residue volt-
age that is the difference between the unknown voltage
MAX1101
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGAand the DAC output. The residue is then compared
again with the flash comparators to obtain the lower
four data bits.
Single-shot timers control the timing of the two conver-
sion steps. Once both MSBs and LSBs have been
determined, the comparators return to input-acquisi-
tion/auto-zero mode.
REF+ and REF-The REF+ and REF- pins set the ADC’s full-scale range.
The optimum input range is +0.5V to +3.0V. Figure 6
shows a matched resistive ladder that generates the
reference voltages. Four pins are available: REF+,
REF-, REFBIAS, and REFGND. If 5.00V is applied to
REFBIAS while REFGND is grounded, then 3.00V and
0.50V are generated at REF+ and REF-, respectively.
For increased accuracy or power-supply immunity,
REF+ can be connected to an external +3.00V refer-
ence. If this is done, the accuracy must be better than
±5%. REFBIAS should be left open in this case.
MultiplexerThe mux selects either the output of the PGA or one of
two other inputs to the ADC. The mux switching is
break-before-make to prevent transient shorts between
channels.The first two bits of the input control byte
select the mux input channel (Table 1).
Serial-Interface LogicThe serial interface inputs and outputs data in 8-bit
words. The interface is controlled by four signals:
MODE, LOAD, DATA, and SCLK.
Figure 4. Correlated Double Sampler (CDS)
