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M93S56-WMN3TP/S
Automotive 2 Kbit MICROWIRE serial access EEPROM with Block Protection
March 2012 Doc ID 022567 Rev 1 1/28
M93S66-125 M93S56-125
M93S46-125Automotive 4-Kbit, 2-Kbit and 1-Kbit
MICROWIRE serial EEPROM with block protection
Datasheet − production data
Features Industry standard MICROWIRETM bus Single supply voltage: 2.5 to 5.5V Single organization: by word (x16) Programming instructions that work on: word or
entire memory Self-timed programming cycle with auto-erase User-defined write-protected area Page Write mode (4 words) Ready/Busy signal during programming Speed: 2-MHz clock rate, 5 ms write time Sequential Read operation Enhanced ESD/Latch-up behavior More than 1 million Erase/Write cycles More than 40-year data retention
Contents M93S66-125 M93S56-125 M93S46-1252/28 Doc ID 022567 Rev 1
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-on data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write protection and the Protection Register . . . . . . . . . . . . . . . . . . . . 164.1 Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Protection Register Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Protection Register Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 Protection Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
M93S66-125 M93S56-125 M93S46-125 List of tables
Doc ID 022567 Rev 1 3/28
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Instruction set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Instruction set for the M93S56, M93S66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Operating conditions (M93Sx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. AC measurement conditions (M93Sx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. DC characteristics (M93Sx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. AC characteristics (M93Sx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. SO8 narrow – 8 lead plastic small outline, 150 mils body width, mechanical data. . . . . . . 25
Table 11. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of figures M93S66-125 M93S56-125 M93S46-125
4/28 Doc ID 022567 Rev 1
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. READ, WRITE, WEN and WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. PAWRITE and WRAL sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. PREAD, PRWRITE and PREN sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. PRCLEAR and PRDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. AC testing input output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Synchronous timing (START and OPCODE INPUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Synchronous timing (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Synchronous timing (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. SO8 narrow – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . 25
M93S66-125 M93S56-125 M93S46-125 Description
Doc ID 022567 Rev 1 5/28
1 Description
The M93S66-125, M93S56-125 and M93S46-125 are a range of 4-Kbit, 2-Kbit, and 1-Kbit
serial Electrically Erasable PROgrammable Memory (EEPROM) products. They are
collectively referred to as M93Sx6-125.
Figure 1. Logic diagram
The M93Sx6-125 is accessed through a Serial Data Input (D) and Serial Data Output (Q)
using the MICROWIRE bus protocol. The memory is divided into 256, 128 and 64 x16-bit
words (respectively for M93S66-125, M93S56-125 and M93S46-125).
The M93Sx6-125 is accessed by a set of instructions which includes Read, Write,
Page Write, Write All and instructions used to set the memory protection. These are
summarized in Table 2 and Table3.
A Read data from memory (READ) instruction loads the address of the first word to be read
into an internal address pointer. The data contained at this address is then clocked out
serially. The address pointer is automatically incremented after the data is output and, if the
Table 1. Signal names
Description M93S66-125 M93S56-125 M93S46-125
6/28 Doc ID 022567 Rev 1
Chip Select Input (S) is held High, the M93Sx6-125 can output a sequential stream of data
words. In this way, the memory can be read as a data stream from 16 to 4096 bits (for the
M93S66-125), or continuously as the address counter automatically rolls over to 00h when
the highest address is reached.
Within the time required by a programming cycle (tW), up to 4 words may be written with
help of the Page Write instruction. the whole memory may also be erased, or set to a
predetermined pattern, by using the Write All instruction.
Within the memory, a user defined area may be protected against further Write instructions.
The size of this area is defined by the content of a Protection register, located outside of the
memory array. As a final protection step, data may be permanently protected by
programming a One Time Programming (OTP) bit which locks the Protection register
content.
Programming is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an erase cycle
prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the
word locations of the M93Sx6-125, the Page Write instruction writes up to 4 words of 16 bits
to sequential locations, assuming in both cases that all addresses are outside the Write
protected area. After the start of the programming cycle, a Busy/Ready signal is available on
Serial Data Output (Q) when Chip Select Input (S) is driven High.
An internal Power-on Data Protection mechanism in the M93Sx6-125 inhibits the device
when the supply is too low.
Figure 2. 8-pin package connections (top view)
Note: See Section 9: Package mechanical data section for package dimensions, and how to
identify pin-1.
M93S66-125 M93S56-125 M93S46-125 Power-on data protection
Doc ID 022567 Rev 1 7/28 Power-on data protection o prevent data corruption and inadvertent write operations during power-up, a Power-on
Reset (POR) circuit resets all internal programming circuitry, and sets the device in the Write
Disable mode. At Power-up and Power-down, the device must not be selected (that is, Chip Select
Input (S) must be driven Low) until the supply voltage reaches the operating value VCC
specified in Section 8: DC and AC parameters. When VCC reaches its valid level, the device is properly reset (in the Write Disable
mode) and is ready to decode and execute incoming instructions.
For the M93Sx6-125, the POR threshold voltage is around 1.5V.
3 Instructions
The instruction set of the M93Sx6-125 devices contains seven instructions, as summarized
in Table 2 and Table 3. Each instruction consists of the following: Each instruction is preceded by a rising edge on Chip Select Input (S) with
Serial Clock (C) being held Low. A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of
Serial Clock (C). Two opcode bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the opcode). The address bits of the byte or word that is to be accessed. For the M93S46-125, the
address is made up of 6 bits (see Table 2). For the M93S56-125 and M93S66-125, the
address is made up of 8 bits (see Table 3).
The M93Sx6-125 devices are fabricated in CMOS technology and are therefore able to run
as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table9.
Instructions M93S66-125 M93S56-125 M93S46-125
8/28 Doc ID 022567 Rev 1
Table 2. Instruction set for the M93S46 X = Don't Care bit.
M93S66-125 M93S56-125 M93S46-125 Instructions
Doc ID 022567 Rev 1 9/28
Table 3. Instruction set for the M93S56, M93S66 X = Don't Care bit. Address bit A7 is not decoded by the M93S56-125.
Instructions M93S66-125 M93S56-125 M93S46-125
10/28 Doc ID 022567 Rev 1
M93S66-125 M93S56-125 M93S46-125 Instructions
Doc ID 022567 Rev 1 11/28
3.1 Read
The Read Data from Memory (READ) instruction outputs serial data on Serial Data
Output (Q). When the instruction is received, the opcode and address are decoded, and the
data from the memory is transferred to an output shift register. A dummy 0 bit is output first,
followed by the 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Sx6-125 automatically increments
the internal address register and clocks out the next byte (or word) as long as the Chip
Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or
words) and a continuous stream of data can be read.
3.2 Write Enable and Write Disable
The Write Enable (WEN) instruction enables the future execution of write instructions, and
the Write Disable (WDS) instruction disables it. When power is first applied, the
M93Sx6-125 initializes itself so that write instructions are disabled. After a Write Enable
(WEN) instruction has been executed, writing remains enabled until a Write Disable (WDS)
instruction is executed, or until VCC falls below the power-on reset threshold voltage. To
protect the memory contents from accidental corruption, it is advisable to issue the Write
Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ)
instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions.
3.3 Write
The Write Data to Memory (WRITE) instruction is composed of the Start bit plus the opcode
followed by the address and the 16 data bits to be written.
Write Enable (W) must be held High before and during the instruction. Input address and
data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or
after this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed.
While the M93Sx6-125 is performing a write cycle, but after a delay (tSLSH) before the status
information becomes available, Chip Select Input (S) can be driven High to monitor the
status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6-125 is still
busy, and High when the cycle is complete, and the M93Sx6-125 is ready to receive a new
instruction. The M93Sx6-125 ignores any data on the bus while it is busy on a write cycle.
Once the M93Sx6-125 is Ready, Serial Data Output (Q) is driven High, and remains in this
state until a new start bit is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected
or left running after the start of a write cycle.
Instructions M93S66-125 M93S56-125 M93S46-125
12/28 Doc ID 022567 Rev 1
3.4 Page Write
A Page Write to Memory (PAWRITE) instruction contains the first address to be written,
followed by up to 4 data words.
After the receipt of each data word, bits A1-A0 of the internal address register are
incremented, the high order bits remaining unchanged (A7-A2 for M93S66-125, M93S56-
125; A5-A2 for M93S46-125). Users must take care, in the software, to ensure that the last
word address has the same upper order address bits as the initial address transmitted to
avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words
addresses the protected area.
Write Enable (W) must be held High before and during the instruction. Input address and
data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or
M93S66-125 M93S56-125 M93S46-125 Instructions
Doc ID 022567 Rev 1 13/28
after this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed.
While the M93Sx6-125 is performing a write cycle, but after a delay (tSLSH) before the status
information becomes available, Chip Select Input (S) can be driven High to monitor the
status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6-125 is still
busy, and High when the cycle is complete, and the M93Sx6-125 is ready to receive a new
instruction. The M93Sx6-125 ignores any data on the bus while it is busy on a write cycle.
Once the M93Sx6-125 is Ready, Serial Data Output (Q) is driven High, and remains in this
state until a new start bit is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected
or left running after the start of a write cycle.
3.5 Write All
The Write All Memory with same Data (WRAL) instruction is valid only after the Protection
Register has been cleared by executing a Protection Register Clear (PRCLEAR) instruction.
The Write All Memory with same Data (WRAL) instruction simultaneously writes the whole
memory with the same data word given in the instruction.
Write Enable (W) must be held High before and during the instruction. Input address and
data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or
after this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed.
While the M93Sx6-125 is performing a write cycle, but after a delay (tSLSH) before the status
information becomes available, Chip Select Input (S) can be driven High to monitor the
status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6-125 is still
busy, and High when the cycle is complete, and the M93Sx6-125 is ready to receive a new
instruction. The M93Sx6-125 ignores any data on the bus while it is busy on a write cycle.
Once the M93Sx6-125 is Ready, Serial Data Output (Q) is driven High, and remains in this
state until a new start bit is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected
or left running after the start of a write cycle.
Instructions M93S66-125 M93S56-125 M93S46-125
14/28 Doc ID 022567 Rev 1
