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M74HCT374M1R-M74HCT374RM13TR
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT (NON INVERTING)
1/11July 2001 HIGH SPEED:
fMAX = 50 MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS : IH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
DESCRIPTIONThe M74HCT374 is an high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
NON INVERTING fabricated with silicon gate2 MOS technology.
This 8 bit D-TYPE FLIP FLOP is controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is at high level the outputs will
be in a high impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
The M74HCT374 is designed to directly interface
HSC2 MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT374OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT3742/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X: Don’t Care
Z: High Impedance
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HCT3743/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HCT3744/11
DC SPECIFICATION
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
M74HCT3745/11
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip
Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 30 + 18 x n (pF)
TEST CIRCUIT CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
M74HCT3746/11
WAVEFORM 1: CK TO Qn PROPAGATION DELAYS, MAXIMUM CK FREQUENCY, Dn TO CK
SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
