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M74HCT10B1R-M74HCT10M1R
TRIPLE 3-INPUT NAND GATE
1/8August 2001 HIGH SPEED:
tPD = 14ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:CC = 1μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS : IH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 10
DESCRIPTIONThe M74HCT10 is an high speed CMOS TRIPLE
3-INPUT NAND GATE fabricated with silicon gate2 MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
The M74HCT10 is designed to directly interface
HSC2 MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT10TRIPLE 3-INPUT NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT102/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don‘t Care
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HCT103/8
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/3 (per gate)
M74HCT104/8
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
