M74HC4017RM13TR ,DECADE COUNTER/DIVIDERlogic diagram has not be used to estimate propagation delays2/12M74HC4017TIMING DIAGRAM
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M74HC4017B1R-M74HC4017M1R-M74HC4017RM13TR
DECADE COUNTER/DIVIDER
1/12August 2001 HIGH SPEED :
tPD = 21 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION:CC =4μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4017
DESCRIPTIONThe M74HC4017 is an high speed CMOS
DECADE COUNTER/DIVIDER fabricated with
silicon gate C2 MOS technology.
The M74HC4017 is a 5-stage Johnson counter
with 10 decoded outputs. Each of the decoded
outputs is normally low and sequentially goes high
on the low to high transition of the clock input.
Each output stays high for one clock period of the
10 clock period cycle. The CARRY output goes
low to high after OUTPUT 10 goes low, and can
be used in conjunction with the CLOCK ENABLE
(CKEN)to cascade several stages.
The CLOCK ENABLE input disables counting
when in the high state. A CLEAR (CLR) input is
also provided which when taken high sets all the
decoded outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC4017DECADE COUNTER/DIVIDER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC40172/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Qn : No Change
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HC40173/12
TIMING DIAGRAM
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC40174/12
DC SPECIFICATIONS
M74HC40175/12
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
M74HC40176/12
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
