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M74HC40103RM13TR
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
1/16September 2001 HIGH SPEED :
fMAX = 38MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC =4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 40103
DESCRIPTIONThe M74HC40103 is an high speed CMOS
8-STAGE PRESETTABLE SYNCHRONOUS
DOWN COUNTER fabricated with silicon gate2 MOS technology.
The HC40103 consists of an 8 stage synchronous
down counter with a single output which is active
when the internal count is zero. The HC40103
contains a single 8-bit binary counter. This device
has control inputs for enabling or disabling the
clock, for clearing the counter to its maximum
count, and for presetting the counter either
synchronously or asynchronously. All control
inputs and the CARRY-OUT / ZERO DETECT
output are active low logic. In normal operation the
counter is decremented by one count on each
positive transition of the CLOCK. Counting is
inhibited when the CARRY-IN / COUNTER
ENABLE (CI/CE) input is high. The CARRY-OUT /
ZERO-DETECT (CO/ZD) output goes low when
the count reaches zero if the CI/CE input is low,
and remains low for one full clock period. When
the SYNCHRONOUS PRESET-ENABLE (SPE)
input is low, data at the J input is clocked into the
counter on the next positive clock transition
regardless of the state of the CI/CE input.
When the ASYNCHRONOUS PRESET-ENABLE
(APE) input is low, data at the J inputs is
asynchronously forced into the counter regardless
of the state of the SPE CI/CE or CLOCK inputs. J
input J0-J7 represent a singular 8-bit binary word.
When the CLEAR, CLR input is low, the counter is
asynchronously cleared to its maximum count
M74HC401038 STAGE PRESETTABLE
SYNCHRONOUS DOWN COUNTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC401032/16
(25510 ) regardless of the state of any other input.
The precedence relationship between control
input is indicated in the truth table. If all control
inputs are high at the time of zero count, the
counters will jump to the maximum count giving a
INPUT AND OUTPUT EQUIVALENT CIRCUIT counting sequence of 256 clock pulses long. The
HC40103 may be cascaded using the CI/CE input
and the CO/ZD output, in either a synchronous or
ripple mode. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.
PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Maximum Count is "255"
M74HC401033/16
LOGIC DIAGRAM
TIMING CHART
M74HC401034/16
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC401035/16
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
M74HC401036/16
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
M74HC401037/16
FUNCTIONAL DESCRIPTIONThis device is an 8-stage presettable synchronous
down counter. Carry Out/Zero Detect (CO/ZD) is
output at the "L" level for the period of 1 bit when
the readout becomes "0". This device adopts
8-bit-binary counter decimal notation, making
setting up to 255 counts possible.
COUNT OPERATION
At the "H" level of control input of CLEAR, SPE
and APE, the counter carriers out down count
operation one by one at the rise of pulse given to
CLOCK input. Count operation can be inhibited by
setting Carry Input/Clock Enable CI/CE to the "H"
level.
CO/ZD is output at the "L" level when the readout
becomes "0" but is not output even if the readout
becomes "0" when CI/CE is at the "H" level, thus
maintaining the "H" level.
Synchronous cascade operation can be carried
out by using CI/CE input and CO/ZD output.
The contents of count jump to maximum count
(255) if clock is given when the readout is "0".
Therefore, operation of 256-frequency division is
carried out when clock input alone is given without
various kinds of preset operation.
PRESET AND RESET OPERATION
When Clear (CLEAR) input is set to the "L" level,
the readout is set to the maximum count
independently of other inputs. When
Asynchronous Preset Enable (APE) input is set to
the "L" level, readouts given on J0 to J7 can be
preset asynchronously to the counter
independently of inputs other than CLEAR input.
When Synchronous Preset Enable (SPE) is set to
the "L" level the readouts given on J0 to J7 can be
preset to counter synchronously with the rise of
clock. As to these operation mode, refer to the
truth table.
M74HC401038/16
TYPICAL APPLICATIONS
PROGRAMMABLE DIVIDE-BY-N COUNTER
PARALLEL CARRY CASCADING
PROGRAMMABLE TIMER
