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M74HC373RM13T
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING
M54/74HC373 4/7 4HC533HC373 NON INVERTING- HC533 INVERTING
OCTAL D-TYPE LATCH WITH3 STATE OUTPUT
B1R(Plastic Package)
ORDER CODES:M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
F1R(CeramicPackage)
M1R(MicroPackage)
C1R(Chip Carrier)
PIN CONNECTION (top view) HIGH SPEED
tPD=11ns (TYP.) AT VCC =5V. LOWPOWER DISSIPATION
ICC =4 μA (MAX.) ATTA =25°C. HIGH NOISE IMMUNITY
VNIH =VNIL =28% VCC (MIN.). OUTPUT DRIVE CAPABILITY LSTTL LOADS. SYMMETRICAL OUTPUT IMPEDANCE
IOL= IOH=6 mA (MIN.). BALANCEDPROPAGATION DELAYS
tPLH =tPHL. WIDE OPERATING VOLTAGE RANGE
VCC (OPR)=2V TO6V. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS373/533
DESCRIPTIONThe M54/74HC373/533 are high speed CMOS
OCTAL LATCH WITH 3-STATE OUTPUTS
fabricated within silicon gateC2 MOS technology.
These ICs achive the high speed operation similar equivalent LSTTL while maintaning the CMOS
low power dissipation.
These8bit D-Type latches are controlledbya latch
enable input (LE) anda output enable input (OE).
While the LE inputis heldata high level, theQ
outputs will follow the data input precisely or
inversely. When the LEis taken low, theQ outputs
willbe latched preciselyor inverselyat the logiclevelD input data. While the OE inputisat low level,
the eight outputs willbeina normal logic state (high low logic level) and while high level the outpts willina high impedance state.
The application designer has a choise of
combinationof inverting and non inverting outputs.
The three state output configuration and the wide
choise of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against discharge and transient excess voltage.
HC373 HC533 HC373 HC533
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION (HC373)
PIN No SYMBOL NAME AND FUNCTION OE 3 State output Enable
Input (Active LOW)5,6,9,
12,15, 16,toQ7 3 State outputs4,7,8,
13,14, 17,toD7 Data Inputs LE Latch Enable Input GND Ground (0V) VCC Positive Supply Voltage
PIN DESCRIPTION (HC533)
PIN No SYMBOL NAME AND FUNCTION OE 3 State output Enable
Input (Active LOW)5,6,9,
12, 15, 16,toQ7 3 State outputs4,7,8,
13, 14, 17,toD7 Data Inputs LE Latch Enable Input GND Ground (0V) VCC Positive Supply Voltage
IEC LOGIC SYMBOLS
HC373 HC533
M54/M74HC373/533
TRUTH TABLE
INPUTS OUTPUTS LE D Q (HC373) Q (HC533) X Z Z L X NO CHANGE* NO CHANGE* L L H H H L DON’T CARE HIGH IMPEDANCE Q/QOUTPUTSARELATCHEDAT THE TIMEWHENTHELE INPUTISTAKEN LOW LOGIC LEVEL.
LOGIC DIAGRAMS
HC373
HC533
M54/M74HC373/533
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage -0.5to+7 V DC Input Voltage -0.5to VCC+ 0.5 V DC Output Voltage -0.5to VCC+ 0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±20 mA DC Output Source Sink Current Per Output Pin ±35 mA
ICCor IGND DC VCCor Ground Current ±70 mA Power Dissipation 500(*) mW
Tstg Storage Temperature -65to +150 oC Lead Temperature (10 sec) 300 oC
Absolute Maximum Ratingsarethosevalues beyondwhichdamage tothe devicemayoccu r.Functionaloperationunder theseconditionsis notimplied.
(*)500 mW:≅65oC derate to300mWby 10mW/oC:65o Cto85oC
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value UnitVCC Supply Voltage 2to6 V Input Voltage 0to VCC V Output Voltage 0to VCC V
Top Operating Temperature:
M54HC Series
M74HC Series
-55to +125
-40to +85CC
tr,tf Input Rise and Fall Time VCC=2V 0to 1000 ns
VCC=4.5V 0to 500
VCC=6V 0to 400
M54/M74HC373/533
SPECIFICATIONSSymbol Parameter
Test Conditions Value
UnitVCC(V)
=25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.VIH High Level Input
Voltage
2.0 1.5 1.5 1.54.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Low Level Input
Voltage
2.0 0.5 0.5 0.54.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH High Level
Output Voltage
2.0 VI=
VIH
VIL
IO=-20μA
1.9 2.0 1.9 1.94.5 4.4 4.5 4.4 4.4
6.0 5.9 6.0 5.9 5.9
4.5 IO=-6.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-7.8 mA 5.68 5.8 5.63 5.60
VOL Low Level Output
Voltage
2.0 VI=
VIH
VIL
IO=20μA
0.0 0.1 0.1 0.14.5 0.0 0.1 0.1 0.1
6.0 0.0 0.1 0.1 0.1
4.5 IO= 6.0 mA 0.17 0.26 0.33 0.40
6.0 IO= 7.8 mA 0.18 0.26 0.33 0.40 Input Leakage
Current 6.0 VI =VCCor GND ±0.1 ±1 ±1 μA
IOZ 3 State Output
Off State Current
6.0 VI =VIHorVIL =VCCor GND
±0.5 ±5.0 ±10 μA
ICC Quiescent Supply
Current
6.0 VI =VCCor GND 4 40 80 μA
M54/M74HC373/533
ELECTRICAL CHARACTERISTICS (CL =50 pF, Inputtr =tf =6 ns)
Symbol Parameter
Test Conditions Value
UnitVCC(V)
(pF)
=25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.tTLH
tTHL
Output Transition
Time
2.0 60 75 904.5 7 121518
6.0 6 101315
tPLH
tPHL
Propagation
Delay Time
(LE,D-Q,Q)
2.0 125 155 1904.5 14 25 31 38
6.0 12 21 26 32
150 175 220 2654.5 19 35 44 53
6.0 16 30 37 45
tPZL
tPZH State Output
Enable Time
2.0 RL =1 KΩ 125 155 1904.5 13 25 31 38
6.0 11 21 26 32
150 RL =1 KΩ 175 220 2654.5 18 35 44 53
6.0 15 30 37 45
tPLZ
tPHZ State Output
Disable Time
2.0 RL =1 KΩ 125 155 1904.5 14 25 31 38
6.0 13 21 26 32
tW(H) Minimum Pulse
Width (LE)
2.0 75 95 1104.5 6 151922
6.0 6 131619 Minimum Set-up
Time
2.0 50 65 754.5 4 101315
6.0 3 9 11 13 Minimum Hold
Time
5554.5 5 5 5
6.0 5 5 5
CIN Input Capacitance 5 10 10 10 pF
COUT Out put
Capacitance pF
CPD(*) Power Dissipation
Capacitance pF
(*) CPDis definedasthe valueofthe IC’sinternalequivalent capac itance whichis calculated from theoperatingcurrent consumption without load.
(Referto TestCircuit). Average operting current canbe obtainedbythe followingequation. ICC(opr)=CPD•VCC•fIN +ICC/8(perFlip Flop) andthe
CPDwhennpcs ofFlip Flop operate,canbe gained byfollowing equation: CPD (TOTAL)=22+16xn[pF]
M54/M74HC373/533
SWITCHING CHARACTERISTICS TEST WAVEFORMtPLZ,tPZL
The 1KΩ load resistors shouldbe connected between
outputs and VCC line and the 50pF load capacitors
shouldbe connected between outputsand GND line.
All inputs except OE input shouldbe connectedto VCC
lineor GND line such that outputs willbein low logic
level while OE inputis held low.
tPHZ,tPZH
The 1KΩ load resistors and the 50pF load capacitors
shouldbe connected between each output and GND
line.
All inputs except OE input shouldbe connectedto VCC GND line such that output willbein high logic level
while OE inputis held low.
tPLH,tPHL,(D-Q,Q) tPLH,tPHL (LE-Q, Q), ts,th,tW
M54/M74HC373/533
