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M74HC174M1RSTN/a6000avaiHEX D-TYPE FLIP FLOP WITH CLEAR
M74HC174RM13TRSTN/a101avaiHEX D-TYPE FLIP FLOP WITH CLEAR


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M74HC174M1R-M74HC174RM13TR
HEX D-TYPE FLIP FLOP WITH CLEAR
1/11July 2001 HIGH SPEED :
fMAX = 66MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:CC =4μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
DESCRIPTION

The M74HC174 is an high speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C2 MOS technology.
Information signals applied to D inputs are
transferred to the Q output on the positive going
edge of the clock pulse. When the CLEAR input is
held low, the Q outputs are held low independently
of the other inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC174

HEX D-TYPE FLIP FLOP WITH CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC174
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE

X : Don’t Care
LOGIC DIAGRAM

This logic diagram has not to be used to estimate propagation delays
M74HC174
3/11
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC174
4/11
DC SPECIFICATIONS
M74HC174
5/11
AC ELECTRICAL CHARACTERISTICS (C
L = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/6 (per FLIP/
FLOP)
And the total CPD when N pcs of FLIP-FLOP operate can be gained by the following equation : CPD (total) = 38 + 15 x n
M74HC174
6/11
TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK), SETUP AND
HOLD TIME (nD TO CLOCK), CLOCK MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
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