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M74HC173M1RSTN/a2800avaiQUAD D-TYPE REGISTER (3-STATE)
M74HC173RM13TRSTN/a2800avaiQUAD D-TYPE REGISTER (3-STATE)


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M74HC173M1R-M74HC173RM13TR
QUAD D-TYPE REGISTER (3-STATE)
1/12July 2001 HIGH SPEED:
fMAX = 84MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL =6mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 173
DESCRIPTION

The M74HC173 is an high speed CMOS QUAD
D-TYPE REGISTER (3-STATE) fabricated with
silicon gate C2 MOS technology.
This device is composed of a four-bit register
including D-TYPE flip-flops and 3-state buffers.
The four flip-flops are controlled by a common
clock input (CLOCK) and a common reset input
(CLEAR). Signals applied to the data inputs (D1 -
D4) are stored at the respective flip-flops on the
positive going transition of the clock input, only
when both clock control inputs (G1 and G2) are
held low.
The reset feature is asynchronous and active
high. The stored data are provided on each output
only when both output control inputs (M and N) are
held low, otherwise the outputs go to the
high-impedance state.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC173

QUAD D-TYPE REGISTER (3 STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC173
2/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE

X : Don’t Care
Z : High Impedance
M74HC173
3/12
LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
M74HC173
4/12
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HC173
5/12
AC ELECTRICAL CHARACTERISTICS (C
L = 50 pF, Input tr = tf = 6ns)
M74HC173
6/12
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (Per
Circuit)
TEST CIRCUIT

CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
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