M68Z128 ,5V, 1 Mbit (128Kb x8) Low Power SRAM with Output EnableAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....4DC AND AC ..
M68Z128-55N1 ,5V / 1 Mbit 128Kb x8 Low Power SRAM with Output EnableAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
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M68Z128
5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
1/17May 2002
M68Z1285V,1 Mbit (128 Kbitx 8) Low Power SRAM with Output Enable
FEATURES SUMMARY ULTRA LOW DATA RETENTION CURRENT
–10nA (typical)
–2.0μA (max) OPERATION VOLTAGE: 5.0V± 10% 128 Kbitx8 VERY FAST SRAM WITH
OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW VCC DATA RETENTION: 2.0V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER AUTOMATIC POWER-DOWN WHEN
DESELECTED INTENDED FOR USE WITH ST
ZEROPOWER® AND TIMEKEEPER®
CONTROLLERS
M68Z1282/17
TABLE OF CONTENTS
DESCRIPTION ...... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....3Logic Diagram (Figure 2.). ...... ....... ...... ....... ...... ....... ...... ...... .....3
Signal Names (Table1.).. ...... ....... ...... ....... ...... ....... ...... ...... .....3
TSOP Connections (Figure 3.)... ....... ...... ....... ...... ....... ...... ...... .....3
Block Diagram (Figure4.). ...... ....... ...... ....... ...... ....... ...... ...... .....4
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....4Absolute Maximum Ratings (Table2.) .... ...... ....... ...... ....... ...... ...... .....4
AND AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... .....5 and AC Measurement Conditions (Table3.)... ....... ...... ....... ...... ...... .....5 Testing Load Circuit (Figure 5.)....... ...... ....... ...... ....... ...... ...... .....5
Capacitance (Table4.)... ...... ....... ...... ....... ...... ....... ...... ...... .....5 Characteristics (Table5.) .... ....... ...... ....... ...... ....... ...... ...... .....6
OPERATION. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....7Operating Modes (Table 6.)...... ....... ...... ....... ...... ....... ...... ...... .....7
READ Mode...... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....7
Address Controlled, READ Mode AC Waveforms (Figure6.) ...... ....... ...... ...... .....7
Chip Enableor Output Enable Controlled, READ Mode AC Waveforms (Figure 7.).. ...... .....8
Standby Mode AC Waveforms (Figure 8.).. ...... ....... ...... ....... ...... ...... .....8
READ and Standby Mode AC Characteristics (Table 7.) ... ...... ....... ...... ...... .....9
WRITEMode ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
WRITE Enable Controlled, WRITE Mode AC Waveforms (Figure9.) ....... ...... ...... ....10
Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 10.). ....... ...... ...... ....11
WRITEMode AC Characteristics (Table8.) ...... ....... ...... ....... ...... ...... ....12
Low VCC Data Retention AC Waveforms (Figure 11.)...... ...... ....... ...... ...... ....13
Low VCC Data Retention Characteristics (Table 9.) ....... ...... ....... ...... ...... ....13
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....14
PACKAGE MECHANICAL INFORMATION... ...... ....... ...... ....... ...... ...... ....15
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
3/17
M68Z128
DESCRIPTIONThe M68Z128isa1 Mbit (1,048,576 bit) CMOS
SRAM, organizedas 131,072 wordsby8 bits. The
device features fully static operation requiring no
external clocksor timing strobes, with equal ad-
dress access and cycle times.It requiresa single ±10% supply, andall inputs and outputs are
TTL compatible.
This device hasan automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68Z128is availablein TSOP32(8x 20mm)
package.
Table1. Signal Names
Figure3. TSOP Connections
M68Z1284/17
Figure4. Block Diagram
MAXIMUM RATINGStressing the deviceabove therating listedinthe
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operationof the deviceat
theseor any other conditions above those indicat-in the Operating sectionsof this specificationis
not implied. Exposureto Absolute Maximum Rat-
ing conditionsfor extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table2. Absolute Maximum RatingsNote:1. Reflow atpeak temperatureof 215°Cto 225°Cfor<60 seconds (total thermal budgetnotto exceed 180°Cfor between 90and120
seconds).Uptoa maximum operating VCCof 5.5V only. One outputata time,notto exceed1 second duration.
5/17
M68Z128 AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristicsof the device. The parametersin
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listedin the relevant tables. De-
signers should check that the operating conditions their projects match the measurement condi-
tions when using the quoted parameters.
Table3. DC and AC Measurement ConditionsNote: Output HighZis definedasthe point where dataisno longer driven (see Table3, page5).
Table4. CapacitanceNote:1. Sampled only,not 100% tested. Outputs deselected.At 25°C.
M68Z1286/17
Table5. DC CharacteristicsNote:1. Validfor Ambient Operating Temperature:TA =0to 70°C; VCC=4.5to 5.5V (except where noted). AverageAC current, Outputs open, cyclingat tAVAV minimum.All other InputsatVIL≤ 0.8Vor VIH≥ 2.2V.All other InputsatVIL≤ 0.3Vor VIH≥ VCC –0.3V.
7/17
M68Z128
OPERATIONThe M68Z128 hasa Chip Enable power down fea-
ture which invokes an automatic standby mode
whenever either Chip Enableis de-asserted (E1=
Highor E2= Low). An Output Enable (G)signal
providesa high speed tri-state control, allowing
fast READ/WRITE cyclestobe achieved with the
common I/O data bus. Operational modes are de-
termined by device control inputs W,E1, and E2 summarizedin the Operating Modes table.
Table6. Operating ModesNote:X=VIHorVIL.
READ ModeThe M68Z128isin the READ Mode whenever
WRITE Enable (W)is High with Output Enable (G)
Low, and both Chip Enables (E1 and E2) are as-
serted. This provides accessto data from eightof
the 1,048,576 locationsin the static memory array,
specifiedby the 17 address inputs. Valid data will availableat the eight output pins within tAVQV
after the last stable address, providingGis Low,is Low and E2is High.If Chip Enableor Output
Enable access times are not met, data access will measured from the limiting parameter (tE1LQV,
tE2HQV,or tGLQV) rather than the address. Data out
maybe indeterminateat tE1LQX,tE2HQX and tGLQX,
but data lines will alwaysbe validat tAVQV.
Figure6. Address Controlled, READ Mode AC WaveformsNote:E1= Low,E2= High,+G =Low,W =High.
M68Z1288/17
9/17
M68Z128
Table7. READ and Standby Mode AC CharacteristicsNote:1. Validfor Ambient Operating Temperature:TA =0to 70°C; VCC=4.5to 5.5V (except where noted).CL= 100pF.CL= 5pF.At any given temperature and voltage condition, tEIHQZ +tEZHQZis less than tEILQX and tEZLQX,tGHQZis less than tGLQXforany
given device.
