M68AW127 ,1Mbit 128K x8 / 3.0V Asynchronous SRAMAbsolute Maximum Ratings . 5DC AND AC PARAMETERS . . 6Table 3. Operating and AC Measurem ..
M68AW127BM70MC6T ,1 MBIT (128K X8), 3.0V ASYNCHRONOUS SRAMfeatures fully static operation requiring no when deselected.external clocks or timing strobes, wit ..
M68AW127BM70MC6U ,1 MBIT (128K X8), 3.0V ASYNCHRONOUS SRAMAbsolute Maximum Ratings 8DC AND AC PARAMETERS . . 9Table 4. Operating and AC Measuremen ..
M68AW127BM70N6 ,1 MBIT (128K X8), 3.0V ASYNCHRONOUS SRAMFEATURES SUMMARY■ SUPPLY VOLTAGE: 2.7 to 3.6V Figure 1. Packages■ 128K x 8 bits SRAM with OUTPUT EN ..
M68AW127BM70NK6 ,1 MBIT (128K X8), 3.0V ASYNCHRONOUS SRAMBlock Diagram . . 6OPERATION . . . . . . 7Read Mode . . . . 7Write Mode ..
M68AW127BM70NK6T ,1Mbit 128K x8, 3.0V Asynchronous SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SO Connections . 5Figur ..
MAX1092AEEG ,400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel InterfaceApplications D6 3 22 REFD5 4 21 REFADJIndustrial Control Systems Data LoggingD4 5 20 GNDEnergy Mana ..
MAX1092BCEG ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel Interfaceapplications or for other circuits withdemanding power consumption and space require- Pin Configura ..
MAX1092BEEG ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor at ..
MAX1092BEEG+ ,400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor at ..
MAX1093ACEG ,250ksps / +3V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = V = +2.7V to +3.6V, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacit ..
MAX1093BCEG ,250ksps / +3V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 20 GNDIndustrial Control Systems Data LoggingMAX1093D3 6 19 COMEnergy Management P ..
M68AW127
1Mbit 128K x8 / 3.0V Asynchronous SRAM
1/20August 2003
M68AW127B1Mbit (128K x8), 3.0V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.6V 128K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
M68AW127B2/20
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 8. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . .9
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 11. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 12. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . .14
Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . .15
TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline. . . . . . . . . . . . . . . . . . . . . . . .16
TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data . . . . . . . . . . . . . . . .16
TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline . . . . . . . . . . . . . . . . . . . . . .17
TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data . . . . . . . . . . . . . .17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3/20
M68AW127B
SUMMARY DESCRIPTIONThe M68AW127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
2.7 to 3.6V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AW127B is available in SO32, TSOP32
8x20mm and TSOP32 8x13.4mm packages.
Table 1. Signal Names
M68AW127B
4/20
5/20
M68AW127B
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Note:1. One output at a time, not to exceed 1 second duration. Up to a maximum operating VCC of 3.6V only.
M68AW127B
6/20
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
7/20
M68AW127B
Table 4. Capacitance
Note:1. Sampled only, not 100% tested. At TA = 25°C, f = 1MHz, VCC = 3.0V.
Table 5. DC Characteristics
Note:1. Average AC current, cycling at tAVAV minimum. E1 = VIL, E2 = VIH, VIN = VIH or VIL. E1 ≤ 0.2V or E2 ≥ VCC –0.2V, VIN ≤ 0.2V or VIN ≥ VCC –0.2V. Output disabled.
M68AW127B
8/20
OPERATION
The M68AW127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 6).
Table 6. Operating Modes
Note: X = VIH or VIL.
Read Mode
The M68AW127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within tAVQV after the last stable address, provid-
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(tELQV or tGLQV) rather than the address. Data out
may be indeterminate at tELQX and tGLQX, but data
lines will always be valid at tAVQV.
9/20
M68AW127B
Note: Write Enable (W) = High.
M68AW127B
10/20
Table 7. Read and Standby Mode AC Characteristics
Note:1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than tELQX for any given device. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels. Tested initially and after any design or process changes that may affect these parameters.
