M59PW1282-100M1 ,128Mbit (two 64Mb, x16, Uniform Block, LightFlash™)3V Supply, Multiple Memory ProductLogic Diagram . . 4Table 1. Signal Names . . . 4Figure 3. SO Connections . 5Ta ..
M5K4164AL-15 , 65 536 BIT DYNAMIC RAM
M5L2764K-2 , 65536-BIT (8192-WORD BY 8-BIT) ERASABLE AND ELECTRICALLT REPROGRAMMABLE ROM
M5L2764K-2 , 65536-BIT (8192-WORD BY 8-BIT) ERASABLE AND ELECTRICALLT REPROGRAMMABLE ROM
M5M27C202JK-10 , 2097152-BIT(131072-WORD BY 16-BIT) CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM
M5M27C202JK-12 , 2097152-BIT(131072-WORD BY 16-BIT) CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM
MA02303GJ-R7 ,2200-2600 MHz, RF power amplifier IC for 2.4 GHz ISM
MA100L , UART-to- USB Bridge Controller
MA10100 ,Small-signal deviceElectrical Characteristics T = 25°C ± 3°CaParameter Symbol Conditions Min Typ Max UnitReverse curr ..
MA10701 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..
MA10702 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..
MA10704 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..
M59PW1282-100M1
128Mbit (two 64Mb, x16, Uniform Block, LightFlash™)3V Supply, Multiple Memory Product
1/24November 2003
M59PW1282128Mbit (two 64Mb, x16, Uniform Block, LightFlash™)
3V Supply, Multiple Memory Product
FEATURES SUMMARY MASK-ROM PIN-OUT COMPATIBLE TWO 64 Mbit LightFlash™ MEMORIES
STACKED IN A SINGLE PACKAGE SUPPLY VOLTAGE
–VCC = 2.7 to 3.6V for Read
–VPP = 11.4 to 12.6V for Program and Erase ACCESS TIME
–90ns at VCC = 3.0 to 3.6V 100, 120ns at VCC = 2.7 to 3.6V PROGRAMMING TIME 9µs per Word typical Multiple Word Programming Option
(16s typical Chip Program) ERASE TIME 85s typical Chip Erase UNIFORM BLOCKS 64 blocks of 2 Mbits PROGRAM/ERASE CONTROLLER Embedded Word Program algorithms 10,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code : 88A8h
M59PW1282
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Address/Voltage Supply (A22/VPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Setup Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Program Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . .11
Figure 4. A22 Latch Procedure Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. A22 Latch Procedure AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 5. Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6. Chip Erase Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 7. Multiple Word Program Flowchart for 64Mbit Top and Bottom Die . . . . . . . . . . . . . . . . .13
3/24
M59PW1282
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Status Register Bit DQ1 is reserved.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 9. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 10. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 12. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 13. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 14. Chip Enable Controlled, Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 15. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data.21
Figure 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . .21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
M59PW1282
SUMMARY DESCRIPTIONThe M59PW1282 is a 128Mbit (8Mb x16), Mask-
ROM pinout compatible, non-volatile LightFlash™
memory, that can be read, erased and repro-
grammed. Read operations can be performed us-
ing a single low voltage (2.7 to 3.6V) supply.
Program and Erase operations require an addi-
tional VPP (11.4 to 12.6V) power supply. On pow-
er-up the memory defaults to its Read mode where
it can be read in the same way as a ROM or
EPROM.
The Mask-ROM compatibility is obtained using a
dual function Address/Voltage Supply pin (A22/
VPP). In Read mode the A22/VPP pin works as an
address pin; in Program or Erase mode it also
works as a voltage supply pin. At the beginning of
any program or erase operation, a specific proce-
dure (see Figure 4) must be performed to internal-
ly memorize the A22 value that will be used during
the program or erase operation.
The device is composed of two 64Mbit memories
stacked in a single package. Recommended oper-
ating conditions do not allow both memories to be
active at the same time. Address A22 selects the
memory to be enabled. The other memory is in
Standby mode.
The memory is divided into 64 uniform blocks that
can be erased independently so it is possible to
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller (P/E.C.) simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The M59PW1282 features an innovative com-
mand, Multiple Word Program, that is used to pro-
gram large streams of data. It greatly reduces the
total programming time when a large number of
Words are written to the memory at any one time.
Using this command the entire memory can be
programmed in 16s, compared to 72s using the
standard Word Program.
The end of a Program or Erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards. Chip Enable
and Output Enable signals control the bus opera-
tion of the memory. They allow simple connection
to most microprocessors, often without additional
logic.
The memory is offered in SO44 package and is
supplied with all the bits set to ’1’).
Table 1. Signal Names
5/24
M59PW1282
M59PW1282
Table 2. Block Addresses
7/24
M59PW1282
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Address/Voltage Supply (A22/VPP). The
A22/VPP signal has two functions.
During read operations the A22/VPP signal works
as an address input, which is used to select the
Top (A22 = VIH) or Bottom (A22 = VIL) die.
During program or erase operations it also works
as a VPP voltage supply pin. At the beginning of
any program or erase operation, a specific proce-
dure (see Figure 4) must be performed to internal-
ly memorize the A22 value that will be used during
the program or erase operation.
When the VPP is in the VHH range (see Table 12,
DC Characteristic, for the relevant values) pro-
gram and erase operations are enabled. During
such operations VPP must be stable in the VHH
range. Program and erase operation are not al-
lowed when VPP is below the VHH range.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the command
sent to the Command Interface of the Program/
Erase Controller. When reading the Status Regis-
ter they report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Interface does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write opera-
tions, when VPP is in the VHH range.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operations of the memory. It
also allows Bus Write operations, when VPP is in
the VHH range.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for Read operations.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program opera-
tions, ICC3.
Vss Ground. The VSS Ground is the reference
for all voltage measurements.
M59PW1282
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 3, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs and applying a Low signal, VIL, to Chip En-
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 12, Read AC
Waveforms, and Table 12, Read AC Characteris-
tics, for details of when the output becomes valid.
During read array operations A22 selects Top
(A22 = VIH) or Bottom (A22 = VIL) die.
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
when VPP is set to VHH. A valid Bus Write opera-
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure
12, Write AC Waveforms, and Table 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 12, DC Characteristics.
During program operation the memory will contin-
ue to use the Program Supply Current, ICC3, for
Program operation until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3, Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Table 3. Bus Operations
Note:1. X = VIL or VIH. When reading the Status Register during a program operation A22/VPP must be kept at VHH. VIL enables the Bottom die, VIH enables the Top die during read array operation. VHH after latching A22 at VIL or VIH.
9/24
M59PW1282
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 4 and 5, for a summary of the com-
mands.
As the device contains two internal memories care
must be taken to issue the commands to the cor-
rect address. To select the Top die (A22 = VIH) or
the Bottom die (A22 = VIL) the A22 latch procedure
(see Figure 4) must be followed.
It is not necessary to repeat the A22 latch proce-
dure if all the commands are issued to the same
die, unless the power supply VCC is switched off.
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
VPP must be set to VHH during the Read/Reset
command. If VPP is set to either VIL or VIH the com-
mand will be ignored. The command can be is-
sued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
Auto Select Command.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. VPP
must be set to VHH during the Auto Select com-
mand. If VPP is set to either VIL or VIH the com-
mand will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Se-
lect command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
Word Program Command.
The Word Program command can be used to pro-
gram a Word to the memory array. VPP must be
set to VHH during Word Program. If VPP is set to ei-
ther VIL or VIH the command will be ignored, the
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the P/E.C.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
once. VPP must be set to VHH during Multiple Word
Program. If VPP is set either VIL or VIH the com-
mand will be ignored, the data will remain un-
changed and the device will revert to Read mode.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the P/E.C. has started (see Table 8 and
Figure 8).
Program Phase. The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (re-
fer to Table 5, Multiple Word Program and Figure
7, Multiple Word Program Flowchart).
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the P/E.C. is ready to accept the op-
eration (see Table 8 and Figure 8).
The Program Phase is executed in three different
sub-phases: The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
M59PW1282
Start Address and the first Word to be
programmed. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A21 equal to the
Start Address), that indicates to the PC that the
Program Phase has to continue. A0 to A16 are
‘don’t care’. Finally, after all Words have been programmed,
a Bus Write operation (the (n+1)th ) with a Final
Address, FA (A17 or a higher address pin
different from the Start Address), ends the
Program Phase.
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the P/E.C. is ready for the next oper-
ation or if the reprogram of the location has failed
(see Table 8 and Figure 8).
Three successive steps are required to execute
the Verify Phase of the command: The first Bus Write operation of the Verify Phase
latches the Start Address and the Word to be
verified. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
but only a Continue Address, CA (A17 to A21
equal to the Start Address). Finally, after all Words have been verified, a Bus
Write cycle with a Final Address, FA (A17 or a
higher address pin different from the Start
Address) ends the Verify Phase.
Exit Phase. After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 8
and Figure 8).
If the Verify Phase accomplishes successfully, the
memory returns to the Read mode and DQ6 stops
toggling.
On the contrary, if the P/E.C. fails to reprogram a
given location, the Verify Phase terminates, DQ6
continues toggling and error bit DQ5 is set in the
Status Register. If the error is due to a VPP failure
DQ4 is also set.
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 6.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’.
Block Erase Command.
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost.
VPP must be set to VHH during Block Erase. If VPP
is set to either VIL or VIH the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode.
Six Bus Write operations are required to select the
block . The Block Erase operation starts the P/E.C.
after the last Bus Write operation. The Status Reg-
ister can be read after the sixth Bus Write opera-
tion. See the Status Register for details on how to
identify if the P/E.C. has started the Block Erase
operation.
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Chip Erase Command.
The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the mem-
ory to ’1’. All previous data in the memory is lost.
VPP must be set to VHH during Chip Erase. If VPP
is set to either VIL or VIH the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the P/E.C.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
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M59PW1282
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
Table 4. Standard Commands
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A21, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Note:1. TA = 25°C, VPP = 12V.
M59PW1282
