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M59MR032C120GC6TSTN/a275avai32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory


M59MR032C120GC6T ,32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash MemoryLogic Diagram– Parameter Blocks (Top or Bottom location) ■ DUAL BANK OPERATIONS– Read within one Ba ..
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M59MR032C120GC6T
32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
1/49April 2001
M59MR032C
M59MR032D

32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst)
1.8V Supply Flash Memory SUPPLY VOLTAGE
–VDD = VDDQ = 1.65V to 2.0V for Program,
Erase and Read
–VPP = 12V for fast Program (optional) MULTIPLEXED ADDRESS/DATA SYNCHRONOUS / ASYNCHRONOUS READ Configurable Burst mode Read Page mode Read (4 Words Page) Random Access: 100ns PROGRAMMING TIME 10μs by Word typical Double Word Programming Option MEMORY BLOCKS Dual Bank Memory Array: 8 Mbit - 24 Mbit Parameter Blocks (Top or Bottom location) DUAL BANK OPERATIONS Read within one Bank while Program or
Erase within the other No delay between Read and Write operations BLOCK PROTECTION/UNPROTECTION All Blocks protected at Power-up Any combination of Blocks can be protected COMMON FLASH INTERFACE (CFI) 64 bit SECURITY CODE ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M59MR032C: A4h Bottom Device Code, M59MR032D: A5h
Figure 1. Logic Diagram
M59MR032C, M59MR032D
Figure 2. LFBGA Connections (Top view through package)
3/49
M59MR032C, M59MR032D
Figure 3. μBGA Connections (Top view through package)
M59MR032C, M59MR032D
Table 1. Signal Names
DESCRIPTION

The M59MR032 is a 32 Mbit non-volatile Flash
memory that may be erased electrically at block
level and programmed in-system on a Word-by-
Word basis using a 1.65V to 2.0V VDD supply for
the circuitry. For Program and Erase operations
the necessary high voltages are generated inter-
nally. The device supports synchronous burst read
and asynchronous page mode read from all the
blocks of the memory array; at power-up the de-
vice is configured for page mode read. In synchro-
nous burst mode, a new data is output at each
clock cycle for frequencies up to 54MHz.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against pro-
gramming and erase at Power-up. Blocks can be
unprotected to make changes in the application
and then reprotected.
Instructions for Read/Reset, Auto Select, Write
Configuration Register, Programming, Block
Erase, Bank Erase, Erase Suspend, Erase Re-
sume, Block Protect, Block Unprotect, Block Lock-
ing, CFI Query, are written to the memory through
a Command Interface (C.I.) using standard micro-
processor write timings.
The memory is offered in LFBGA54 and μBGA46,
0.5 mm ball pitch packages and it is supplied with
all the bits erased (set to ’1’).
Table 2. Absolute Maximum Ratings (1)

Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Depends on range. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
5/49
M59MR032C, M59MR032D
Organization

The M59MR032 is organized as 2Mbit by 16 bits.
The first sixteen address lines are multiplexed with
the Data Input/Output signals on the multiplexed
address/data bus ADQ0-ADQ15. The remaining
address lines A16-A20 are the MSB addresses.
Memory control is provided by Chip Enable E, Out-
put Enable G and Write Enable W inputs.
The clock K input synchronizes the memory to the
microprocessor during burst read.
Reset RP is used to reset all the memory circuitry
and to set the chip in power-down mode if this
function is enabled by a proper setting of the Con-
figuration Register. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
ADQ7 provides a Data Polling signal, ADQ6 and
ADQ2 provide Toggle signals and ADQ5 provides
error bit to indicate the state of the P/E.C opera-
tions. WAIT output indicates to the microprocessor
the status of the memory during the burst mode
operations.
Memory Blocks

The device features asymmetrically blocked archi-
tecture. M59MR032 has an array of 71 blocks and
is divided into two banks A and B, providing Dual
Bank operations. While programming or erasing in
Bank A, read operations are possible into Bank B
or vice versa. The memory also features an erase
suspend allowing to read or program in another
block within the same bank. Once suspended the
erase can be resumed. The Bank Size and Sector-
ization are summarized in Table 8. Parameter
Blocks are located at the top of the memory ad-
dress space for the M59MR032C, and at the bot-
tom for the M59MR032D. The memory maps are
shown in Tables 4, 5, 6 and 7.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additional data
security. Instructions are provided to protect or un-
protect any block in the application. A second reg-
ister locks the protection status while WP is low
(see Block Locking description). All blocks are pro-
tected and unlocked at Power-up.
Table 3. Bank Size and Sectorization
M59MR032C, M59MR032D
Table 4. Bank A, Top Boot Block Addresses
M59MR032C
Table 5. Bank B, Top Boot Block Addresses
M59MR032C
7/49
M59MR032C, M59MR032D
Table 6. Bank B, Bottom Boot Block Addresses
M59MR032D
Table 7. Bank A, Bottom Boot Block Addresses
M59MR032D
M59MR032C, M59MR032D
SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.
Address Inputs or Data Input/Output (ADQ0-
ADQ15).
When Chip Enable E is at VIL and Out-
put Enable G is at VIH the multiplexed address/
data bus is used to input addresses for the memo-
ry array, data to be programmed in the memory ar-
ray or commands to be written to the C.I. The
address inputs for the memory array are latched
on the rising edge of Latch Enable L. The address
latch is transparent when L is at VIL. Both input
data and commands are latched on the rising edge
of Write Enable W. When Chip Enable E and Out-
put Enable G are at VIL the address/data bus out-
puts data from the Memory Array, the Electronic
Signature Manufacturer or Device codes, the
Block Protection status the Configuration Register
status or the Status Register Data Polling bit
ADQ7, the Toggle Bits ADQ6 and ADQ2, the Error
bit ADQ5. The address/data bus is high imped-
ance when the chip is deselected, Output Enable
G is at VIH, or RP is at VIL.
Address Inputs (A16-A20).
The five MSB ad-
dresses of the memory array are latched on the
rising edge of Latch Enable L.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at VIH deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at VIL.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is at VIH the outputs are High im-
pedance.
Write Enable (W).
This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP).
This input gives an addition-
al hardware protection level against program or
erase when pulled at VIL, as described in the Block
Lock instruction description.
Reset/Power-down Input (RP).
The RP input
provides hardware reset of the memory, and/or
Power-down functions, depending on the Configu-
ration Register status. Reset/Power-down of the
memory is achieved by pulling RP to VIL for at
least tPLPH. When the reset pulse is given, if the
memory is in Read, Erase Suspend Read or
Standby, it will output new valid data in tPHQ7V1 af-
ter the rising edge of RP. If the memory is in Erase
or Program modes, the operation will be aborted
and the reset recovery will take a maximum of
tPLQ7V. The memory will recover from Power-
down (when enabled) in tPHQ7V2 after the rising
edge of RP. Exit from Reset/Power-down changes
the contents of the configuration register bits 14
and 15, setting the memory in asynchronous page
mode read and power save function disabled. All
blocks are protected and unlocked after a Reset/
Power-down. See Tables 29, 31 and Figure 14.
Latch Enable (L).
L latches the address bits
ADQ0-ADQ15 and A16-A20 on its rising edge.
The address latch is transparent when L is at VIL
and it is inhibited when L is at VIH.
Clock (K).
The clock input synchronizes the
memory to the microcontroller during burst mode
read operation; the address is latched on a K edge
(rising or falling, according to the configuration set-
tings) when L is at VIL. K is don’t care during asyn-
chronous page mode read and in write operations.
Wait (WAIT).
WAIT is an output signal used dur-
ing burst mode read, indicating whether the data
on the output bus are valid or a wait state must be
inserted. This output is high impedance when E or
G are high or RP is at VIL, and can be configured
to be active during the wait cycle or one clock cy-
cle in advance.
9/49
M59MR032C, M59MR032D
Bus Invert (BINV).
BINV is an input/output signal
used to reduce the amount of power needed to
switch the external address/data bus. The power
saving is achieved by inverting the data output on
ADQ0-ADQ15 every time this gives an advantage
in terms of number of toggling bits. In burst mode
read, each new data output from the memory is
compared with the previous data. If the number of
transitions required on the data bus is in excess of
8, the data is inverted and the BINV signal will be
driven by the memory at VOH to inform the receiv-
ing system that data must be inverted before any
further processing. By doing so, the actual transi-
tions on the data bus will be less than 8. In a simi-
lar way, when a command is given, BINV may be
driven by the system at VIH to inform the memory
that the data must be inverted.Like the other input/
output pins, BINV is high impedance when the
chip is deselected, output enable G is at VIH or RP
is at VIL; when used as an input, BINV must follow
the same setup and hold timings of the data in-
puts.
VDD and VDDQ Supply Voltage (1.65V to 2.0V).

The main power supply for all operations (Read,
Program and Erase). VDD and VDDQ must be at
the same voltage.
VPP Program Supply Voltage (12V).
VPP is
both a control input and a power supply pin. The
two functions are selected by the voltage range
applied to the pin; if VPP is kept in a low voltage
range (0 to 2V) VPP is seen as a control input, and
the current absorption is limited to 5μA (0.2μA typ-
ical). In this case with VPP = VIL we obtain an ab-
solute protection against program or erase; with
VPP = VPP1 these functions are enabled. VPP val-
ue is only sampled during program or erase write
cycles; a change in its value after the operation
has been started does not have any effect and
program or erase are carried on regularly. If VPP is
used in the 11.4V to 12.6V range (VPP2) then the
pin acts as a power supply. This supply voltage
must remain stable as long as program or erase
are finished. In read mode the current sunk is less
then 0.5mA, while during program and erase oper-
ations the current may increase up to 10mA.
VSS Ground.
VSS is the reference for all the volt-
age measurements.
M59MR032C, M59MR032D
Table 8. User Bus Operations (1)

Note:1. X = Don’t care.
Table 9. Read Electronic Signature (AS and Read CFI instructions) (1)

Note:1. Addresses are latched on the rising edge of L input.
Table 10. Read Block Protection (AS and Read CFI instructions) (1)

Note:1. Addresses are latched on the rising edge of L input. A locked block can be unprotected only with WP at VIH.
DEVICE OPERATIONS

The following operations can be performed using
the appropriate bus cycles: Address Latch, Read
Array (Random, and Page Modes), Write com-
mand, Output Disable, Standby, Reset/Power-
down and Block Locking. See Table 8.
Address Latch.
In asynchronous operation, the
address is latched on the rising edge of L input; in
burst mode, the address is latched either by L go-
ing high or with a rising/falling edge of K, depend-
ing on the clock configuration.
Read.
Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status, the Configuration Register sta-
tus and the Security Code.
Read operation of the Memory Array may be per-
formed in asynchronous page mode or synchro-
nous burst mode. In asynchronous page mode
data is internally read and stored in a page buffer.
The page has a size of 4 words and is addressed
by ADQ0 and ADQ1 address inputs.
According to the device configuration the following
Read operations: Electronic Signature - Status
Register - CFI - Block Protection Status - Configu-
ration Register Status - Security Code must be ac-
cessed as asynchronous read or as single
synchronous burst mode (see Figure 4). Both Chip
Enable E and Output Enable G must be at VIL in
order to read the output of the memory.
11/49
M59MR032C, M59MR032D
Figure 4. Read Operation Sequence when CR15 = 0 (excluding Read Memory Array)
Burst Read.
The device also supports a burst
read. In this mode, an address is first latched on
the rising edge of L or K (or falling edge of K, ac-
cording to configuration settings); after a config-
urable delay of 2 to 6 clock cycles a new data is
output at each clock cycle. The burst sequence
may be configured for linear or interleaved order
and for a length of 4, 8 words or for continuous
burst mode.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur.
This delay will depend on the starting address of
the burst sequence; the worst case delay will oc-
cur when the sequence is crossing a 32 word
boundary and the starting address was at the end
of a four word boundary. See the Write Configura-
tion Register (CR) Instruction for more details on
all the possible settings for the synchronous burst
read.
Write.
Write operations are used to give Instruc-
tion Commands to the memory or to latch Input
Data to be programmed. A write operation is initi-
ated when Chip Enable E and Write Enable W are
at VIL with Output Enable G at VIH. Addresses are
latched on the rising edge of L. Commands and In-
put Data are latched on the rising edge of W or E
whichever occurs first. Noise pulses of less than
5ns typical on E, W and G signals do not start a
write cycle. Write operations are asynchronous
and clock is ignored during write.
Dual Bank Operations.
The Dual Bank allows to
read data from one bank of memory while a pro-
gram or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an ad-
dress within the bank being modified.
Output Disable.
The data outputs are high im-
pedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby.
The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The pow-
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Automatic Standby.
When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus. The automatic standby fea-
ture is not available when the device is configured
for synchronous burst mode.
Power-down.
The memory is in Power-down
when the Configuration Register is set for Power-
down and RP is at VIL. The power consumption is
reduced to the Power-down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Block Locking.
Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to VIL (see Block Lock instruction).
M59MR032C, M59MR032D
INSTRUCTIONS AND COMMANDS

Seventeen instructions are defined (see Table
17), and the internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits can be read at any time, dur-
ing programming or erase, to monitor the progress
of the operation.
Instructions, made up of one or more commands
written in cycles, can be given to the Program/
Erase Controller through a Command Interface
(C.I.). The C.I. latches commands written to the
memory. Commands are made of address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followed by an input
command or a confirmation command. The Coded
Sequence consists of writing the data AAh at the
address 555h during the first cycle and the data
55h at the address 2AAh during the second cycle.
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all in-
structions (see Table 17). The third cycle inputs
the instruction set-up command. Subsequent cy-
cles output the addressed data, Electronic Signa-
ture, Block Protection, Configuration Register
Status or CFI Query for Read operations. In order
to give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. For a Program instruction, the
fourth command cycle inputs the address and data
to be programmed. For a Double Word Program-
ming instruction, the fourth and fifth command cy-
cles input the address and data to be
programmed. For a Block Erase and Bank Erase
instructions, the fourth and fifth cycles input a fur-
ther Coded Sequence before the Erase confirm
command on the sixth cycle. Any combination of
blocks of the same memory bank can be erased.
Erasure of a memory block may be suspended, in
order to read data from another block or to pro-
gram data in another block, and then resumed.
When power is first applied the command interface
is reset to Read Array.
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to ensure maximum
data security.
Read/Reset (RD) Instruction.
The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded Cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. The Reset command does
not affect the configuration of unprotected blocks
and the Configuration Register status. Read/Re-
set Instruction is ignored when program or erase is
in progress.
CFI Query (RCFI) Instruction.
Common Flash
Interface Query mode is entered writing 98h at ad-
dress 55h. The CFI data structure gives informa-
tion on the device, such as the sectorization, the
command set and some electrical specifications.
Tables 19, 20, 21 and 22 show the addresses
used to retrieve each data. The CFI data structure
contains also a security area; in this section, a 64
bit unique security number, organized by word, is
written starting at address 81h. This area can be
accessed only in read mode by the final user and
there are no ways of changing the code after it has
been written by ST. Write a read instruction (RD)
to return to Read Array mode.
Table 11. Commands
13/49
M59MR032C, M59MR032D
Auto Select (AS) Instruction.
This instruc-
tion uses two Coded Cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the Manufacturer or the Device Code (Electronic
Signature), the Block Protection status or the Con-
figuration Register status depending on the levels
of ADQ0 and ADQ1 (see Tables 9, 10 and 11).
The Electronic Signature can be read from the
memory allowing programming equipment or ap-
plications to automatically match their interface to
the characteristics of M59MR032. The Manufac-
turer Code is output when the address lines ADQ0
and ADQ1 are at VIL, the Device Code is output
when ADQ0 is at VIH with ADQ1 at VIL.
The codes are output on ADQ0-ADQ7 with ADQ8-
ADQ15 at 00h. The AS instruction also allows the
access to the Block Protection Status. After giving
the AS instruction, ADQ0 is set to VIL with ADQ1
at VIH, while A12-A20 define the address of the
block to be verified (see Table 10). The AS Instruc-
tion finally allows the access to the Configuration
Register status if both ADQ0 and ADQ1 are set to
VIH; refer to Table 12 for configuration register de-
scription.
A reset command puts the device in Read Array
mode.
Write Configuration Register (CR) Instruc-
tion.
This instruction uses two Coded Cycles fol-
lowed by one write cycle giving the command 60h
to address 555h. A further write cycle giving the
command 03h writes the contents of address bits
ADQ0-ADQ15 to bits CR15-CR0 of the configura-
tion register. At Power-up the Configuration Reg-
ister is set to asynchronous Read mode, Power-
down disabled and bus invert (power save func-
tion) disabled.
A description of the effects of each configuration
bit is given in Table 12.
Table 12. Read Configuration Register (AS and Read CFI instructions)
M59MR032C, M59MR032D
Table 13. X-Latency Configuration

Note:1. Configuration codes 5 and 6 may be used only in conjunction with configuration bit CR9 set at “1” (one data every 2 clock cycles).
Figure 5. X-Latency Configuration Sequence Read mode (CR15).
The device supports an
asynchronous page mode and a synchronous
burst mode. In asynchronous page mode, the
default at power-up, data is internally read and
stored in a buffer of 4 words selected by ADQ0
and ADQ1 address inputs. In synchronous burst
mode, the device latches the starting address
and then outputs a sequence of data which de-
pends on the configuration register settings. Bus Invert configuration (CR14). This regis-
ter bit is used to enable the BINV pin functional-
ity. BINV functionality depends upon
configuration bits CR14 and CR15 (see Table
12 for configuration bits definition) as shown in
Table 14.
As output pin BINV is active only when enabled
(CR14 = 1) in Read Array burst mode (CR15 = 0).
As input pin BINV is active only when enabled
(CR14 = 1). BINV is ignored when ADQ0-
ADQ15 lines are used as address inputs (ad-
dresses must not be inverted).
Table 14. BINV Configuration Bits
15/49
M59MR032C, M59MR032D X-Latency (CR13-CR11).
These configuration
bits define the number of clock cycles elapsing
from L going low to valid data available in burst
mode. The correspondence between X-Latency
settings and the sustainable clock frequencies
is given in Table 13 and Figure 5. Power-down configuration (CR10). The RP
pin may be configured to give a very low power
consumption when driven low (power-down
state). In power-down the ICC supply current is
reduced to a typical figure of 2μA; if this function
is disabled (default at power-up) the RP pin
causes only a reset of the device and the supply
current is the stand-by value. The recovery time
after a RP pulse is significantly longer (50μs vs.
150ns) when power-down is enabled. Data hold configuration (CR9). In burst
mode this register bit determines if a new data
is output at each clock cycle or every 2 clock cy-
cles. Wait configuration (CR8). In burst mode
WAIT indicates whether the data on the output
bus are valid or a wait state must be inserted.
The configuration bit determines if WAIT will be
asserted one clock cycle before the wait state or
during the wait state (see Figure 10). Burst order configuration (CR7). See Table
15 for burst order and length. Clock configuration (CR6). In burst mode de-
termines if address is latched and data is output
on the rising or falling edge of the clock. Burst length (CR2-CR0). In burst mode deter-
mines the number of words output by the mem-
ory. It is possible to have 4 words, 8 words or a
Table 15. Burst Order and Length Configuration

continuous burst mode, in which all the words in
bank A or bank B are read sequentially. In con-
tinuous burst mode the burst sequence is inter-
rupted at the end of each of the two banks or
when a suspended block is reached. In continu-
ous burst mode it may happen that the memory
will stop the data output flow for a few clock cy-
cles; this event is signaled by WAIT going low
until the output flow is resumed. The initial ad-
dress determines if the output delay will occur
as well as its duration. If the starting address is
aligned to a four word boundary no wait states
will be needed. If the starting address is shifted
by 1,2 or 3 positions from the four word bound-
ary, WAIT will be asserted for 1,2 or 3 clock cy-
cles (2,4, 6 cycles if CR9 is set at “1”) when the
burst sequence is crossing the first 32 word
boundary. WAIT will be asserted only once dur-
ing a continuous burst access. See also Table
Enter Bypass Mode (EBY) Instruction. This in-
struction uses the two Coded cycles followed by
one write cycle giving the command 20h to ad-
dress 555h for mode set-up. Once in Bypass
mode, the device will accept the Exit Bypass
(XBY) and Program or Double Word Program in
Bypass mode (PGBY, DPGBY) commands. The
Bypass mode allows to reduce the overall pro-
gramming time when large memory arrays need to
be programmed.
Exit Bypass Mode (XBY) Instruction.
This in-
struction uses two write cycles. The first inputs to
the memory the command 90h and the second in-
puts the Exit Bypass mode confirm (00h). After the
XBY instruction, the device resets to Read Memo-
ry Array mode.
M59MR032C, M59MR032D
Program in Bypass Mode (PGBY) Instruc-
tion.
This instruction uses two write cycles. The
Program command A0h is written to any Address
on the first cycle and the second write cycle latch-
es the Address on the rising edge of L and the
Data to be written on the rising edge of W and
starts the P/E.C. Read operations within the same
bank output the Status Register bits after the pro-
gramming has started. Memory programming is
made only by writing ’0’ in place of ’1’. The content
of the memory cell is not changed if the user write
’1’ in place of ’0’ and no error occurs. Status bits
ADQ6 and ADQ7 determine if programming is on-
going and ADQ5 allows verification of any possible
error.
Program (PG) Instruction.
This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write operation latches the
Address and the Data to be written and starts the
P/E.C. Read operations within the same bank out-
put the Status Register bits after the programming
has started. Memory programming is made only
by writing ’0’ in place of ’1’. The content of the
memory cell is not changed if the user write ’1’ in
place of ’0’ and no error occurs. Status bits ADQ6
and ADQ7 determine if programming is on-going
and ADQ5 allows verification of any possible error.
Programming at an address not in blocks being
erased is also possible during erase suspend.
Double Word Program (DPG) Instruction.
This
feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. High voltage (11.4V to 12.6V) on VPP
pin is required. This instruction uses five write cy-
cles. The double word program command 40h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write cycle latches the ad-
dress and data to be written to the first location. A
fifth write cycle latches the new data to be written
to the second location and starts the P/E.C.. Note
that the two locations must have the same address
except for the address bit A0. The Double Word
Program can be executed in Bypass mode (DPG-
BY) to skip the two coded cycles at the beginning
of each command.
Block Protect (BP), Block Unprotect (BU),
Block Lock (BL) Instructions.
All blocks are
protected and unlocked at power-up. Each block
of the array has two levels of protection against
program or erase operation. The first level is set by
the Block Protect instruction; a protected block
cannot be programmed or erased until a Block Un-
protect instruction is given for that block. A second
level of protection is set by the Block Lock instruc-
tion, and requires the use of the WP pin, according
to the following scheme: when WP is at VIH, the Lock status is overridden
and all blocks can be protected or unprotected; when WP is at VIL, Lock status is enabled; the
locked blocks are protected, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status, and pro-
gram or erase accordingly;
Table 16. Protection States (1)

Note:1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by
ADQ1 (= 1 for a locked block) and ADQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
its logic value. A WP transition to VIH on a locked block will restore the previous ADQ0 value, giving a 111 or 110.
17/49
M59MR032C, M59MR032D
the lock status is cleared for all blocks at power-
up or pulling RP at VIL for at least tPLPH. The
protection and lock status can be monitored for
each block using the Autoselect (AS) instruc-
tion. Protected blocks will output a ‘1’ on ADQ0
and locked blocks will output a ‘1’ on ADQ1.
After a pulse of RP of at least tPLPH all blocks are
protected and unlocked.
Refer to Table 16 for a list of the protection states.
Block Erase (BE) Instruction.
This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles and an address within the block to be
erased is given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. All blocks must belong to the same
bank of memory; if a new block belonging to the
other bank is given, the operation is aborted. The
erase will start after an erase timeout period of
100μs. Thus, additional Erase Confirm commands
for other blocks must be given within this delay.
The input of a new Erase Confirm command will
restart the timeout period. The status of the inter-
nal timer can be monitored through the level of
ADQ3, if ADQ3 is '0' the Block Erase Command
has been given and the timeout is running, if
ADQ3 is '1', the timeout has expired and the P/
E.C. is erasing the Block(s). If the second com-
mand given is not an erase confirm or if the Coded
cycles are wrong, the instruction aborts, and the
device is reset to Read Array. It is not necessary
to program the block with 00h as the P/E.C. will do
this automatically before erasing to FFh. Read op-
erations within the same bank, after the sixth rising
edge of W or E, output the status register bits.
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction; the Read/Reset RD instruction is ac-
cepted during the 100μs time-out period. Data
Polling bit ADQ7 returns '0' while the erasure is in
progress and '1' when it has completed. The Tog-
gle bit ADQ6 toggles during the erase operation,
and stops when erase is completed.
After completion the Status Register bit ADQ5 re-
turns '1' if there has been an erase failure. In such
a situation, the Toggle bit ADQ2 can be used to
determine which block is not correctly erased. In
the case of erase failure, a Read/Reset RD in-
struction is necessary in order to reset the P/E.C.
Bank Erase (BKE) Instruction.
This instruction
uses six write cycles and is used to erase all the
blocks belonging to the selected bank. The Erase
Set-up command 80h is written to address 555h
on the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10h is similarly
written on the sixth cycle after another two Coded
cycles at an address within the selected bank. If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts and the device is reset to Read Array.
It is not necessary to program the array with 00h
first as the P/E.C. will automatically do this before
erasing it to FFh. Read operations within the same
bank after the sixth rising edge of W or E output
the Status Register bits. During the execution of
the erase by the P/E.C., Data Polling bit ADQ7 re-
turns '0', then '1' on completion. The Toggle bit
ADQ6 toggles during erase operation and stops
when erase is completed. After completion the
Status Register bit ADQ5 returns '1' if there has
been an Erase Failure.
Erase Suspend (ES) Instruction.
In a dual bank
memory the Erase Suspend instruction is used to
read data within the bank where erase is in
progress. It is also possible to program data in
blocks not being erased.
The Erase Suspend instruction consists of writing
the command B0h without any specific address.
No Coded Cycles are required. Erase suspend is
accepted only during the Block Erase instruction
execution. The Toggle bit ADQ6 stops toggling
when the P/E.C. is suspended within 15μs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be set to
Read Memory Array mode. When erase is sus-
pended, a Read from blocks being erased will out-
put ADQ2 toggling and ADQ6 at '1'. A Read from
a block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in ADQ6 toggling when the
data is being programmed.
Erase Resume (ER) Instruction.
If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at an address within the bank be-
ing erased and without any Coded Cycle.
M59MR032C, M59MR032D
Table 17. Instructions (1,2)
19/49
M59MR032C, M59MR032D

Note:1. Commands not interpreted in this table will default to read array mode. For Coded cycles address inputs A11-A20 are don’t care. X = Don’t Care. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
mand cycles. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. High voltage on VPP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.
M59MR032C, M59MR032D
STATUS REGISTER BITS

P/E.C. status is indicated during execution by Data
Polling on ADQ7, detection of Toggle on ADQ6
and ADQ2, or Error on ADQ5 bits. Any read at-
tempt within the Bank being modified and during
Program or Erase command execution will auto-
matically output these five Status Register bits.
The P/E.C. automatically sets bits ADQ2, ADQ5,
ADQ6 and ADQ7. Other bits (ADQ0, ADQ1 and
ADQ4) are reserved for future use and should be
masked (see Table 18). Read attempts within the
bank not being modified will output array data.
Toggle bits ADQ6 and ADQ2 are affected by G
and/or E cycles regardless of the bank in which
these cycles refer to. This means that toggle bits
are in a state that depends on the amount of ac-
cesses to both banks and not only to the bank
where erasing or programming is on going. Status
Register Bits must be accessed according to the
device configuration (see Figure 4).
Data Polling Bit (ADQ7).
When Programming
operations are in progress, this bit outputs the
complement of the bit being programmed on
ADQ7. In case of a double word program opera-
tion, the complement is done on ADQ7 of the last
word written to the command interface, i.e. the
data written in the fifth cycle. During Erase opera-
tion, it outputs a ’0’. After completion of the opera-
tion, ADQ7 will output the bit last programmed or
a ’1’ after erasing. Data Polling is valid and only ef-
fective during P/E.C. operation, that is after the
fourth W pulse for programming or after the sixth
W pulse for erase. It must be performed at the ad-
dress being programmed or at an address within
the block being erased. See Figure 17 for the Data
Polling flowchart and Figure 15 for the Data Polling
waveforms. ADQ7 will also flag the Erase Sus-
pend mode by switching from ’0’ to ’1’ at the start
of the Erase Suspend. In order to monitor ADQ7 in
the Erase Suspend mode an address within a
block being erased must be provided. For a Read
Operation in Suspend mode, ADQ7 will output ’1’
if the read is attempted on a block being erased
and the data value on other blocks. During Pro-
gram operation in Erase Suspend Mode, ADQ7
will have the same behavior as in the normal pro-
gram execution outside of the suspend mode.
Toggle Bit (ADQ6).
When Programming or Eras-
ing operations are in progress, successive at-
tempts to read ADQ6 will output complementary
data. ADQ6 will toggle following toggling of either
G, or E when G is at VIL. The operation is complet-
ed when two successive reads yield the same out-
put data. The next read will output the bit last
programmed or a ’1’ after erasing. The toggle bit
ADQ6 is valid only during P/E.C. operations, that
is after the fourth W pulse for programming or after
the sixth W pulse for Erase. ADQ6 will be set to ’1’
if a Read operation is attempted on an Erase Sus-
pend block. When erase is suspended ADQ6 will
toggle during programming operations in a block
different from the block in Erase Suspend. Either
E or G toggling will cause ADQ6 to toggle. See
Figure 18 for Toggle Bit flowchart and Figure 16
for Toggle Bit waveforms.
Toggle Bit (ADQ2).
This toggle bit, together with
ADQ6, can be used to determine the device status
during the Erase operations. During Erase Sus-
pend a read from a block being erased will cause
ADQ2 to toggle. A read from a block not being
erased will output data. ADQ2 will be set to ’1’ dur-
ing program operation. After erase completion and
if the error bit ADQ5 is set to ’1’, ADQ2 will toggle
if the faulty block is addressed.
Error Bit (ADQ5).
This bit is set to ’1’ by the P/
E.C. when there is a failure of programming or
block erase, that results in invalid data in the mem-
ory block. In case of an error in block erase or pro-
gram, the block in which the error occurred or to
which the programmed data belongs, must be dis-
carded. Other Blocks may still be used. The error
bit resets after a Read/Reset (RD) instruction. In
case of success of Program or Erase, the error bit
will be set to ’0’.
Erase Timer Bit (ADQ3).
This bit is set to ‘0’ by
the P/E.C. when the last block Erase command
has been entered to the Command Interface and it
is awaiting the Erase start. When the erase time-
out period is finished, ADQ3 returns to ‘1’, in the
range of 80μs to 120μs.
21/49
M59MR032C, M59MR032D
Table 18. Status Register Bits (1)

Note:1. Status Register bits do not consider BINV. DQ7 and DQ2 require a valid address when reading status information.
POWER CONSUMPTION
Power-down

The memory provides Reset/Power-down control
input RP. The Power-down function can be acti-
vated only if the relevant Configuration Register bit
is set to ’1’. In this case, when the RP signal is
pulled at VSS the supply current drops to typically
ICC2 (see Table 28), the memory is deselected and
the outputs are in high impedance.If RP is pulled
to VSS during a Program or Erase operation, this
operation is aborted in tPLQ7V and the memory
content is no longer valid (see Reset/Power-down
input description).
Power-up

The memory Command Interface is reset on Pow-
er-up to Read Array. Either E or W must be tied to
VIH during Power-up to allow maximum security
and the possibility to write a command on the first
rising edge of W. At Power-up the device is config-
ured as: page mode: (CR15 = 1) power-down disabled: (CR10 = 0) BINV disabled: (CR14 = 0)
and all blocks are protected and unlocked.
Supply Rails

Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the VDD rails decoupled with a 0.1μF capac-
itor close to the VDD, VDDQ and VSS pins. The PCB
trace widths should be sufficient to carry the re-
quired VDD program and erase currents.
M59MR032C, M59MR032D
Table 19. Query Structure Overview

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 20, 21 and 22. Query data are always presented on the lowest order data outputs.
Table 20. CFI Query Identification String

Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’.
COMMON FLASH INTERFACE (CFI)

The Common Flash Interface (CFI) specification is
a JEDEC approved, standardised data structure
that can be read from the Flash memory device.
CFI allows a system software to query the flash
device to determine various electrical and timing
parameters, density information and functions
supported by the device. CFI allows the system to
easily interface to the Flash memory, to learn
about its features and parameters, enabling the
software to configure itself when necessary.
Tables 19, 20, 21, 22, 23 and 24 show the address
used to retrieve each data.
The CFI data structure gives information on the
device, such as the sectorization, the command
set and some electrical specifications. Tables 19,
20, 21 and 22 show the addresses used to retrieve
each data. The CFI data structure contains also a
security area; in this section, a 64 bit unique secu-
rity number is written, starting at address 81h. This
area can be accessed only in read mode and there
are no ways of changing the code after it has been
written by ST. Write a read instruction to return to
Read mode. Refer to the CFI Query instruction to
understand how the M59MR032 enters the CFI
Query mode.
23/49
M59MR032C, M59MR032D
Table 21. CFI Query System Interface Information
M59MR032C, M59MR032D
Table 22. Device Geometry Definition
25/49
M59MR032C, M59MR032D
Table 23. Primary Algorithm-Specific Extended Query Table
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