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M59DR032EA10ZB6N/a2198avai32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORY
M59DR032EA10ZB6STN/a8383avai32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORY


M59DR032EA10ZB6 ,32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYAbsolute Maximum Ratings . . . . . . . 20DC and AC PARAMETERS . 21Table 14. Operating an ..
M59DR032EA10ZB6 ,32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYLogic Diagram . . 5Table 1. Signal Names . . . 5Figure 3. TFBGA Connections (Top view ..
M59MR032C120GC6T ,32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash MemoryLogic Diagram– Parameter Blocks (Top or Bottom location) ■ DUAL BANK OPERATIONS– Read within one Ba ..
M59PW016 ,16 MBIT (1MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYfeatures an innovative command,ROM pin-out compatible, non-volatile LightFlash Multiple Word Progra ..
M59PW016-100M1 ,16 MBIT (1MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. PDIP and SDIP Connections ..
M59PW064 ,64 MBIT (4MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYfeatures an innovative command,ROM pin-out compatible, non-volatile LightFlash Multiple Word Progra ..
M-991-01SMTR , Call Progress Tone Generator
MA02303GJ-R7 ,2200-2600 MHz, RF power amplifier IC for 2.4 GHz ISM
MA100L , UART-to- USB Bridge Controller
MA10100 ,Small-signal deviceElectrical Characteristics T = 25°C ± 3°CaParameter Symbol Conditions Min Typ Max UnitReverse curr ..
MA10701 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..
MA10702 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..


M59DR032EA10ZB6
32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORY
1/43April 2003
M59DR032EA
M59DR032EB

32 Mbit (2Mb x 16, Dual Bank, Page )
1.8V Supply Flash Memory
FEATURES SUMMARY
SUPPLY VOLTAGE
–VDD = VDDQ = 1.65V to 2.2V for Program,
Erase and Read
–VPP = 12V for fast Program (optional) ASYNCHRONOUS PAGE MODE READ Page Width: 4 Words Page Access: 35ns Random Access: 85ns, 100ns and 120ns PROGRAMMING TIME 10μs by Word typical Double Word Program Option MEMORY BLOCKS Dual Bank Memory Array: 4 Mbit, 28 Mbit Parameter Blocks (Top or Bottom location) DUAL BANK OPERATIONS Read within one Bank while Program or
Erase within the other No delay between Read and Write operations BLOCK LOCKING All blocks locked at Power up Any combination of blocks can be locked
–WP for Block Lock-Down COMMON FLASH INTERFACE (CFI) 64 bit Unique Device Identifier 64 bit User Programmable OTP Cells ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per
BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 0020h Top Device Code, M59DR032EA: 00A0h Bottom Device Code, M59DR032EB: 00A1h
Figure 1. Packages
M59DR032EA, M59DR032EB
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 2. Bank Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Reset/Power-Down Input (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VDD and VDDQ Supply Voltage (1.65V to 2.2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VPP Programming Voltage (11.4V to 12.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Dual Bank Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Quadruple Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Enter Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Exit Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Double Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Quadruple Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3/43
M59DR032EA, M59DR032EB

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 6. Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 7. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . .15
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 13. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 14. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 5. Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 6. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 7. Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 8. Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 17. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 9. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 18. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 10. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 19. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M59DR032EA, M59DR032EB
Figure 11. Reset/Power-Down AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 20. Reset/Power-Down AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 12. Data Polling DQ7 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 21. Data Polling and Toggle Bits AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 14. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 15. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 16. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Outline. . . . . . . . . . . . . .32
Table 22. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . .32
Figure 17. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Outline. . . . . . . . . . . . . . .33
Table 23. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . .33
Figure 18. TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . .34
Figure 19. TFBGA48 Daisy Chain - PCB Connection Proposal (Top view through package). . . . .34
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 25. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 26. Bank A, Top Boot Block Addresses M59DR032EA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 27. Bank B, Top Boot Block Addresses M59DR032EA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 28. Bank B, Bottom Boot Block Addresses M59DR032EB . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 29. Bank A, Bottom Boot Block Addresses M59DR032EB . . . . . . . . . . . . . . . . . . . . . . . . . .38
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 32. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5/43
M59DR032EA, M59DR032EB
SUMMARY DESCRIPTION

The M59DR032E is a 32 Mbit (2Mbit x16) non-vol-
atile Flash memory that may be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 1.65V to 2.2V VDD
supply for the circuitry and a 1.65V to 2.2V VDDQ
supply for the Input/Output pins. An optional 12V
VPP power supply is provided to speed up custom-
er programming.
The device features an asymmetrical block archi-
tecture. M59DR032E has an array of 71 blocks
and is divided into two banks, Banks A and B, pro-
viding Dual Bank operations. While programming
or erasing in Bank A, read operations are possible
in Bank B or vice versa. Only one bank at a time is
allowed to be in program or erase mode. The bank
architecture is summarized in Table 2, and the
Block Addresses are shown in Appendix A. The
Parameter Blocks are located at the top of the
memory address space for the M59DR032EA,
and at the bottom for the M59DR032EB.
Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Each block can be programmed and erased over
100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The M59DR032E features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have two
levels of protection. They can be individually
locked and locked-down preventing any acciden-
tal programming or erasure. All blocks are locked
at Power Up and Reset.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system’s design. The Protection Register is di-
vided into two 64 bit segments. The first segment
contains a unique device number written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user. Figure 4, shows the Security Block and
Protection Register Memory Map.
The device is available in TFBGA48 (7 x 12mm
and 7 x 7mm, 0.75mm pitch) packages and it is
supplied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
Table 1. Signal Names
M59DR032EA, M59DR032EB
Figure 3. TFBGA Connections (Top view through package)
Table 2. Bank Organization
7/43
M59DR032EA, M59DR032EB
M59DR032EA, M59DR032EB
SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
During a write operation the address inputs are
latched on the falling edge of Chip Enable E or
Write Enable W, whichever occurs last.
Data Input/Output (DQ0-DQ15).
The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Write Bus op-
eration.
Both input data and commands are latched on the
rising edge of Write Enable W. The data output is
the Memory Array, the Common Flash Interface,
the Electronic Signature Manufacturer or Device
codes, the Block Protection status, the Configura-
tion Register status or the Status Register Data
depending on the address.
The data bus is high impedance when the chip is
deselected, Output Enable G is at VIH, or RP is at
VIL.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at VIH the device is deselected and the power con-
sumption is reduced to the standby level.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read op-
eration. When Output Enable is at VIH the outputs
are high impedance.
Write Enable (W).
The Write Enable controls the
Bus Write operation of the memory’s Command
Interface.
Write Protect (WP).
Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the
locked-down blocks cannot be locked or unlocked.
When Write Protect is at VIH, the Lock-Down is
disabled and the locked-down blocks can be
locked or unlocked. (refer to Table 10, Lock Sta-
tus).
Reset/Power-Down Input (RP).
The Reset/Pow-
er-Down input provides hardware reset of the
memory, and/or Power-Down functions, depend-
ing on the Configuration Register status. A Reset
or Power-Down of the memory is achieved by pull-
ing RP to VIL for at least tPLPH.
The Reset/Power-Down function is set in the Con-
figuration Register (see Set Configuration Regis-
ter command). If it is set to ‘0’ the Reset function is
enabled, if it is set to ‘1’ the Power-Down function
is enabled. After a Reset or Power-Up the power
save function is disabled and all blocks are locked.
The memory Command Interface is reset on Pow-
er Up to Read Array. Either Chip Enable or Write
Enable must be tied to VIH during Power Up to al-
low maximum security and the possibility to write a
command on the first rising edge of Write Enable.
After a Reset, when the device is in Read, Erase
Suspend Read or Standby, valid data will be out-
put tPHQ7V1 after the rising edge of RP. If the de-
vice is in Erase or Program, the operation will be
aborted and the reset recovery will take a maxi-
mum of tPLQ7V. The memory will recover from
Power-Down tPHQ7V2 after the rising edge of RP.
See Tables 17, 18 and Figure 11.
VDD and VDDQ Supply Voltage (1.65V to 2.2V).

VDD provides the power supply to the internal core
of the memory device. It is the main power supply
for all operations (read, program and erase).
VDDQ provides the power supply to the I/O pins.
VDD and VDDQ must be at the same voltage.
VPP Programming Voltage (11.4V to 12.6V).
VPP
provides a high voltage power supply for fast fac-
tory programming. VPP is required to use the Dou-
ble Word and Quadruple Word Program
commands.
VSS Ground.
VSS ground is the reference for the
core supply. It must be connected to the system
ground.
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1μF ca-
pacitor close to the pin. See Figure 6, AC Mea-
surement Load Circuit. The PCB trace widths
should be sufficient to carry the required VPP
program and erase currents.
9/43
M59DR032EA, M59DR032EB
BUS OPERATIONS

The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write, Output Disable, Standby
and Reset/Power-Down, see Table 3.
Read.
Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is per-
formed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asynchronous read
cycles (Random Read). Both Chip Enable E and
Output Enable G must be at VIL in order to read the
output of the memory.
Write.
Write operations are used to give com-
mands to the memory or to latch Input Data to be
programmed. A write operation is initiated when
Chip Enable E and Write Enable W are at VIL with
Output Enable G at VIH. Addresses are latched on
the falling edge of W or E whichever occurs last.
Commands and Input Data are latched on the ris-
ing edge of W or E whichever occurs first. Noise
pulses of less than 5ns typical on E, W and G sig-
nals do not start a write cycle.
Output Disable.
The data outputs are high im-
pedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby.
The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The pow-
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Automatic Standby.
In Read mode, after 150ns
of bus inactivity and when CMOS levels are driving
the addresses, the chip automatically enters a
pseudo-standby mode where consumption is re-
duced to the CMOS standby value, while outputs
still drive the bus.
Power-Down.
The memory is in Power-Down
when the Configuration Register is set for Power-
Down and RP is at VIL. The power consumption is
reduced to the Power-Down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Dual Bank Operations.
The Dual Bank allows
data to be read from one bank of memory while a
program or erase operation is in progress in the
other bank of the memory. Read and Write cycles
can be initiated for simultaneous operations in dif-
ferent banks without any delay. Status Register
during Program or Erase must be monitored using
an address within the bank being modified.
Table 3. Bus Operations

Note: X = Don’t care.
M59DR032EA, M59DR032EB
COMMAND INTERFACE

All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. Two bus
write cycles are required to unlock the Command
Interface. They are followed by a setup or confirm
cycle. The increased number of write cycles is to
ensure maximum data security.
The Program/Erase Controller provides a Status
Register whose output may be read at any time to
monitor the progress or the result of the operation.
The Command Interface is reset to Read mode
when power is first applied or exiting from Reset.
Command sequences must be followed exactly.
Any invalid combination of commands will reset
the device to Read mode
Read/Reset Command.
The Read/Reset com-
mand returns the device to Read mode. One Bus
Write cycle is required to issue the Read/Reset
command and return the device to Read mode.
Subsequent Read operations will read the ad-
dressed location and output the data. The write cy-
cle can be preceded by the unlock cycles but it is
not mandatory.
Read CFI Query Command.
The Read CFI
Query command is used to read data from the
Common Flash Interface (CFI) and the Electronic
Signature (Manufacturer or the Device Code, see
Table 5). The Read CFI Query Command consists
of one Bus Write cycle. Once the command is is-
sued the device enters Read CFI mode. Subse-
quent Bus Read operations read the Common
Flash Interface or Electronic Signature. Once the
device has entered Read CFI mode, only the
Read/Reset command should be used and no oth-
er. Issuing the Read/Reset command returns the
device to Read mode.
See Appendix B, Common Flash Interface, Tables
31, 32, and 33 for details on the information con-
tained in the Common Flash Interface memory ar-
ea.
Auto Select Command.
The Auto Select com-
mand uses the two unlock cycles followed by one
write cycle to any bank address to setup the com-
mand. Subsequent reads at any address will out-
put the Block Protection status, Protection
Register and Protection Register Lock or the Con-
figuration Register status depending on the levels
of A0 and A1 (see Tables 6, 7 and 8). Once the
Auto Select command has been issued only the
Read/Reset command should be used and no oth-
er. Issuing the Read/Reset command returns the
device to Read mode.
Set Configuration Register Command.
The
M59DR032E contains a Configuration Register,
see Table 7, Configuration Register.
It is used to define the status of the Reset/Power-
Down functions. The value for the Configuration
Register is always presented on A0-A15, the other
address bits are ignored. Address input A10 de-
fines the status of the Reset/Power-Down func-
tions. If it is set to ‘0’ the Reset function is enabled,
if it is set to ‘1’ the Power-Down function is en-
abled. At Power Up the Configuration Register bit
is set to ‘0’.
The Set Configuration Register command is used
to write a new value to the Configuration Register.
The command uses the two unlock cycles followed
by one write cycle to setup the command and a
further write cycle to write the data and confirm the
command.
Program Command.
The Program command
uses the two unlock cycles followed by a write cy-
cle to set up the command and a further write cycle
to latch the Address and Data and start the Pro-
gram Erase Controller. Read operations within the
same bank output the Status Register after pro-
gramming has started.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole bank from ’0’ to ’1’. If the Program
command is used to try to set a bit from ‘0’ to ‘1’
Status Register Error bit DQ5 will be set to ‘1’, only
if VPP is in the range of 11.4V to 12.6V.
Double Word Program Command.
This feature
is offered to improve the programming throughput
by writing a page of two adjacent Words in parallel.
The VPP supply voltage is required to be from
11.4V to 12.6V for the Double Word Program com-
mand.
The command uses the two unlock cycles followed
by a write cycle to set up the command. A further
two cycles are required to latch the address and
data of the two Words and start the Program Erase
Controller.
The addresses must be the same except for the
A0. The Double Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Double Word Program command
cannot change a bit set to ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Double Word Program command is used to try to
set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5
will be set to ‘1’.
Quadruple Word Program Command.
The
Quadruple Word Program command improves the
11/43
M59DR032EA, M59DR032EB

programming throughput by writing a page of four
adjacent Words in parallel. The four Words must
differ only for the addresses A0 and A1. The VPP
supply voltage is required to be from 11.4V to
12.6V for the Quadruple Word Program com-
mand.
The command uses the two unlock cycles followed
by a write cycle to set up the command. A further
four cycles are required to latch the address and
data of the four Words and start the Program
Erase Controller.
The Quadruple Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Quadruple Word Program command
cannot change a bit set to ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Quadruple Word Program command is used to try
to set a bit from ‘0’ to ‘1’ Status Register Error bit
DQ5 will be set to ‘1’.
Enter Bypass Mode Command.
The Bypass
mode is used to reduce the overall programming
time when large memory arrays need to be pro-
grammed.
The Enter Bypass Mode command uses the two
unlock cycles followed by one write cycle to set up
the command. Once in Bypass mode, it is impera-
tive that only the following commands be issued:
Exit Bypass, Program, Double Word Program or
Quadruple Word Program.
Exit Bypass Mode Command.
The Exit Bypass
Mode command uses two write cycles to be set up
and confirmed. The unlock cycles are not required.
After the Exit Bypass Mode command, the device
resets to Read mode.
Program in Bypass Mode Command.
The
Program in Bypass Mode command can be is-
sued when the device is in Bypass mode (issue an
Enter Bypass Mode command). It uses the same
sequence of cycles as the Program command with
the exception of the unlock cycles.
Double Word Program in Bypass Mode Com-
mand.
The Double Word Program in Bypass
Mode command can be issued when the device is
in Bypass mode (issue an Enter Bypass Mode
command). It uses the same sequence of cycles
as the Double Word Program command with the
exception of the unlock cycles.
Quadruple Word Program in Bypass Mode
Command.
The Quadruple Word Program in By-
pass Mode command can be issued when the de-
vice is in Bypass mode (issue an Enter Bypass
Mode command). It uses the same sequence of
cycles as the Quadruple Word Program command
with the exception of the unlock cycles.
Block Lock Command.
The Block Lock com-
mand is used to lock a block and prevent Program
or Erase operations from changing the data in it.
All blocks are locked at Power-Up or Reset.
Three Bus Write cycles are required to issue the
Block Lock command. The first two bus cycles unlock the Command
Interface. The third bus cycle sets up the Block Lock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the Lock Status after issuing a Block Lock com-
mand.
The Block Lock bits are volatile, once set they re-
main set until a hardware Reset or Power-Down/
Power-Up. They are cleared by a Block Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.
Block Unlock Command.
The Block Unlock
command is used to unlock a block, allowing the
block to be programmed or erased.
Three Bus Write cycles are required to issue the
Block Unlock command. The first two bus cycles unlock the Command
Interface. The third bus cycle sets up the Block UnLock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the lock status after issuing a Block Unlock com-
mand. Refer to the section, Block Locking, for a
detailed explanation.
Block Lock-Down Command.
A locked or un-
locked block can be locked-down by issuing the
Block Lock-Down command. A locked-down block
cannot be programmed or erased, or have its pro-
tection status changed when WP is low, VIL. When
WP is high, VIH, the Lock-Down function is dis-
abled and the locked blocks can be individually un-
locked by the Block Unlock command.
Three Bus Write cycles are required to issue the
Block Lock-Down command. The first two bus cycles unlock the Command
Interface. The third bus cycle sets up the Block Lock-
Down command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Locked-Down
blocks revert to the locked (and not locked-down)
state when the device is reset on power-down. Ta-
ble 10 shows the Lock Status after issuing a Block
Lock-Down command. Refer to the section, Block
Locking, for a detailed explanation.
M59DR032EA, M59DR032EB
Block Erase Command.
The Block Erase com-
mand can be used to erase a block. It sets all the
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the device will return
to Read Array mode. It is not necessary to pre-pro-
gram the block as the Program/Erase Controller
does it automatically before erasing.
Six Bus Write cycles are required to issue the
command. The first two write cycles unlock the Command
Interface. The third write cycles sets up the command the fourth and fifth write cycles repeat the unlock
sequence the sixth write cycle latches the block address
and confirms the command.
Additional Block Erase confirm cycles can be is-
sued to erase other blocks without further unlock
cycles. All blocks must belong to the same bank; if
a new block belonging to the other bank is given,
the operation is aborted.
The additional Block Erase confirm cycles must be
given within the DQ3 erase timeout period. Each
time a new confirm cycle is issued the timeout pe-
riod restarts. The status of the internal timer can
be monitored through the level of DQ3, see Status
Register section for more details.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
After the command has been issued the Read/Re-
set command will be accepted during the DQ3 tim-
eout period, after that only the Erase Suspend
command will be accepted.
On successful completion of the Block Erase com-
mand, the device returns to Read Array mode.
Bank Erase Command.
The Bank Erase com-
mand can be used to erase a bank. It sets all the
bits within the selected bank to ’1’. All previous
data in the bank is lost. The Bank Erase command
will ignore any protected blocks within the bank. If
all blocks in the bank are protected then the Bank
Erase operation will abort and the data in the bank
will not be changed. It is not necessary to pre-pro-
gram the bank as the Program/Erase Controller
does it automatically before erasing.
As for the Block Erase command six Bus Write cy-
cles are required to issue the command. The first two write cycles unlock the Command
Interface. The third write cycles sets up the command the fourth and fifth write cycles repeat the unlock
sequence the sixth write cycle latches the block address
and confirms the command.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
For optimum performance, Bank Erase com-
mands should be limited to a maximum of 100 Pro-
gram/Erase cycles per Block. After 100 Program/
Erase cycles the internal algorithm will still operate
properly but some degradation in performance
may occur.
Dual operations are not supported during Bank
Erase operations and the command cannot be
suspended.
On successful completion of the Bank Erase com-
mand, the device returns to Read Array mode.
Erase Suspend Command.
The Erase Suspend
command is used to pause a Block Erase opera-
tion. In a Dual Bank memory it can be used to read
data within the bank where an Erase operation is
in progress. It is also possible to program data in
blocks not being erased.
One bus write cycle is required to issue the Erase
Suspend command. The Program/Erase Control-
ler suspends the Erase operation within 20μs of
the Erase Suspend command being issued and
bits 7, 6 and/ or 2 of the Status Register are set to
‘1’. The device is then automatically set to Read
mode. The command can be addressed to any
bank.
During Erase Suspend the memory will accept the
Erase Resume, Program, Read CFI Query, Auto
Select, Block Lock, Block Unlock and Block Lock-
Down commands.
Erase Resume Command.
The Erase Resume
command can be used to restart the Program/
Erase Controller after an Erase Suspend com-
mand has paused it. One Bus Write cycle is re-
quired to issue the command. The command must
be issued to an address within the bank being
erased. The unlock cycles are not required.
Protection Register Program Command.
The
Protection Register Program command is used to
Program the Protection Register (One-Time-Pro-
grammable (OTP) segment and Protection Regis-
ter Lock). The OTP segment is programmed 16
bits at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits
to ‘0’.
Four write cycles are required to issue the Protec-
tion Register Program command. The first two bus cycles unlock the Command
Interface. The third bus cycle sets up the Protection
Register Program command.
13/43
M59DR032EA, M59DR032EB
The fourth latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The OTP segment can be protected by program-
ming bit 1 of the Protection Register Lock. The
segment can be protected by programming bit 1 of
the Protection Register Lock. Bit 1 of the Protec-
tion Register Lock also protects bit 2 of the Protec-
tion Register Lock. Programming bit 2 of the
Protection Register Lock will result in a permanent
protection of Parameter Block #0 (see Figure 4,
Security Block and Protection Register Memory
Map). Attempting to program a previously protect-
ed Protection Register will result in a Status Reg-
ister error. The protection of the Protection
Register and/or the Security Block is not revers-
ible.
Table 4. Commands

Note: X = Don’t Care, BA = Block Address, PA = Program address, PD = Program Data, CRD = Configuration Register Data. For Coded
cycles address inputs A12-A20 are don’t care.
M59DR032EA, M59DR032EB
Table 5. Read Electronic Signature

Note: X = Don’t care.
Table 6. Read Block Protection

Note: X = Don’t care.
Table 7. Configuration Register

Note: X = Don’t care.
15/43
M59DR032EA, M59DR032EB
Table 8. Read Protection Register

Note: X= Don’t care.
Table 9. Program, Erase Times and Program, Erase Endurance Cycles

Note:1. Excludes the time needed to execute the sequence for program command. Same timing value if VPP = 12V
M59DR032EA, M59DR032EB
BLOCK LOCKING

The M59DR032E features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has two levels of protection. Lock/Unlock - this first level allows software-
only control of block locking. Lock-Down - this second level requires
hardware interaction before locking can be
changed.
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 10, de-
fines all of the possible protection states (WP,
DQ1, DQ0).
Reading a Block’s Lock Status

The lock status of every block can be read in the
Auto Select mode of the device. Subsequent
reads at the address specified in Table 6, will out-
put the protection status of that block. The lock
status is represented by DQ0 and DQ1. DQ0 indi-
cates the Block Lock/Unlock status and is set by
the Lock command and cleared by the Unlock
command. It is also automatically set when enter-
ing Lock-Down. DQ1 indicates the Lock-Down sta-
tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked State

The default status of all blocks on power-up or af-
ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper-
ations attempted on a locked block will reset the
device to Read Array mode. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com-
mands. An Unlocked block can be Locked by issu-
ing the Lock command.
Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be un-
locked by issuing the Unlock command.
Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can-
not be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked-
Down blocks revert to the Locked state when the
device is reset or powered-down.
The Lock-Down function is dependent on the WP
input pin. When WP=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
WP=1 (VIH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be individu-
ally unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WP
remains High. When WP is low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP was High. Device reset or power-down
resets all blocks, including those in Lock-Down, to
the Locked state.
Locking Operations During Erase Suspend

Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
17/43
M59DR032EA, M59DR032EB
Table 10. Lock Status

Note:1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Auto Select command with A1 = VIH and A0 = VIL. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
M59DR032EA, M59DR032EB
STATUS REGISTER

The Status Register provides information on the
current or previous Program or Erase operations.
Bus Read operations from any address within the
bank, always read the Status Register during Pro-
gram and Erase operations.
The various bits convey information about the sta-
tus and any errors of the operation.
The bits in the Status Register are summarized in
Table 12, Status Register Bits. Refer to Tables 11
and 12 in conjunction with the following text de-
scriptions.
Data Polling Bit (DQ7).
When Program opera-
tions are in progress, the Data Polling bit outputs
the complement of the bit being programmed on
DQ7. For a Double Word Program operation, it is
the complement of DQ7 for the last Word written to
the Command Interface.
During an Erase operation, it outputs a ’0’. After
completion of the operation, DQ7 will output the bit
last programmed or a ’1’ after erasing.
Data Polling is valid and only effective during P/
E.C. operation, that is after the fourth W pulse for
programming or after the sixth W pulse for erase.
It must be performed at the address being pro-
grammed or at an address within the block being
erased. See Figure 21 for the Data Polling flow-
chart and Figure 12 for the Data Polling wave-
forms.
DQ7 will also flag an Erase Suspend by switching
from ’0’ to ’1’ at the start of the Erase Suspend. In
order to monitor DQ7 in the Erase Suspend mode
an address within a block being erased must be
provided. DQ7 will output ’1’ if the read is attempt-
ed on a block being erased and the data value on
other blocks. During a program operation in Erase
Suspend, DQ7 will have the same behavior as in
the normal program.
Toggle Bit (DQ6).
When Program or Erase oper-
ations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6
will toggle following the toggling of either G or E.
The operation is completed when two successive
reads give the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing.
The Toggle Bit DQ6 is valid only during P/E.C. op-
erations, that is after the fourth W pulse for pro-
gramming or after the sixth W pulse for Erase.
DQ6 will be set to ’1’ if a read operation is attempt-
ed on an Erase Suspend block. When erase is
suspended DQ6 will toggle during programming
operations in a block different from the block in
Erase Suspend.
See Figure 15 for Toggle Bit flowchart and Figure
13 for Toggle Bit waveforms.
Toggle Bit (DQ2).
Toggle Bit DQ2, together with
DQ6, can be used to determine the device status
during erase operations.
During Erase Suspend a read from a block being
erased will cause DQ2 to toggle. A read from a
block not being erased will output data. DQ2 will
be set to '1' during program operation and to ‘0’ in
erase operation. If a read operation is addressed
to a block where an erase error has occurred, DQ2
will toggle.
Error Bit (DQ5).
The Error Bit can be used to
identify if an error occurs during a program or
erase operation.
The Error Bit is set to ‘1’ when a program or erase
operation has failed. When it is set to ‘0’ the pro-
gram or erase operation was successful.
If any Program command is used to try to set a bit
from ‘0’ to ‘1’ Status Register Error bit DQ5 will be
set to ‘1’, only if VPP is in the range of 11.4V to
12.6V.
The Error Bit is reset by a Read/Reset command.
Erase Timer Bit (DQ3).
The Erase Timer bit is
used to indicate the timeout period for an erase
operation.
When the last block Erase command has been en-
tered to the Command Interface and it is waiting
for the erase operation to start, the Erase Timer Bit
is set to ‘0’. When the erase timeout period is fin-
ished, DQ3 returns to ‘1’, (80μs to 120μs).
DQ0, DQ1 and DQ4 are reserved for future use

and should be masked.
Table 11. Polling and Toggle Bits
19/43
M59DR032EA, M59DR032EB
Table 12. Status Register Bits

Note:1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. In case of double word program DQ7 refers to the last word input.
M59DR032EA, M59DR032EB
MAXIMUM RATING

Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 13. Absolute Maximum Ratings

Note:1. Depends on range. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
21/43
M59DR032EA, M59DR032EB
DC AND AC PARAMETERS

This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 14, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 14. Operating and AC Measurement Conditions
Figure 5. Testing Input/Output Waveforms
Table 15. Capacitance

Note: Sampled only, not 100% tested.
M59DR032EA, M59DR032EB
Table 16. DC Characteristics

Note:1. Sampled only, not 100% tested. VPP may be connected to 12V power supply for a total of less than 100 hrs. For standard program/erase operation VPP is don’t care.
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