M59DR008F ,8 MBIT (512KB X16, DUAL BANK, PAGE) LOW VOLTAGE FLASH MEMORYLogic Diagram■ DUAL BANK OPERATIONS– Read within one Bank while Program orErase within the other– N ..
M59DR016C ,16 MBIT (1MB X16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYLogic Diagram■ DUAL BANK OPERATIONS– Read within one Bank while Program orErase within the other– N ..
M59DR032A120ZB6T ,32 MBIT (2MB X16, DUAL BANK) LOW VOLTAGE FLASH MEMORYLogic Diagram■ DUAL BANK OPERATIONS– Read within one Bank while Program orErase within the other– N ..
M59DR032EA10ZB6 ,32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYAbsolute Maximum Ratings . . . . . . . 20DC and AC PARAMETERS . 21Table 14. Operating an ..
M59DR032EA10ZB6 ,32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYLogic Diagram . . 5Table 1. Signal Names . . . 5Figure 3. TFBGA Connections (Top view ..
M59MR032C120GC6T ,32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash MemoryLogic Diagram– Parameter Blocks (Top or Bottom location) ■ DUAL BANK OPERATIONS– Read within one Ba ..
M-991-01SMTR , Call Progress Tone Generator
MA02303GJ-R7 ,2200-2600 MHz, RF power amplifier IC for 2.4 GHz ISM
MA100L , UART-to- USB Bridge Controller
MA10100 ,Small-signal deviceElectrical Characteristics T = 25°C ± 3°CaParameter Symbol Conditions Min Typ Max UnitReverse curr ..
MA10701 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..
MA10702 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..
M59DR008E-M59DR008F
8 MBIT (512KB X16, DUAL BANK, PAGE) LOW VOLTAGE FLASH MEMORY
1/38June 2001
M59DR008E
M59DR008F Mbit (512Kb x16, Dual Bank, Page)
1.8V Supply Flash Memory SUPPLY VOLTAGE
–VDD =VDDQ= 1.65Vto 2.2V for Program,
Erase and Read
–VPP= 12V for fast Program (optional) ASYNCHRONOUS PAGE MODE READ Page Width:4 words Page Access: 35ns Random Access: 100ns PROGRAMMING TIME 10μsby Word typical Double Word Programming Option MEMORY BLOCKS Dual Bank Memory Array:4 Mbit-4 Mbit Parameter Blocks (Topor Bottom location) DUAL BANK OPERATIONS Read within one Bank while Program or
Erase within the other No delay between Read and Write operations BLOCK PROTECTION/UNPROTECTION All Blocks protectedat Power Up Any combinationof Blocks canbe protected COMMON FLASH INTERFACE (CFI) 64bit SECURITY CODE ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M59DR008E: A2h Bottom Device Code, M59DR008F: A3h
M59DR008E, M59DR008F2/38
Table1. Signal Names
3/38
M59DR008E, M59DR008F
DESCRIPTIONThe M59DR008is an8 Mbit non-volatile Flash
memory that may be erased electricallyat block
level and programmed in-system ona Word-by-
Word basis usinga 1.65Vto 2.2V VDD supply for
the circuitry. For Program and Erase operations
the necessary high voltages are generated inter-
nally. The device supports asynchronous page
mode fromall the blocksof the memory array.
The array matrix organization allows each blockto erased and reprogrammed without affecting
other blocks.All blocks are protected against pro-
gramming and eraseat Power Up. Blocks canbe
unprotectedto make changesin the application
and then reprotected.
Instructions for Read/Reset, Auto Select, Write
Configuration Register, Programming, Block
Erase, Bank Erase, Erase Suspend, Erase Re-
sume, Block Protect, Block Unprotect, Block Lock-
ing, CFI Query, are writtento the memory through Command Interface using standard micropro-
cessor write timings.
The deviceis offeredin TSOP48 (12x20 mm)
andin TFBGA48 (0.75 mm pitch) packages andit supplied withall the bits erased (setto ‘1’).
OrganizationThe M59DR008is organizedas 512Kb x16 bits.
A0-A18 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory controlis providedby
Chip EnableE, Output EnableG and Write Enable inputs.
Reset RPis usedto resetall the memory circuitry
andto set the chipin power down modeif this
functionis enabledbya proper settingof the Con-
figuration Register. Erase and Program operations
are controlledbyan internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
DQ7 providesa Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides errorbit indicate the stateof the P/E.C operations.
Memory BlocksThe device features asymmetrically blocked archi-
tecture. M59DR008 hasan arrayof23 blocks and divided into two banksA andB, providing Dual
Bank operations. While programmingor erasingin
BankA, read operations are possible into BankB vice versa. The memory also featuresan erase
suspend allowingto reador programin another
block within the same bank. Once suspended the
erase canbe resumed. The Bank Size and Sector-
ization are summarizedin Table7. Parameter
Blocks are locatedat the topof the memory ad-
dress space for the M59DR008E, andat the bot-
tom for the M59DR008F. The memory maps are
shownin Tables3,4,5 and6.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Programor Erase provides additional data
security.All blocks are protectedat Power Up.In-
structions are providedto protector unprotect any
blockin the application.A second register locks
the protection status while WPis low (see Block
Locking description). The Reset command does
not affect the configurationof unprotected blocks
and the Configuration Register status.
Table2. Absolute Maximum Ratings(1)Note:1. Exceptforthe rating "Operating Temperature Range", stresses above those listedinthe Table "Absolute Maximum Ratings" may
cause permanent damagetothe device. Theseare stress ratings only and operationofthe deviceat theseorany otherconditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periods may affect device reliability.Referalsotothe STMicroelectronics SUREProgramand otherrelevant qual-
ity documents. Dependson range. Minimum Voltage may undershootto –2V during transition andfor less than 20ns.
M59DR008E, M59DR008F4/38
Table3. BankA, Top Boot Block Addresses
M59DR008E
Table4. BankB, Top Boot Block Addresses
M59DR008E
Table5. BankB, Bottom Boot Block Addresses
M59DR008F
Table6. BankA, Bottom Boot Block Addresess
M59DR008F
5/38
M59DR008E, M59DR008F
SIGNAL DESCRIPTIONSSee Figure1 and Table1.
Address Inputs (A0-A18). The address inputs
for the memory array are latched duringa write op-
eration on the falling edgeof Chip EnableEor
Write Enable W, whichever occurs last.
Data Input/Output (DQ0-DQ15). The Input is
datatobe programmedin the memory arrayora
commandtobe writtento the Command Interface
(C.I.) Both input data and commands are latched the rising edgeof Write Enable W. The Ouput data from the Memory Array, the Common Flash
Interface, the Electronic Signature Manufacturer Device codes, the Block Protection status, the
Configuration Register statusor the Status Regis-
ter Data Pollingbit DQ7, the Toggle Bits DQ6 and
DQ2, the Errorbit DQ5. The data busis high im-
pedance when the chipis deselected, Output En-
ableGisat VIH,or RPisat VIL.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers.Eat VIH deselects
the memory and reduces the power consumption the standby level.E can alsobe usedtocontrol
writingto the command register andto the memo- array, whileW remainsat VIL.
Output Enable (G). The Output Enable gates the
outputs through the data buffers duringa read op-
eration. WhenGisat VIH the outputs are High im-
pedance.
WriteEnable(W). This input controls writingto
the Command Register and Data latches. Data are
latchedon the rising edgeof W.
Write Protect (WP). This input givesan addition- hardware protection level against programor
erase when pulledat VIL,as describedin the Block
Lock instruction description.
Reset/Power Down Input (RP). The RP input
provides hardware resetof the memory (without
affecting the Configuration Register status), and/ Power Down functions, depending on the Con-
figuration Register status. Reset/Power Downof
the memoryis achievedby pulling RPto VILforat
least tPLPH. When the reset pulseis given,if the
memoryisin Read, Erase Suspend Read or
Standby,it will output new valid datain tPHQ7V1af-
ter the rising edgeof RP.If the memoryisin Erase Program modes, the operation will be aborted
and the reset recovery will takea maximumot
tPLQ7V. The memory will recover from Power
Down (when enabled)in tPHQ7V2 after the rising
edgeof RP. See Tables 24,26 and Figure 10.
VDD and VDDQ Supply Voltage (1.65Vto 2.2V).The main power supply forall operations (Read,
Program and Erase). VDD and VDDQ must beat
thesamevoltage.
VPP Programming Voltage (11.4Vto 12.6V). Used provide high voltage for fast factory program-
ming. High voltageon VPP pinis requiredto use
the Double Word Program instruction.Itis also
possibleto perform word programor erase instruc-
tions with VPP pin grounded.
VSS Ground. VSSis the reference forall the volt-
age measurements.
DEVICE OPERATIONSThe following operations canbe performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Dis-
able, Standby, Reset/Power Down and Block
Locking. See Table8.
Read. Read operations are usedto output the
contentsof the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Statusor the Configuration Register
status. Read operationof the memory arrayis per-
formedin asynchronous page mode, that provides
fast access time. Datais internally read and storeda page buffer. The page hasa sizeof4 words
andis addressedby A0-A1 address inputs. Read
operationsof the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performedas single asyncronous read
cycles (Random Read). Both Chip EnableE and
Output EnableG mustbeat VILin orderto read the
outputof the memory.
Write. Write operations are usedto give Instruc-
tion Commandsto the memoryorto latch Input
Datatobe programmed.A write operationis initi-
ated when Chip EnableE and Write EnableW are VIL with Output EnableGat VIH. Addresses are
latchedon the falling edgeofWorE whichever oc-
curs last. Commands and Input Data are latched the rising edgeofWorE whichever occurs first.
Noise pulsesof less than 5ns typicalon E,W and signalsdo not starta write cycle.
Table7. BankSizeand Sectorization
M59DR008E, M59DR008F6/38
Table8. User Bus Operations(1)Note:1.X= Don't care.
Table9. Read Electronic Signature (AS and Read CFI instructions)
Table 10. Read Block Protection (AS and Read CFI instructions)
Table 11. Read Configuration Register (AS and Read CFI instructions)
Automatic Standby. Whenin Read mode, after
150nsof bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
tersa pseudo-standby mode where consumption reducedto the CMOS standby value, while out-
puts still drive the bus.
Power Down. The memoryisin Power Down
when the Configuration Registeris set for Power
Down and RPisat VIL. The power consumptionis
reducedto the Power Down level, and Outputs are high impedance, independentof the Chip En-
ableE, Output EnableGor Write EnableW inputs.
Block Locking. Any combinationof blocks can temporarily protected against Program or
Eraseby setting the lock register and pulling WP VIL (see Block Lock instruction).
Dual Bank Operations. The Dual Bank allowsto
read data from one bankof memory whilea pro-
gramor erase operationisin progressin the other
bankof the memory. Read and Write cycles can initiatedfor simultaneous operationsin different
banks without any delay. Status Register during
Programor Erase mustbe monitored usingan ad-
dress within the bank being modified.
Output Disable. The data outputs are high im-
pedance when the Output EnableGisat VIH with
Write EnableWat VIH.
Standby. The memoryisin standby when Chip
EnableEisat VIH and the P/E.C.is idle. The pow- consumptionis reducedto the standby level
and the outputs are high impedance, independent the Output EnableGor Write EnableW inputs.
7/38
M59DR008E, M59DR008F
INSTRUCTIONS AND COMMANDSSeventeen instructions are defined (see Table
14), and the internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits canbe readat any time, dur-
ing programmingor erase,to monitor the progress the operation.
Instructions, madeupof oneor more commands
writtenincycles, can begivento theProgram/
Erase Controller througha Command Interface
(C.I.). The C.I. latches commands writtento the
memory. Commands are madeof address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followedbyan input
commandora confirmation command. The Coded
Sequence consistsof writing the data AAhat the
address 555h during the first cycle and the data
55hat the address 2AAh during the second cycle.
Instructions are composedofuptosix cycles. The
first two cycles inputa Coded Sequenceto the
Command Interface whichis commonto all in-
structions (see Table 14). The third cycle inputs
the instruction set-up command. Subsequent cy-
cles output the addressed data, Electronic Signa-
ture, Block Protection, Configuration Register
Statusor CFI Queryfor Read operations.In order give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. Fora Program instruction, the
fourth command cycle inputs the address and databe programmed. Fora Double Word Program-
ming instruction, the fourth and fifth command cy-
cles input the address and data to be
programmed. Fora Block Erase and Bank Erase
instructions, the fourth and fifth cycles inputa fur-
ther Coded Sequence before the Erase confirm
command on the sixth cycle. Any combinationof
blocksof the same memory bank canbe erased.
Erasureofa memory block maybe suspended,in
orderto read data from another blockorto pro-
gram datain another block, and then resumed.
When poweris first applied the command interface resetto Read Array.
Command sequencing must be followed exactly.
Any invalid combinationof commands will reset
the deviceto Read Array. The increased number cycles has been chosento ensure maximum
data security.
Read/Reset (RD) Instruction. The Read/Reset
instruction consistsof one write cycle giving the
command F0h.It can be optionally precededby
the two Coded Cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read.
CFI Query (RCFI) Instruction. Common Flash
Interface Query modeis entered writing 98hat ad-
dress 55h. The CFI data structure gives informa-
tionon the device, suchas the sectorization, the
command set and some electrical specifications.
Tables 15, 19, 20 and 21 show the addresses
usedto retrieve each data. The CFI data structure
contains alsoa security area;in this section,a64
bit unique security numberis written, startingat
address 80h. This area canbe accessed onlyin
read modeby the final user and there areno ways changing the code afterit has been writtenby
ST. Writea read instruction (RD)to returnto Read
mode.
Table 12. Commands
M59DR008E, M59DR008F8/38
Auto Select (AS) Instruction. This instruction
uses two Coded Cycles followedby one write cy-
cle giving the command 90hto address 555h for
command set-up.A subsequent read will output
the Manufactureror the Device Code (Electronic
Signature), the Block Protection statusor the Con-
figuration Register status dependingon the levels A0 and A1 (see Tables9, 10 and 11). A7-A2
must beat VIL, while other address input are ig-
nored. The bank addressis don’t care for thisin-
struction. The Electronic Signature can be read
from the memory allowing programming equip-
mentor applicationsto automatically match their
interfaceto the characteristicsof M59DR008. The
Manufacturer Codeis output when the address
lines A0 andA1 areat VIL, the Device Codeis out-
put when A0isat VIH with A1at VIL.
The codes are output on DQ0-DQ7 with DQ8-
DQ15at 00h. The AS instruction also allows the
accessto the Block Protection Status. After giving
the AS instruction, A0is setto VIL with A1at VIH,
while A12-A18 define the addressof the blockto verified.A readin these conditions will outputa
01hif the blockis protected anda 00hif the block not protected.
The AS Instruction finally allows the accessto the
Configuration Register statusif both A0 and A1
are setto VIH.If DQ10is'0' only the Reset function activeas RPis setto VIL (defaultat power-up). DQ10is'1' both the Reset and the Power Down
functions willbe achievedby pulling RPto VIL.The
other bitsof the Configuration Register are re-
served and must be ignored.A reset command
puts the devicein read array mode.
Write Configuration Register (CR) Instruc-
tion. This instruction uses two Coded Cycles fol-
lowedby one write cycle giving the command 60h address 555h.A further write cycle giving the
command 03h writes the contentsof address bits
A0-A15to the 16 bits configuration register. Bits
writtenby inputs A0-A9 and A11-A15 are reserved
for future use. Address input A10 defines the sta-
tusof the Reset/Power Down functions.It mustbe
setto VILto enable only the Reset function andto
VIHto enable also the Power Down function.At
Power Upall the Configuration Register bits are
resetto '0'.
Enter Bypass Mode (EBY) Instruction. This in-
struction uses the two Coded cycles followedby
one write cycle giving the command 20hto ad-
dress 555h for mode set-up. Oncein Bypass
mode, the device will accept the Exit Bypass
(XBY) and Programor Double Word Programin
Bypass mode (PGBY, DPGBY) commands. The
Bypass mode allowsto reduce the overall pro-
gramming time when large memory arrays needto programmed.
Exit Bypass Mode (XBY) Instruction. This in-
struction uses two write cycles. The first inputsto
the memory the command 90h and the secondin-
puts the Exit Bypass mode confirm (00h). After the
XBY instruction, the device resetsto Read Memo- Array mode.
Program in Bypass Mode (PGBY) Instruc-
tion. This instruction uses two write cycles. The
Program command A0his writtento any Address the first cycle and the second write cycle latch- the Addresson the falling edgeofWorE and
the Datatobe writtenon the rising edge and starts
the P/E.C. Read operations within the same bank
output the Status Register bits after the program-
ming has started. Memory programmingis made
onlyby writing'0'in placeof '1'. Status bits DQ6
and DQ7 determineif programmingis on-going
and DQ5 allows verificationof any possible error.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0his
writtento address 555hon the third cycle after two
Coded Cycles.A fourth write operation latches the
Address and the Datato be written and starts the
P/E.C. Read operations within the same bank out-
put the Status Register bits after the programming
has started. Memory programmingis made only writing'0'in placeof '1'. Status bits DQ6 and
DQ7 determineif programmingis on-going and
DQ5 allows verificationof any possible error. Pro-
gramming at an address notin blocks being
erasedis also possible during erase suspend.
Double Word Program (DPG) Instruction. This
featureis offeredto improve the programming
throughput, writinga pageof two adjacent words parallel. High voltage (11.4Vto 12.6V)on VPP
pinis required. This instruction uses five write cy-
cles. The double word program command 40his
writtento address 555hon the third cycle after two
Coded Cycles.A fourth write cycle latches the ad-
dress and datatobe writtento the first location.A
fifth write cycle latches the new datato be written the second location and starts the P/E.C.. Note
that the two locations must have the same address
except for the addressbit A0. The Double Word
Program canbe executedin Bypass mode (DPG-
BY)to skip the two coded cyclesat the beginning each command.
9/38
M59DR008E, M59DR008F
Block Protect (BP), Block Unprotect (BU),
Block Lock (BL) Instructions. All blocks are
protectedat power-up. Each blockof the array has
two levelsof protection against programor erase
operation. The first levelis setby the Block Protect
instruction;a protected block cannot be pro-
grammedor erased untila Block Unprotect in-
structionis given for that block.A second levelof
protectionis setby the Block Lock instruction, and
requires the useof the WP pin, accordingto the
following scheme: when WPisat VIH, the Lock statusis overridden
andall blocks canbe protectedor unprotected; when WPisat VIL, Lock statusis enabled; the
locked blocks are protected, regardlessof their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status, and pro-
gramor erase accordingly; the lock statusis clearedforall blocksat power
up; oncea block has been locked state canbe
cleared only witha reset command. The protec-
tion and lock status canbe monitored for each
block using the Autoselect (AS) instruction. Pro-
tected blocks will outputa‘1’on DQ0 and locked
blocks will outputa‘1’on DQ1.
Referto Table13fora listof the protection states.
Block Erase (BE) Instruction. This instruction
usesa minimumof six write cycles. The Erase
Set-up command 80his writtento address 555h third cycle after the two Coded cycles. The
Block Erase Confirm command 30his similarly
writtenon the sixth cycle after another two Coded
cycles and an address within the blockto be
erasedis given and latched into the memory.
Table 13. Protection States(1)Note:1.All blocksare protectedat power-up,sothe default configurationis001or 101 accordingtoWP status. Current state and Next state givesthe protection statusofa block. The protection statusis definedbythe write protectpinandby
DQ1(=1foralockedblock)and DQ0(=1foraprotectedblock)as readinthe Autoselect instruction withA1=VIH andA0=VIL. Nextstateistheprotection statusofa block after aProtector Unprotect orLock commandhas been issuedor afterWP haschanged
its logic value.AWP transitiontoVIHona locked blockwill restorethe previous DQ0 value, givinga111or 110.
Additional block Erase Confirm commands and
block addresses can be written subsequentlyto
erase other blocksin parallel, without further Cod- cycles. All blocks must belongto the same
bankof memory;ifa new block belongingto the
other bankis given, the operationis aborted. The
erase will start after an erase timeout periodof
100μs. Thus, additional Erase Confirm commands
for other blocks must be given within this delay.
The inputofa new Erase Confirm command will
restart the timeout period. The statusof the inter-
nal timer can be monitored through the levelof
DQ3,if DQ3is'0' the Block Erase Command has
been given and the timeoutis running,if DQ3is'1',
the timeout has expired and the P/E.C.is erasing
the Block(s).If the second command givenis not erase confirmorif the Coded cycles are wrong,
the instruction aborts, and the deviceis resetto
Read Array.Itis not necessaryto program the
block with 00has the P/E.C. willdo this automati-
cally before erasingto FFh. Read operations with- the same bank, after the sixth rising edgeofWE, output the status register bits.
During the executionof the eraseby the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction; the Read/Reset RD instructionis ac-
cepted during the 100μs time-out period. Data
Polling bit DQ7 returns'0' while the erasureisin
progress and'1' whenit has completed. The Tog-
gle bit DQ6 toggles during the erase operation,
and stops when eraseis completed.
After completion the Status Register bit DQ5 re-
turns'1'if there has beenan erase failure.In such situation, the Togglebit DQ2 canbe usedto de-
termine which blockis not correctly erased.In the
caseof erase failure,a Read/Reset RD instruction necessaryin orderto reset the P/E.C.
M59DR008E, M59DR008F10/38
Bank Erase (BKE) Instruction. This instruction
uses six write cycles andis usedto eraseall the
blocks belongingto the selected bank. The Erase
Set-up command 80his writtento address 555h the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10his similarly
writtenon the sixth cycle after another two Coded
cyclesat an address within the selected bank.If
the second command givenis notan erase con-
firmorif the Coded cycles are wrong, the instruc-
tion aborts and the deviceis resetto Read Array.is not necessaryto program the array with 00h
firstas the P/E.C. will automaticallydo this before
erasingitto FFh. Read operations within the same
bank after the sixth rising edgeofWorE output
the Status Register bits. During the executionof
the eraseby the P/E.C., Data Pollingbit DQ7 re-
turns '0', then'1' on completion. The Toggle bit
DQ6 toggles during erase operation and stops
when eraseis completed. After completion the
Status Register bit DQ5 returns'1'if there has
beenan Erase Failure.
Erase Suspend (ES) Instruction.Ina dual bank
memory the Erase Suspend instructionis usedto
read data within the bank where eraseisin
progress.Itis also possibleto program datain
blocks not being erased.
The Erase Suspend instruction consistsof writing
the command B0h without any specific address. Coded Cycles are required. Erase suspendis
accepted only during the Block Erase instruction
execution. The Toggle bit DQ6 stops toggling
when the P/E.C.is suspended within 15μs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be setto
Read Memory Array mode. When eraseis sus-
pended,a Read from blocks being erased will out-
put DQ2 toggling and DQ6at '1'.A Read froma
block not being erased returns valid data. During
suspension the memory will respond onlyto the
Erase Resume ER and the Program PG instruc-
tions.A Program operation canbe initiated during
erase suspendin oneof the blocks not being
erased.It will resultin DQ6 toggling when the data being programmed.
Erase Resume (ER) Instruction.If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h,atan address within the bank be-
ing erased and without any Coded Cycle.
11/38
M59DR008E, M59DR008F
Table 14. Instructions (1,2)
M59DR008E, M59DR008F12/38
Note:1. Commandsnot interpretedinthis tablewill defaultto read array mode. For Coded cycles address inputs A11-A20are don't care.X= Don't Care. The first cyclesoftheRDorAS instructionsare followedby read operations. Any numberof read cycles can occur afterthe com-
mand cycles. During Erase Suspend, Read and Data Program functionsare allowedin blocksnot being erased. Program Address1 and ProgramAddress2 mustbe consecutive addresses differing onlyfor addressbitA0. High voltageon VPP (11.4Vto 12.6V)is requiredforthe proper executionofthe Double Word Program instruction.
13/38
M59DR008E, M59DR008F
Table 15. Status Register Bits(1)Note:1. Logic level'1'is High,'0'is Low. -0-1-0-0-0-1-1-1-0- representbit valuein successive Read operations.In caseof double word program DQ7referstothelast word input.
M59DR008E, M59DR008F14/38
STATUS REGISTER BITSP/E.C. statusis indicated during executionby Data
Pollingon DQ7, detectionof Toggleon DQ6 and
DQ2,or Erroron DQ5 bits. Any read attempt within
the Bank being modified and during Programor
Erase command execution will automatically out-
put these five Status Register bits. The P/E.C. au-
tomatically sets bits DQ2, DQ5, DQ6 and DQ7.
Other bits (DQ0, DQ1 and DQ4) are reserved for
future use and shouldbe masked (see Tables15
and 16). Read attemps within the bank not being
modified will output array data.
Data Polling Bit (DQ7). When Programming op-
erations arein progress, thisbit outputs the com-
plementof thebit being programmed on DQ7.In
caseofa double word program operation, the
complementis doneon DQ7of the last word writ-
tento the command interface, i.e. the data written the fifth cycle. During Erase operation,it outputs '0'. After completionof the operation, DQ7 will
output thebit last programmedora'1' after eras-
ing. Data Pollingis valid and only effective during
P/E.C. operation, thatis after the fourthW pulse
for programmingor after the sixthW pulse for
erase.It mustbe performedat the address being
programmedoratan address within the block be-
ing erased. See Figure 13 for the Data Polling
flowchart and Figure11for the Data Polling wave-
forms. DQ7 will also flag the Erase Suspend mode switching from'0'to'1'at the startof the Erase
Suspend.In orderto monitor DQ7in the Erase
Suspend mode an address withina block being
erased mustbe provided. Fora Read Operationin
Suspend mode, DQ7 will output'1'if the readisat-
temptedona block being erased and the data val- on other blocks. During Program operationin
Erase Suspend Mode, DQ7 will have the same be-
haviour asin the normal program execution out-
sideof the suspend mode.
Toggle Bit (DQ6). When Programmingor Eras-
ing operations arein progress, successive at-
temptsto read DQ6 will output complementary
data. DQ6 will toggle following togglingof eitherG,E whenGisat VIL. The operationis completed
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammedora'1' after erasing. The togglebit DQ6 valid only during P/E.C. operations, thatis after
the fourthW pulse for programmingor after the
sixthW pulse for Erase. DQ6 will be setto'1'ifa
Read operationis attemptedonan Erase Suspend
block. When eraseis suspended DQ6 will toggle
during programming operationsina block different
from the blockin Erase Suspend. EitherEorG
toggling will cause DQ6to toggle. See Figure14
for Toggle Bit flowchart and Figure12 for Toggle
Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, canbe usedto determine the device status
during the Erase operations. During Erase Sus-
penda read froma block being erased will cause
DQ2to toggle.A read froma block not being
erased will output data. DQ2 willbe setto'1' during
program operation andto‘0’in Erase operation.
After erase completion andif the errorbit DQ5is
setto '1', DQ2 will toggleif the faulty blockis ad-
dressed.
Error Bit (DQ5). Thisbitis setto'1'by the P/E.C.
when thereisa failureof programmingor block
erase, that resultsin invalid datain the memory
block.In caseof an errorin block eraseor pro-
gram, the blockin which the error occurredorto
which the programmed data belongs, mustbe dis-
carded. Other Blocks may stillbe used. The error
bit resets aftera Read/Reset (RD) instruction.In
caseof successof Programor Erase, the errorbit
willbe setto'0'.
Erase Timer Bit (DQ3). Thisbitis setto‘0’by the
P/E.C. when the last block Erase command has
been enteredto the Command Interface anditis
awaiting the Erase start. When the erase timeout
periodis finished, DQ3 returnsto ‘1’,in the range 80μsto 120μs.
Table 16. Polling and Toggle Bits
15/38
M59DR008E, M59DR008F
Table 17. Program, Erase Times and Program, Erase Endurance Cycles(TA=0to 70°C; VDD =VDDQ= 1.65Vto 2.2V, VPP =VDD unless otherwise specified)
Note:1. Max values refertothe maximum time allowedbythe internal algorithm before errorbitis set. Worst case conditions programor
erase should perform significantly better. Excludesthe time neededto executethe sequencefor program instruction. Same timing valueif VPP =12V.
POWER CONSUMPTION
Power DownThe memory provides Reset/Power Down control
input RP. The Power Down function can be acti-
vated onlyif the relevant Configuration Registerbit setto '1'.In this case, when the RP signalis
pulledat VSS the supply current dropsto typically
ICC2 (see Table 22), the memoryis deselected and
the outputs arein high impedance.If RPis pulled VSS duringa Programor Erase operation, this
operationis abortedin tPLQ7V and the memory
contentisno longer valid (see Reset/Power Down
input description).
Power UpThe memory Command Interfaceis reseton Pow- Upto Read Array. EitherEorW mustbe tiedto
VIH during Power Upto allow maximum security
and the possibilityto writea commandon the first
rising edgeof W.
Supply RailsNormal precautions mustbe taken for supply volt-
age decoupling; each deviceina system should
have the VDD rails decoupled witha 0.1μF capac-
itor closetothe VDD,VDDQ and VSS pins. The PCB
trace widths should be sufficientto carry the re-
quired VDD program and erase currents.
M59DR008E, M59DR008F16/38
Table 18. Query Structure OverviewNote: The Flash memory displaytheCFI data structure whenCFI Query commandis issued.Inthis tableare listedthe main sub-sections
detailledin Tables19,20 and21. Query dataare always presentedonthe lowest order data outputs.
Table 19. CFI Query Identification StringNote: Query dataare always presentedonthe lowest- order data outputs (DQ7-DQ0) only. DQ8-DQ15are‘0’.
COMMON FLASH INTERFACE (CFI)The Common Flash Interface (CFI) specificationis JEDEC approved, standardised data structure
that can be read from the Flash memory device.
CFI allowsa system softwareto query the flash
deviceto determine various electrical and timing
parameters, density information and functions
supportedby the device. CFI allows the systemto
easily interfaceto the Flash memory,to learn
aboutits features and parameters, enabling the
softwareto configure itself when necessary.
Tables 18, 19,20 and21 show the address used retrieve each data.
The CFI data structure gives information on the
device, such as the sectorization, the command
set and some electrical specifications. Tables 18,
19,20 and21 show the addresses usedto retrieve
each data. The CFI data structure contains alsoa
security area;in this section,a64bit unique secu-
rity numberis written, startingat address 81h. This
area canbe accessed onlyin read mode and there
areno waysof changing the code afterit has been
writtenby ST. Writea read instructionto returnto
Read mode. Referto the CFI Query instructionto
understand how the M59DR008 enters the CFI
Query mode.
17/38
M59DR008E, M59DR008F
Table 20. CFI Query System Interface Information
M59DR008E, M59DR008F18/38
Table 21. Device Geometry Definition
19/38
M59DR008E, M59DR008F
Table 23. Capacitance(1)(TA =25°C,f= 1MHz)
Note:1. Sampled only,not 100% tested.
Table 22. AC Measurement Conditions
