M58WR032FB60ZB6 ,32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash MemoryLogic Diagram . . 8Table 1. Signal Names . . 8Figure 3. VFBGA Connections (Top view t ..
M58WR032FB60ZB6 ,32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash MemoryFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Package–V = 1.7V to 2V for Program, Erase and DDRead–V = ..
M58WR032KU70ZA6U , 16-, 32- and 64-Mbit (x 16, Mux I/O, Multiple Bank, Burst) 1.8 V supply Flash memories
M58WR032QT70ZB6F , 16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories
M58WR064 ,64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash MemoryLogic Diagram . . 7Table 1. Signal Names . . . 7Figure 3. VFBGA Connections (Top view ..
M58WR064 ,64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash MemoryFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Package–V = 1.65V to 2.2V for Program, Erase and DDRead– ..
M95640-MN3 ,64/32/16/8 KBIT SERIAL SPI EEPROM WITH HIGH SPEED CLOCK AND POSITIVE CLOCK STROBEFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95640-WDL6T ,64KBIT AND 32KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES . . . . 9Power-up . . . . . 9Power On Reset: VCC Lock-Out Write Protect ..
M95640-WDW6P ,32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed ClockLogic Diagram . . 5Figure 3. DIP and SO Connections . . 5Figure 4. TSSOP14 Connections ..
M95640-WDW6T ,32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed ClockAbsolute Maximum Ratings . . . . . . . 22DC AND AC PARAMETERS . 23Table 10. Operating Con ..
M95640-WDW6TG ,32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed ClockBlock Diagram . 12INSTRUCTIONS . . 13Table 6. Instruction Set . 13Write Enabl ..
M95640-WDW6TP ,64Kbit and 32Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES . . . . 9Power-Up . . . . . 9 . . . . . . 9Power On Reset: VCC Lock ..
M58WR032FB60ZB6
32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
1/86November 2004
M58WR032FT
M58WR032FB32 Mbit (2Mb x16, Multiple Bank, Burst)
1.8V Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VDD = 1.7V to 2V for Program, Erase and
Read
–VDDQ = 1.7V to 2.24V for I/O Buffers
–VPP = 12V for fast Program (optional) SYNCHRONOUS / ASYNCHRONOUS READ Synchronous Burst Read mode: 66MHz Asynchronous/ Synchronous Page Read
mode Random Access: 60ns, 70ns, 80ns SYNCHRONOUS BURST READ SUSPEND PROGRAMMING TIME 8µs by Word typical for Fast Factory
Program Double/Quadruple Word Program option Enhanced Factory Program options MEMORY BLOCKS Multiple Bank Memory Array: 4 Mbit
Banks Parameter Blocks (Top or Bottom
location) DUAL OPERATIONS Program Erase in one Bank while Read in
others No delay between Read and Write
operations BLOCK LOCKING All blocks locked at Power up Any combination of blocks can be locked
–WP for Block Lock-Down SECURITY 128 bit user programmable OTP cells 64 bit unique device number COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per
BLOCK
M58WR032FT, M58WR032FB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3. VFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3/86
M58WR032FT, M58WR032FB
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Quadruple Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 7. Factory Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
M58WR032FT, M58WR032FB
Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Burst length Bits (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 9. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 11. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 13. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Table 14. Program/Erase Times and Endurance Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 17. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 18. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 19. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 10.Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 11.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 20. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5/86
M58WR032FT, M58WR032FBFigure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 13.Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 14.Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 15.Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 21. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 16.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 22. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 17.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 23. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 18.Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54Figure 19.VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline . . .54
Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data . . . . . .54
Figure 20.VFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . .55
Figure 21.VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . .56
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58Table 28. Top Boot Block Addresses, M58WR032FT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 29. Bottom Boot Block Addresses, M58WR032FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 31. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 35. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 36. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 37. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 38. Bank and Erase Block Region 1 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 39. Bank and Erase Block Region 2 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 23.Double Word Program Flowchart and Pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 24.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 25.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .72
Figure 26.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 27.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . .74
M58WR032FT, M58WR032FBFigure 28.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 29.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . .76
Figure 30.Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78Figure 31.Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Quadruple Enhanced Factory Program Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Table 40. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 41. Command Interface States - Modify Table, Next Output. . . . . . . . . . . . . . . . . . . . . . . . .82
Table 42. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 43. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . .84
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85Table 44. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7/86
M58WR032FT, M58WR032FB
SUMMARY DESCRIPTIONThe M58WR032FT/B is a 32 Mbit (2 Mbit x16)
non-volatile Flash memory that may be erased
electrically at block level and programmed in-sys-
tem on a Word-by-Word basis using a 1.7V to 2V
VDD supply for the circuitry and a 1.7V to 2.24V
VDDQ supply for the Input/Output pins. An optional
12V VPP power supply is provided to speed up
customer programming.
The VPP pin can also be used as a control pin to
provide absolute protection against program or
erase.
The device features an asymmetrical block archi-
tecture. M58WR032FT/B has an array of 71
blocks, and is divided into 4 Mbit banks. There are
7 banks each containing 8 main blocks of 32
KWords, and one parameter bank containing 8 pa-
rameter blocks of 4 KWords and 7 main blocks of
32 KWords. The Multiple Bank Architecture allows
Dual Operations, while programming or erasing in
one bank, Read operations are possible in other
banks. Only one bank at a time is allowed to be in
Program or Erase mode. It is possible to perform
burst reads that cross bank boundaries. The bank
architecture is summarized in Table 2., and the
memory maps are shown in Figure 4. The Param-
eter Blocks are located at the top of the memory
address space for the M58WR032FT and at the
bottom for the M58WR032FB.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage VDD. There are two Enhanced Factory
programming commands available to speed up
programming.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In synchronous burst mode,
data is output on each clock cycle at frequencies
of up to 66MHz. The synchronous burst read oper-
ation can be suspended and resumed.
The device features an Automatic Standby mode.
When the bus is inactive during Asynchronous
Read operations, the device automatically switch-
es to the Automatic Standby mode. In this condi-
tion the power consumption is reduced to the
standby value IDD4 and the outputs are still driven.
The M58WR032FT/B features an instant, individu-
al block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at Power-
Up.
The device includes a Protection Register to in-
crease the protection of a system’s design. The
Protection Register is divided into two segments:
a 64 bit segment containing a unique device num-
ber written by ST, and a 128 bit segment One-
Time-Programmable (OTP) by the user. The user
programmable segment can be permanently pro-
tected. Figure 5. shows the Protection Register
Memory Map.
The memory is offered in a VFBGA56, 7.7 x 9mm,
8x7 active ball array, 0.75 mm pitch package.
In addition to the standard version, the package is
also available in Lead-free version, in compliance
with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages
are compliant with Lead-free soldering processes.
The memory is supplied with all the bits erased
(set to ’1’).
M58WR032FT, M58WR032FB Table 1. Signal Names
9/86
M58WR032FT, M58WR032FB
M58WR032FT, M58WR032FB
11/86
M58WR032FT, M58WR032FB
SIGNAL DESCRIPTIONSSee Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Bus Write
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable or Write Enable
whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the Lock-
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or un-
locked. (refer to Table 13., Lock Status).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at VIL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is re-
duced to the Reset Supply Current IDD2. Refer to
Table 18., DC Characteristics - Currents, for the
value of IDD2. After Reset all blocks are in the
Locked state and the Configuration Register is re-
set. When Reset is at VIH, the device is in normal
operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 19., DC Characteristics - Voltages).
Latch Enable (L). Latch Enable latches the ad-
dress bits on its rising edge. The address
latch is transparent when Latch Enable is at
VIL and it is inhibited when Latch Enable is at
VIH. Latch Enable can be kept Low (also at
board level) when the Latch Enable function
is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at VIL. Clock is
don't care during asynchronous read and in write
operations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable is at VIH or Reset is at VIL.
It can be configured to be active during the wait cy-
cle or one clock cycle in advance. The WAIT signal
is not gated by Output Enable.
VDD Supply Voltage . VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is a power
supply pin. The Supply Voltage VDD and the Pro-
gram Supply Voltage VPP can be applied in any or-
der. The pin can also be used as a control input.
The two functions are selected by the voltage
range applied to the pin. If VPP is kept in a low volt-
age range (0V to VDDQ) VPP is seen as a control
input. In this case a voltage lower than VPPLK
gives an absolute protection against program or
erase, while VPP > VPP1 enables these functions
(see Tables 18 and 19, DC Characteristics for the
relevant values). VPP is only sampled at the begin-
ning of a program or erase; a change in its value
after the operation has started does not have any
effect and program or erase operations continue.
If VPP is in the range of VPPH it acts as a power
supply pin. In this condition VPP must be stable un-
til the Program/Erase algorithm is completed.
VSS Ground. VSS ground is the reference for the
core supply. It must be connected to the system
ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS.
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1µF ce-
ramic capacitor close to the pin (high frequen-
cy, inherently low inductance capacitors
M58WR032FT, M58WR032FB
should be as close as possible to the pack-
age). See Figure 9., AC Measurement Load Cir-
cuit. The PCB track widths should be sufficient
to carry the required VPP program and erase
currents.
BUS OPERATIONSThere are six standard bus operations that control
the device. These are Bus Read, Bus Write, Ad-
dress Latch, Output Disable, Standby and Reset.
See Table 3., Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see COMMAND INTERFACE sec-
tion). See Figures 10, 11, 12 and 13 Read AC
Waveforms, and Tables 20 and 21 Read AC Char-
acteristics, for details of when the output becomes
valid.
Bus Write. Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at VIL with
Output Enable at VIH. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the
bus write operation.
See Figures 16 and 17, Write AC Waveforms, and
Tables 22 and 23, Write AC Characteristics, for
details of the timing requirements.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at VIL during address latch opera-
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high imped-
ance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable and Reset are at VIH. The pow-
er consumption is reduced to the stand-by level
and the outputs are set to high impedance, inde-
pendently from the Output Enable or Write Enable
inputs. If Chip Enable switches to VIH during a pro-
gram or erase operation, the device enters Stand-
by mode when finished.
Reset. During Reset mode the memory is dese-
lected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL.
The power consumption is reduced to the Standby
level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to
VSS during a Program or Erase, this operation is
aborted and the memory content is no longer valid.
Table 3. Bus Operations Note:1. X = Don't care. L can be tied to VIH if the valid address has been previously latched. Depends on G. WAIT signal polarity is configured using the Set Configuration Register command.
13/86
M58WR032FT, M58WR032FB
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
The Command Interface is reset to read mode
when power is first applied, when exiting from Re-
set or whenever VDD is lower than VLKO. Com-
mand sequences must be followed exactly. Any
invalid combination of commands will be ignored.
Refer to Table 4., Command Codes, and APPEN-
DIX D., Tables 40, 41, 42 and 43, Command Inter-
face States - Modify and Lock Tables, for a
summary of the Command Interface.
The Command Interface is split into two types of
commands: Standard commands and Factory
Program commands. The following sections ex-
plain in detail how to perform each command.
Table 4. Command Codes
M58WR032FT, M58WR032FB
COMMAND INTERFACE - STANDARD COMMANDSThe following commands are the basic commands
used to read, write to and configure the device.
Refer to Table 5., Standard Commands, in con-
junction with the following text descriptions.
Read Array CommandThe Read Array command returns the addressed
bank to Read Array mode. One Bus Write cycle is
required to issue the Read Array command and re-
turn the addressed bank to Read Array mode.
Subsequent read operations will read the ad-
dressed location and output the data. A Read Ar-
ray command can be issued in one bank while
programming or erasing in another bank. However
if a Read Array command is issued to a bank cur-
rently executing a Program or Erase operation the
command will be executed but the output data is
not guaranteed.
Read Status Register CommandThe Status Register indicates when a Program or
Erase operation is complete and the success or
failure of operation itself. Issue a Read Status
Register command to read the Status Register
content. The Read Status Register command can
be issued at any time, even during Program or
Erase operations.
The following read operations output the content
of the Status Register of the addressed bank. The
Status Register is latched on the falling edge of E
or G signals, and can be read until E or G returns
to VIH. Either E or G must be toggled to update the
latched data. See Table 8. for the description of
the Status Register Bits. This mode supports
asynchronous or single synchronous reads only.
Read Electronic Signature Command The Read Electronic Signature command reads
the Manufacturer and Device Codes, the Block
Locking Status, the Protection Register, and the
Configuration Register.
The Read Electronic Signature command consists
of one write cycle to an address within one of the
banks. A subsequent Read operation in the same
bank will output the Manufacturer Code, the De-
vice Code, the protection Status of the blocks in
the targeted bank, the Protection Register, or the
Configuration Register (see Table 6.).
If a Read Electronic Signature command is issued
in a bank that is executing a Program or Erase op-
eration the bank will go into Read Electronic Sig-
nature mode, subsequent Bus Read cycles will
output the Electronic Signature data and the Pro-
gram/Erase controller will continue to program or
erase in the background. This mode supports
asynchronous or single synchronous reads only, it
does not support page mode or synchronous burst
reads.
Read CFI Query Command The Read CFI Query command is used to read
data from the Common Flash Interface (CFI). The
Read CFI Query Command consists of one Bus
Write cycle, to an address within one of the banks.
Once the command is issued subsequent Bus
Read operations in the same bank read from the
Common Flash Interface.
If a Read CFI Query command is issued in a bank
that is executing a Program or Erase operation the
bank will go into Read CFI Query mode, subse-
quent Bus Read cycles will output the CFI data
and the Program/Erase controller will continue to
Program or Erase in the background. This mode
supports asynchronous or single synchronous
reads only, it does not support page mode or syn-
chronous burst reads.
The status of the other banks is not affected by the
command (see Table 11.). After issuing a Read
CFI Query command, a Read Array command
should be issued to the addressed bank to return
the bank to Read Array mode.
See APPENDIX B., Common Flash Interface, Ta-
bles 30, 31, 32, 33, 34, 35, 36, 37, 38 and 39 for
details on the information contained in the Com-
mon Flash Interface memory area.
Clear Status Register CommandThe Clear Status Register command can be used
to reset (set to ‘0’) error bits SR1, SR3, SR4 and
SR5 in the Status Register. One bus write cycle is
required to issue the Clear Status Register com-
mand. The Clear Status Register command does
not change the Read mode of the bank.
The error bits in the Status Register do not auto-
matically return to ‘0’ when a new command is is-
sued. The error bits in the Status Register should
be cleared before attempting a new Program or
Erase command.
Block Erase CommandThe Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error. The Block
Erase command can be issued at any moment, re-
gardless of whether the block has been pro-
grammed or not.
Two Bus Write cycles are required to issue the
command. The first bus cycle sets up the Erase
command. The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
15/86
M58WR032FT, M58WR032FBIf the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits SR4 and SR5 are set
and the command aborts. Erase aborts if Reset
turns to VIL. As data integrity cannot be guaran-
teed when the Erase operation is aborted, the
block must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode un-
til a Read Array, Read CFI Query or Read Elec-
tronic Signature command is issued.
During Erase operations the bank containing the
block being erased will only accept the Read Ar-
ray, Read Status Register, Read Electronic Signa-
ture, Read CFI Query and the Program/Erase
Suspend command, all other commands will be ig-
nored. Refer to DUAL OPERATIONS AND MUL-
TIPLE BANK ARCHITECTURE section for
detailed information about simultaneous opera-
tions allowed in banks not being erased. Typical
Erase times are given in Table 14., Program/Erase
Times and Endurance Cycles.
See APPENDIX C., Figure 26., Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
for using the Block Erase command.
Program CommandThe memory array can be programmed word-by-
word. Only one Word in one bank can be pro-
grammed at any one time. Two bus write cycles
are required to issue the Program Command. The first bus cycle sets up the Program
command. The second latches the Address and the Data
to be written and starts the Program/Erase
Controller.
After programming has started, read operations in
the bank being programmed output the Status
Register content.
During Program operations the bank being pro-
grammed will only accept the Read Array, Read
Status Register, Read Electronic Signature, Read
CFI Query and the Program/Erase Suspend com-
mand. Refer to DUAL OPERATIONS AND MULTI-
PLE BANK ARCHITECTURE section for detailed
information about simultaneous operations al-
lowed in banks not being programmed. Typical
Program times are given in Table 14., Program/
Erase Times and Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the memory location must be
reprogrammed.
See APPENDIX C., Figure 22., Program Flow-
chart and Pseudo Code, for the flowchart for using
the Program command.
Program/Erase Suspend Command The Program/Erase Suspend command is used to
pause a Program or Block Erase operation. A
Bank Erase operation cannot be suspended.
One bus write cycle is required to issue the Pro-
gram/Erase command. Once the Program/Erase
Controller has paused bits SR7, SR6 and/ or SR2
of the Status Register will be set to ‘1’. The com-
mand can be addressed to any bank.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array (cannot read the erase-suspended
block or the program-suspended Word), Read
Status Register, Read Electronic Signature and
Read CFI Query commands. Additionally, if the
suspend operation was Erase then the Clear sta-
tus Register, Program, Block Lock, Block Lock-
Down or Block Unlock commands will also be ac-
cepted. The block being erased may be protected
by issuing the Block Lock, Block Lock-Down or
Protection Register Program commands. Only the
blocks not being erased may be read or pro-
grammed correctly. When the Program/Erase Re-
sume command is issued the operation will
complete. Refer to the DUAL OPERATIONS AND
MULTIPLE BANK ARCHITECTURE section for
detailed information about simultaneous opera-
tions allowed during Program/Erase Suspend.
During a Program/Erase Suspend, the device can
be placed in standby mode by taking Chip Enable
to VIH. Program/Erase is aborted if Reset turns to
VIL.
See APPENDIX C., Figure 25., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 27., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Suspend command.
Program/Erase Resume Command The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend command has paused
it. One Bus Write cycle is required to issue the
command. The command can be written to any
address.
The Program/Erase Resume command does not
change the read mode of the banks. If the sus-
pended bank was in Read Status Register, Read
Electronic signature or Read CFI Query mode the
bank remains in that mode and outputs the corre-
sponding data. If the bank was in Read Array
mode subsequent read operations will output in-
valid data.
If a Program command is issued during a Block
Erase Suspend, then the erase cannot be re-
sumed until the programming operation has com-
pleted. It is possible to accumulate suspend
operations. For example: suspend an erase oper-
M58WR032FT, M58WR032FBation, start a programming operation, suspend the
programming operation then read the array. See
APPENDIX C., Figure 25., Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
27., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Resume command.
Protection Register Program CommandThe Protection Register Program command is
used to Program the 128 bit user One-Time-Pro-
grammable (OTP) segment of the Protection Reg-
ister and the Protection Register Lock. The
segment is programmed 16 bits at a time. When
shipped all bits in the segment are set to ‘1’. The
user can only program the bits to ‘0’.
Two write cycles are required to issue the Protec-
tion Register Program command. The first bus cycle sets up the Protection
Register Program command. The second latches the Address and the Data
to be written to the Protection Register and
starts the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register (see Figure 5.,
Protection Register Memory Map). Attempting to
program a previously protected Protection Regis-
ter will result in a Status Register error. The pro-
tection of the Protection Register is not reversible.
The Protection Register Program cannot be sus-
pended. See APPENDIX C., Figure 29., Protec-
tion Register Program Flowchart and Pseudo
Code, for a flowchart for using the Protection Reg-
ister Program command.
Set Configuration Register CommandThe Set Configuration Register command is used
to write a new value to the Configuration Register
which defines the burst length, type, X latency,
Synchronous/Asynchronous Read mode and the
valid Clock edge configuration.
Two Bus Write cycles are required to issue the Set
Configuration Register command. The first cycle writes the setup command and
the address corresponding to the
Configuration Register content. The second cycle writes the Configuration
Register data and the confirm command.
Read operations output the memory array content
after the Set Configuration Register command is
issued.
The value for the Configuration Register is always
presented on A0-A15. CR0 is on A0, CR1 on A1,
etc.; the other address bits are ignored.
Block Lock CommandThe Block Lock command is used to lock a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command. The first bus cycle sets up the Block Lock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command. .
Table 13. shows the Lock Status after issuing a
Block Lock command.
The Block Lock bits are volatile, once set they re-
main set until a hardware reset or power-down/
power-up. They are cleared by a Block Unlock
command. Refer to the section, BLOCK LOCK-
ING, for a detailed explanation. See APPENDIX
C., Figure 28., Locking Operations Flowchart and
Pseudo Code, for a flowchart for using the Lock
command.
Block Unlock CommandThe Block Unlock command is used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Write cycles are required to is-
sue the Block Unlock command. The first bus cycle sets up the Block Unlock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 13. shows the protection status after issuing
a Block Unlock command. Refer to the section,
BLOCK LOCKING, for a detailed explanation and
APPENDIX C., Figure 28., Locking Operations
Flowchart and Pseudo Code, for a flowchart for
using the Unlock command.
Block Lock-Down CommandA locked or unlocked block can be locked-down by
issuing the Block Lock-Down command. A locked-
down block cannot be programmed or erased, or
have its protection status changed when WP is
low, VIL. When WP is high, VIH, the Lock-Down
function is disabled and the locked blocks can be
individually unlocked by the Block Unlock com-
mand.
Two Bus Write cycles are required to issue the
Block Lock-Down command. The first bus cycle sets up the Block Lock
command. The second Bus Write cycle latches the block
address.
17/86
M58WR032FT, M58WR032FBThe lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table 13. shows the Lock Status af-
ter issuing a Block Lock-Down command. Refer to
the section, BLOCK LOCKING, for a detailed ex-
planation and APPENDIX C., Figure 28., Locking
Operations Flowchart and Pseudo Code, for a
flowchart for using the Lock-Down command.
Table 5. Standard CommandsNote:1. X = Don't Care, WA=Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature
Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address,
PRD = Protection Register Data, CRD = Configuration Register Data. Must be same bank as in the first cycle. The signature addresses are listed in Table 6. Any address within the bank can be used.
M58WR032FT, M58WR032FB
19/86
M58WR032FT, M58WR032FB
COMMAND INTERFACE - FACTORY PROGRAM COMMANDSThe Factory Program commands are used to
speed up programming. They require VPP to be at
VPPH except for the Bank Erase command which
also operates at VPP = VDD. Refer to Table 7., Fac-
tory Program Commands, in conjunction with the
following text descriptions.
The use of Factory Program commands requires
certain operating conditions. VPP must be set to VPPH (except for Bank
Erase comand), VDD must be within operating range, Ambient temperature, TA must be 25°C ± 5°C, The targeted block must be unlocked.
Bank Erase CommandThe Bank Erase command can be used to erase a
bank. It sets all the bits within the selected bank to
’1’. All previous data in the bank is lost. The Bank
Erase command will ignore any protected blocks
within the bank. If all blocks in the bank are pro-
tected then the Bank Erase operation will abort
and the data in the bank will not be changed. The
Status Register will not output any error.
Bank Erase operations can be performed at both
VPP = VPPH and VPP = VDD.
Two Bus Write cycles are required to issue the
command. The first bus cycle sets up the Bank Erase
command. The second latches the bank address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Bank Erase
Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if
Reset turns to VIL. As data integrity cannot be
guaranteed when the Erase operation is aborted,
the bank must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode un-
til a Read Array, Read CFI Query or Read Elec-
tronic Signature command is issued.
During Bank Erase operations the bank being
erased will only accept the Read Array, Read Sta-
tus Register, Read Electronic Signature and Read
CFI Query command, all other commands will be
ignored.
For optimum performance, Bank Erase com-
mands should be limited to a maximum of 100 Pro-
gram/Erase cycles per Block. After 100 Program/
Erase cycles the internal algorithm will still operate
properly but some degradation in performance
may occur.
Dual Operations are not supported during Bank
Erase operations and the command cannot be
suspended.
Typical Erase times are given in Table 14., Pro-
gram/Erase Times and Endurance Cycles.
Double Word Program CommandThe Double Word Program command improves
the programming throughput by writing a page of
two adjacent words in parallel. The two words
must differ only for the address A0.
Three bus write cycles are necessary to issue the
Double Word Program command. The first bus cycle sets up the Double Word
Program Command. The second bus cycle latches the Address and
the Data of the first word to be written. The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Read operations in the bank being programmed
output the Status Register content after the pro-
gramming has started.
During Double Word Program operations the bank
being programmed will only accept the Read Ar-
ray, Read Status Register, Read Electronic Signa-
ture and Read CFI Query command, all other
commands will be ignored. Dual operations are
not supported during Double Word Program oper-
ations and the command cannot be suspended.
Typical Program times are given in Table 14., Pro-
gram/Erase Times and Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the memory locations must
be reprogrammed.
See APPENDIX C., Figure 23., Double Word Pro-
gram Flowchart and Pseudo code, for the flow-
chart for using the Double Word Program
command.
Quadruple Word Program Command The Quadruple Word Program command im-
proves the programming throughput by writing a
page of four adjacent words in parallel. The four
words must differ only for the addresses A0 and
A1.
Five bus write cycles are necessary to issue the
Quadruple Word Program command. The first bus cycle sets up the Double Word
Program Command. The second bus cycle latches the Address and
the Data of the first word to be written. The third bus cycle latches the Address and
the Data of the second word to be written.
M58WR032FT, M58WR032FB The fourth bus cycle latches the Address and
the Data of the third word to be written. The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations to the bank being programmed
output the Status Register content after the pro-
gramming has started.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the memory locations must
be reprogrammed.
During Quadruple Word Program operations the
bank being programmed will only accept the Read
Array, Read Status Register, Read Electronic Sig-
nature and Read CFI Query command, all other
commands will be ignored.
Dual operations are not supported during Quadru-
ple Word Program operations and the command
cannot be suspended. Typical Program times are
given in Table 14., Program/Erase Times and En-
durance Cycles.
See APPENDIX C., Figure 24., Quadruple Word
Program Flowchart and Pseudo Code, for the
flowchart for using the Quadruple Word Program
command.
Enhanced Factory Program CommandThe Enhanced Factory Program command can be
used to program large streams of data within any
one block. It greatly reduces the total program-
ming time when a large number of Words are writ-
ten to a block at any one time.
Dual operations are not supported during the En-
hanced Factory Program operation and the com-
mand cannot be suspended.
For optimum performance the Enhanced Factory
Program commands should be limited to a maxi-
mum of 10 program/erase cycles per block. If this
limit is exceeded the internal algorithm will contin-
ue to work properly but some degradation in per-
formance is possible. Typical Program times are
given in Table 14.
The Enhanced Factory Program command has
four phases: the Setup Phase, the Program Phase
to program the data to the memory, the Verify
Phase to check that the data has been correctly
programmed and reprogram if necessary and the
Exit Phase. Refer to Table 7., Factory Program
Commands, and Figure 30., Enhanced Factory
Program Flowchart.
Setup Phase. The Enhanced Factory Program
command requires two Bus Write operations to ini-
tiate the command. The first bus cycle sets up the Enhanced
Factory Program command. The second bus cycle confirms the command.
The Status Register P/E.C. Bit SR7 should be
read to check that the P/E.C. is ready. After the
confirm command is issued, read operations
output the Status Register data. The read Status
Register command must not be issued as it will be
interpreted as data to program.
Program Phase. The Program Phase requires
n+1 cycles, where n is the number of Words (refer
to Table 7., Factory Program Commands, and Fig-
ure 30., Enhanced Factory Program Flowchart).
Three successive steps are required to issue and
execute the Program Phase of the command. Use one Bus Write operation to latch the Start
Address and the first Word to be programmed.
The Status Register Bank Write Status bit SR0
should be read to check that the P/E.C. is
ready for the next Word. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address can either remain the Start Address,
in which case the P/E.C. increments the
address location or the address can be
incremented in which case the P/E.C. jumps to
the new address. If any address that is not in
the same block as the Start Address is given
with data FFFFh, the Program Phase
terminates and the Verify Phase begins. The
Status Register bit SR0 should be read
between each Bus Write cycle to check that
the P/E.C. is ready for the next Word. Finally, after all Words have been pro-
grammed, write one Bus Write operation with
data FFFFh to any address outside the block
containing the Start Address, to terminate the
programming phase. If the data is not FFFFh,
the command is ignored.
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data. The Program/Erase Controller
checks the stream of data with the data that was
programmed in the Program Phase and repro-
grams the memory location if necessary.
Three successive steps are required to execute
the Verify Phase of the command. Use one Bus Write operation to latch the Start
Address and the first Word, to be verified. The
Status Register bit SR0 should be read to
check that the Program/Erase Controller is
ready for the next Word. Each subsequent Word to be verified is
latched with a new Bus Write operation. The
Words must be written in the same order as in
the Program Phase. The address can remain
the Start Address or be incremented. If any
address that is not in the same block as the
21/86
M58WR032FT, M58WR032FBStart Address is given with data FFFFh, the
Verify Phase terminates. Status Register bit
SR0 should be read to check that the P/E.C. is
ready for the next Word. Finally, after all Words have been verified,
write one Bus Write operation with data FFFFh
to any address outside the block containing
the Start Address, to terminate the Verify
Phase.
If the Verify Phase is successfully completed the
memory remains in Read Status Register mode. If
the Program/Erase Controller fails to reprogram a
given location, the error will be signaled in the Sta-
tus Register.
Exit Phase. Status Register P/E.C. bit SR7 set to
‘1’ indicates that the device has returned to Read
mode. A full Status Register check should be done
to ensure that the block has been successfully pro-
grammed. See the section on the STATUS REG-
ISTER for more details.
Quadruple Enhanced Factory Program
CommandThe Quadruple Enhanced Factory Program com-
mand can be used to program one or more pages
of four adjacent words in parallel. The four words
must differ only for the addresses A0 and A1.
Dual operations are not supported during Quadru-
ple Enhanced Factory Program operations and
the command cannot be suspended.
The Quadruple Enhanced Factory Program com-
mand has four phases: the Setup Phase, the Load
Phase where the data is loaded into the buffer, the
combined Program and Verify Phase where the
loaded data is programmed to the memory and
then automatically checked and reprogrammed if
necessary and the Exit Phase. Unlike the En-
hanced Factory Program it is not necessary to re-
submit the data for the Verify Phase. The Load
Phase and the Program and Verify Phase can be
repeated to program any number of pages within
the block.
Setup Phase. The Quadruple Enhanced Factory
Program command requires one Bus Write opera-
tion to initiate the load phase. After the setup
command is issued, read operations output the
Status Register data. The Read Status Register
command must not be issued as it will be
interpreted as data to program.
Load Phase. The Load Phase requires 4 cycles
to load the data (refer to Table 7., Factory Program
Commands, and Figure 31., Quadruple Enhanced
Factory Program Flowchart). Once the first Word
of each Page is written it is impossible to exit the
Load phase until all four Words have been written.
Two successive steps are required to issue and
execute the Load Phase of the Quadruple En-
hanced Factory Program command. Use one Bus Write operation to latch the Start
Address and the first Word of the first Page to
be programmed. For subsequent Pages the
first Word address can remain the Start
Address (in which case the next Page is
programmed) or can be any address in the
same block. If any address with data FFFFh is
given that is not in the same block as the Start
Address, the device enters the Exit Phase. For
the first Load Phase Status Register bit SR7
should be read after the first Word has been
issued to check that the command has been
accepted (bit SR7 set to ‘0’). This check is not
required for subsequent Load Phases. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address is only checked for the first Word of
each Page as the order of the Words to be
programmed is fixed.
The memory is now set to enter the Program and
Verify Phase.
Program and Verify Phase. In the Program and
Verify Phase the four Words that were loaded in
the Load Phase are programmed in the memory
array and then verified by the Program/Erase Con-
troller. If any errors are found the Program/Erase
Controller reprograms the location. During this
phase the Status Register shows that the Pro-
gram/Erase Controller is busy, Status Register bit
SR7 set to ‘0’, and that the device is not waiting for
new data, Status Register bit SR0 set to ‘1’. When
Status Register bit SR0 is set to ‘0’ the Program
and Verify phase has terminated.
Once the Verify Phase has successfully complet-
ed subsequent pages in the same block can be
loaded and programmed. The device returns to
the beginning of the Load Phase by issuing one
Bus Write operation to latch the Address and the
first of the four new Words to be programmed.
Exit Phase. Finally, after all the pages have been
programmed, write one Bus Write operation with
data FFFFh to any address outside the block con-
taining the Start Address, to terminate the Load
and Program and Verify Phases.
Status Register bit SR7 set to ‘1’ and bit SR0 set
to ‘0’ indicate that the Quadruple Enhanced Facto-
ry Program command has terminated. A full Status
Register check should be done to ensure that the
block has been successfully programmed. See the
section on the STATUS REGISTER for more de-
tails.
If the Program and Verify Phase has successfully
completed the memory returns to Read mode. If
the P/E.C. fails to program and reprogram a given
location, the error will be signaled in the Status
Register.
M58WR032FT, M58WR032FB
Table 7. Factory Program CommandsNote:1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1. Address can remain Starting Address WA1 or be incremented. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and
check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent
Words in each Page can be written to any address. Any address within the bank can be used. Any address within the block can be used.
23/86
M58WR032FT, M58WR032FB
STATUS REGISTERThe Status Register provides information on the
current or previous Program or Erase operations.
Issue a Read Status Register command to read
the contents of the Status Register, refer to Read
Status Register Command section for more de-
tails. To output the contents, the Status Register is
latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be
read until Chip Enable or Output Enable returns to
VIH. The Status Register can only be read using
single asynchronous or single synchronous reads.
Bus Read operations from any address within the
bank, always read the Status Register during Pro-
gram and Erase operations.
The various bits convey information about the sta-
tus and any errors of the operation. Bits SR7, SR6,
SR2 and SR0 give information on the status of the
device and are set and reset by the device. Bits
SR5, SR4, SR3 and SR1 give information on er-
rors, they are set by the device but must be reset
by issuing a Clear Status Register command or a
hardware reset. If an error bit is set to ‘1’ the Status
Register should be reset before issuing another
command. SR7 to SR1 refer to the status of the
device while SR0 refers to the status of the ad-
dressed bank.
The bits in the Status Register are summarized in
Table 8., Status Register Bits. Refer to Table 8. in
conjunction with the following text descriptions.
Program/Erase Controller Status Bit (SR7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive in any bank. When the Program/Erase
Controller Status bit is Low (set to ‘0’), the Pro-
gram/Erase Controller is active; when the bit is
High (set to ‘1’), the Program/Erase Controller is
inactive, and the device is ready to process a new
command.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg-
ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Lock Status bits should be tested
for errors.
Erase Suspend Status Bit (SR6). The Erase
Suspend Status bit indicates that an Erase opera-
tion has been suspended or is going to be sus-
pended in the addressed block. When the Erase
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
The Erase Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is High (Program/Erase Controller inactive).
SR7 is set within the Erase Suspend Latency time
of the Program/Erase Suspend command being
issued therefore the memory may still complete
the operation rather than entering the Suspend
mode.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status Bit (SR5). The Erase Status bit
can be used to identify if the memory has failed to
verify that the block or bank has erased correctly.
When the Erase Status bit is High (set to ‘1’), the
Program/Erase Controller has applied the maxi-
mum number of pulses to the block or bank and
still failed to verify that it has erased correctly. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status Bit (SR4). The Program Status
bit is used to identify a Program failure or an at-
tempt to program a ‘1’ to an already programmed
bit when VPP = VPPH.
When the Program Status bit is High (set to ‘1’),
the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that it has programmed correctly.
After an attempt to program a '1' to an already pro-
grammed bit, the Program Status bit SR4 only
goes High (set to '1') if VPP = VPPH (if VPP is differ-
ent from VPPH, SR4 remains Low (set to '0') and
the attempt is not shown).
The Program Status bit should be read once the
Program/Erase Controller Status bit is High (Pro-
gram/Erase Controller inactive).
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new command is issued, otherwise the new
command will appear to fail.
VPP Status Bit (SR3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
M58WR032FT, M58WR032FBor Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the volt-
age on the VPP pin was sampled at a valid voltage;
when the VPP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the VPP Lockout
Voltage, VPPLK, the memory is protected and Pro-
gram and Erase operations cannot be performed.
Once set High, the VPP Status bit can only be reset
Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Suspend Status Bit (SR2). The Pro-
gram Suspend Status bit indicates that a Program
operation has been suspended in the addressed
block. When the Program Suspend Status bit is
High (set to ‘1’), a Program/Erase Suspend com-
mand has been issued and the memory is waiting
for a Program/Erase Resume command. The Pro-
gram Suspend Status should only be considered
valid when the Program/Erase Controller Status
bit is High (Program/Erase Controller inactive).
SR2 is set within the Program Suspend Latency
time of the Program/Erase Suspend command be-
ing issued therefore the memory may still com-
plete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status Bit (SR1). The Block
Protection Status bit can be used to identify if a
Program or Block Erase operation has tried to
modify the contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Bank Write/Multiple Word Program Status Bit
(SR0). The Bank Write Status bit indicates wheth-
er the addressed bank is programming or erasing.
In Enhanced Factory Program mode the Multiple
Word Program bit shows if a Word has finished
programming or verifying depending on the phase.
The Bank Write Status bit should only be consid-
ered valid when the Program/Erase Controller Sta-
tus SR7 is Low (set to ‘0’).
When both the Program/Erase Controller Status bit
and the Bank Write Status bit are Low (set to ‘0’),
the addressed bank is executing a Program or
Erase operation. When the Program/Erase Con-
troller Status bit is Low (set to ‘0’) and the Bank
Write Status bit is High (set to ‘1’), a Program or
Erase operation is being executed in a bank other
than the one being addressed.
In Enhanced Factory Program mode if Multiple
Word Program Status bit is Low (set to ‘0’), the de-
vice is ready for the next Word, if the Multiple Word
Program Status bit is High (set to ‘1’) the device is
not ready for the next Word.
Note: Refer to APPENDIX C., FLOWCHARTS
AND PSEUDO CODES, for using the Status Reg-
ister.
25/86
M58WR032FT, M58WR032FB
Table 8. Status Register BitsNote: Logic level '1' is High, '0' is Low.
M58WR032FT, M58WR032FB
CONFIGURATION REGISTERThe Configuration Register is used to configure
the type of bus access that the memory will per-
form. Refer to READ MODES section for details
on read operations.
The Configuration Register is set through the
Command Interface. After a Reset or Power-Up
the device is configured for asynchronous page
read (CR15 = 1). The Configuration Register bits
are described in Table 9. They specify the selec-
tion of the burst length, burst type, burst X latency
and the Read operation. Refer to Figures 6 and 7
for examples of synchronous burst configurations.
Read Select Bit (CR15)The Read Select bit, CR15, is used to switch be-
tween asynchronous and synchronous Bus Read
operations. When the Read Select bit is set to ’1’,
read operations are asynchronous; when the
Read Select bit is set to ’0’, read operations are
synchronous. Synchronous Burst Read is support-
ed in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous access.
X-Latency Bits (CR13-CR11)The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available. For correct operation the
X-Latency bits can only assume the values in Ta-
ble 9., Configuration Register.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters. Two conditions must be satisfied: Depending on whether tAVK_CPU or tDELAY is
supplied either one of the following two
equations must be satisfied:
(n + 1) tK ≥ tACC - tAVK_CPU + tQVK_CPU
(n + 2) tK ≥ tACC + tDELAY + tQVK_CPU and also
tK > tKQV + tQVK_CPU
where
n is the chosen X-Latency configuration code
tK is the clock period
tAVK_CPU is clock to address valid, L Low, or E
Low, whichever occurs last
tDELAY is address valid, L Low, or E Low to clock,
whichever occurs last
tQVK_CPU is the data setup time required by the
system CPU,
tKQV is the clock to data valid time
tACC is the random access time of the device.
Refer to Figure 6., X-Latency and Data Output
Configuration Example.
Wait Polarity Bit (CR10)In synchronous burst mode the Wait signal indi-
cates whether the output data are valid or a WAIT
state must be inserted. The Wait Polarity bit is
used to set the polarity of the Wait signal. When
the Wait Polarity bit is set to ‘0’ the Wait signal is
active Low. When the Wait Polarity bit is set to ‘1’
the Wait signal is active High (default).
Data Output Configuration Bit (CR9)The Data Output Configuration bit determines
whether the output remains valid for one or two
clock cycles. When the Data Output Configuration
Bit is ’0’ the output data is valid for one clock cycle,
when the Data Output Configuration Bit is ’1’ the
output data is valid for two clock cycles.
The Data Output Configuration depends on the
condition: tK > tKQV + tQVK_CPU
where tK is the clock period, tQVK_CPU is the data
setup time required by the system CPU and tKQV
is the clock to data valid time. If this condition is not
satisfied, the Data Output Configuration bit should
be set to ‘1’ (two clock cycles). Refer to Figure 6.,
X-Latency and Data Output Configuration Exam-
ple.
Wait Configuration Bit (CR8)In burst mode the Wait bit controls the timing of the
Wait output pin, WAIT. When WAIT is asserted,
Data is Not Valid and when WAIT is deasserted,
Data is Valid. When the Wait bit is ’0’ the Wait out-
put pin is asserted during the wait state. When the
Wait bit is ’1’ (default) the Wait output pin is assert-
ed one clock cycle before the wait state.
Burst Type Bit (CR7)The Burst Type bit is used to configure the se-
quence of addresses read as sequential or inter-
leaved. When the Burst Type bit is ’0’ the memory
outputs from interleaved addresses; when the
Burst Type bit is ’1’ (default) the memory outputs
from sequential addresses. See Table 10., Burst
Type Definition, for the sequence of addresses
output from a given starting address in each mode.
Valid Clock Edge Bit (CR6)The Valid Clock Edge bit, CR6, is used to config-
ure the active edge of the Clock, K, during Syn-
chronous Burst Read operations. When the Valid
Clock Edge bit is ’0’ the falling edge of the Clock is
the active edge; when the Valid Clock Edge bit is
’1’ the rising edge of the Clock is active.
Wrap Burst Bit (CR3)The burst reads can be confined inside the 4 or 8
Word boundary (wrap) or overcome the boundary
27/86
M58WR032FT, M58WR032FB(no wrap). The Wrap Burst bit is used to select be-
tween wrap and no wrap. When the Wrap Burst bit
is set to ‘0’ the burst read wraps; when it is set to
‘1’ the burst read does not wrap.
Burst length Bits (CR2-CR0)The Burst Length bits set the number of Words to
be output during a Synchronous Burst Read oper-
ation as result of a single address latch cycle.
They can be set for 4 Words, 8 Words, 16 Words
or continuous burst, where all the words are read
sequentially.
In continuous burst mode the burst sequence can
cross bank boundaries.
In continuous burst mode or in 4, 8, 16 Words no-
wrap, depending on the starting address, the de-
vice asserts the WAIT output to indicate that a de-
lay is necessary before the data is output.
If the starting address is aligned to a 4 Word
boundary no wait states are needed and the WAIT
output is not asserted.
If the starting address is shifted by 1,2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 16 Word boundary, to
indicate that the device needs an internal delay to
read the successive words in the array. WAIT will
be asserted only once during a continuous burst
access. See also Table 10., Burst Type Definition.
CR14, CR5 and CR4 are reserved for future use.
Table 9. Configuration Register
M58WR032FT, M58WR032FB
Table 10. Burst Type Definition
29/86
M58WR032FT, M58WR032FB
M58WR032FT, M58WR032FB
31/86
M58WR032FT, M58WR032FB
READ MODESRead operations can be performed in two different
ways depending on the settings in the Configura-
tion Register. If the clock signal is ‘don’t care’ for
the data output, the read operation is Asynchro-
nous; if the data output is synchronized with clock,
the read operation is Synchronous.
The Read mode and data output format are deter-
mined by the Configuration Register. (See CON-
FIGURATION REGISTER section for details). All
banks supports both asynchronous and synchro-
nous read operations. The Multiple Bank architec-
ture allows read operations in one bank, while
write operations are being executed in another
(see Tables 11 and 12).
Asynchronous Read ModeIn Asynchronous Read operations the clock signal
is ‘don’t care’. The device outputs the data corre-
sponding to the address latched, that is the mem-
ory array, Status Register, Common Flash
Interface or Electronic Signature depending on the
command issued. CR15 in the Configuration Reg-
ister must be set to ‘1’ for Asynchronous opera-
tions.
In Asynchronous Read mode a Page of data is in-
ternally read and stored in a Page Buffer. The
Page has a size of 4 Words and is addressed by
A0 and A1 address inputs. The address inputs A0
and A1 are not gated by Latch Enable in Asyn-
chronous Read mode.
The first read operation within the Page has a
longer access time (Tacc, Random access time),
subsequent reads within the same Page have
much shorter access times. If the Page changes
then the normal, longer timings apply again.
Asynchronous Read operations can be performed
in two different ways, Asynchronous Random Ac-
cess Read and Asynchronous Page Read. Only
Asynchronous Page Read takes full advantage of
the internal page storage so different timings are
applied.
During Asynchronous Read operations, after a
bus inactivity of 150ns, the device automatically
switches to the Automatic Standby mode. In this
condition the power consumption is reduced to the
standby value and the outputs are still driven.
In Asynchronous Read mode, the WAIT signal is
always asserted.
See Table 20., Asynchronous Read AC Charac-
teristics, Figure 10., Asynchronous Random Ac-
cess Read AC Waveforms, and Figure 11.,
Asynchronous Page Read AC Waveforms, for de-
tails.
Synchronous Burst Read ModeIn Synchronous Burst Read mode the data is out-
put in bursts synchronized with the clock. It is pos-
sible to perform burst reads across bank
boundaries.
Synchronous Burst Read mode can only be used
to read the memory array. For other read opera-
tions, such as Read Status Register, Read CFI
and Read Electronic Signature, Single Synchro-
nous Read or Asynchronous Random Access
Read must be used.
In Synchronous Burst Read mode the flow of the
data output depends on parameters that are con-
figured in the Configuration Register.
A burst sequence is started at the first clock edge
(rising or falling depending on Valid Clock Edge bit
CR6 in the Configuration Register) after the falling
edge of Latch Enable or Chip Enable, whichever
occurs last. Addresses are internally incremented
and after a delay of 2 to 5 clock cycles (X latency
bits CR13-CR11) the corresponding data are out-
put on each clock cycle.
The number of Words to be output during a Syn-
chronous Burst Read operation can be configured
as 4, 8, 16 Words, or Continuous (Burst Length
bits CR2-CR0). The data can be configured to re-
main valid for one or two clock cycles (Data Output
Configuration bit CR9).
The order of the data output can be modified
through the Burst Type and the Wrap Burst bits in
the Configuration Register. The burst sequence
may be configured to be sequential or interleaved
(CR7). The burst reads can be confined inside the
4, 8 or 16 Word boundary (Wrap) or overcome the
boundary (No Wrap). If the starting address is
aligned to the Burst Length (4, 8 or 16 Words) the
wrapped configuration has no impact on the output
sequence. Interleaved mode is not allowed in Con-
tinuous Burst Read mode or with No Wrap se-
quences.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur. This delay
will depend on the starting address of the burst se-
quence; the worst case delay will occur when the
sequence is crossing a 16 Word boundary and the
starting address was at the end of a four word
boundary.
WAIT is asserted during X latency, the Wait state
and at the end of 4-, 8- or 16-Word burst. It is only
deasserted when output data are valid. In Contin-
uous Burst Read mode a Wait state will occur
when crossing the first 16 Word boundary. If the
burst starting address is aligned to a 4 Word Page,
the Wait state will not occur.
The WAIT signal can be configured to be active
Low or active High (default) by setting CR10 in the
Configuration Register. The WAIT signal is mean-
ingful only in Synchronous Burst Read mode, in
M58WR032FT, M58WR032FBother modes, WAIT is always asserted (except for
Read Array mode).
See Table 21., Synchronous Read AC Character-
istics, and Figure 12., Synchronous Burst Read
AC Waveforms, for details.
Synchronous Burst Read Suspend. A Syn-
chronous Burst Read operation can be suspend-
ed, freeing the data bus for other higher priority
devices. It can be suspended during the initial ac-
cess latency time (before data is output) in which
case the initial latency time can be reduced to ze-
ro, or after the device has output data. When the
Synchronous Burst Read operation is suspended,
internal array sensing continues and any previous-
ly latched internal data is retained. A burst se-
quence can be suspended and resumed as often
as required as long as the operating conditions of
the device are met.
A Synchronous Burst Read operation is suspend-
ed when E is low and the current address has
been latched (on a Latch Enable rising edge or on
a valid clock edge). The clock signal is then halted
at VIH or at VIL, and G goes high.
When G becomes low again and the clock signal
restarts, the Synchronous Burst Read operation is
resumed exactly where it stopped.
WAIT being gated by E remains active and will not
revert to high-impedance when G goes high. So if
two or more devices are connected to the system’s
READY signal, to prevent bus contention the
WAIT signal of the Flash memory should not be di-
rectly connected to the system’s READY signal.
See Table 21., Synchronous Read AC Character-
istics and Figure 14., Synchronous Burst Read
Suspend AC Waveforms, for details.
Single Synchronous Read ModeSingle Synchronous Read operations are similar
to Synchronous Burst Read operations except that
only the first data output after the X latency is valid.
Synchronous Single Reads are used to read the
Electronic Signature, Status Register, CFI, Block
Protection Status, Configuration Register Status
or Protection Register. When the addressed bank
is in Read CFI, Read Status Register or Read
Electronic Signature mode, the WAIT signal is al-
ways asserted.
See Table 21., Synchronous Read AC Character-
istics and Figure 13., Single Synchronous Read
AC Waveforms, for details.
33/86
M58WR032FT, M58WR032FB
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTUREThe Multiple Bank Architecture of the
M58WR032FT/B provides flexibility for software
developers by allowing code and data to be split
with 4Mbit granularity. The Dual Operations fea-
ture simplifies the software management of the de-
vice and allows code to be executed from one
bank while another bank is being programmed or
erased.
The Dual operations feature means that while pro-
gramming or erasing in one bank, Read opera-
tions are possible in another bank with zero
latency (only one bank at a time is allowed to be in
Program or Erase mode). If a Read operation is re-
quired in a bank which is programming or erasing,
the Program or Erase operation can be suspend-
ed. Also if the suspended operation was Erase
then a Program command can be issued to anoth-
er block, so the device can have one block in
Erase Suspend mode, one programming and oth-
er banks in Read mode. Bus Read operations are
allowed in another bank between setup and con-
firm cycles of program or erase operations. The
combination of these features means that read op-
erations are possible at any moment.
Tables 11 and 12 show the dual operations possi-
ble in other banks and in the same bank. For a
complete list of possible commands refer to AP-
PENDIX D., COMMAND INTERFACE STATE TA-
BLES.
Table 11. Dual Operations Allowed In Other Banks
Table 12. Dual Operations Allowed In Same BankNote:1. Not allowed in the Block or Word that is being erased or programmed. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
M58WR032FT, M58WR032FB
BLOCK LOCKINGThe M58WR032FT/B features an instant, individu-
al block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection. Lock/Unlock - this first level allows software-
only control of block locking. Lock-Down - this second level requires
hardware interaction before locking can be
changed. VPP ≤ VPPLK - the third level offers a complete
hardware protection against program and
erase on all blocks.
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 13., de-
fines all of the possible protection states (WP,
DQ1, DQ0), and APPENDIX C., Figure 28., shows
a flowchart for the locking operations.
Reading a Block’s Lock StatusThe lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode write 90h to the device. Subse-
quent reads at the address specified in Table 6.,
will output the protection status of that block. The
lock status is represented by DQ0 and DQ1. DQ0
indicates the Block Lock/Unlock status and is set
by the Lock command and cleared by the Unlock
command. It is also automatically set when enter-
ing Lock-Down. DQ1 indicates the Lock-Down sta-
tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked StateThe default status of all blocks on power-up or af-
ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper-
ations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com-
mands. An Unlocked block can be Locked by issu-
ing the Lock command.
Unlocked StateUnlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be un-
locked by issuing the Unlock command.
Lock-Down StateBlocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can-
not be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked-
Down blocks revert to the Locked state when the
device is reset or powered-down.
The Lock-Down function is dependent on the WP
input pin. When WP=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
WP=1 (VIH) the Lock-Down function is disabled
(1,1,x) and Locked-Down blocks can be individual-
ly unlocked to the (1,1,0) state by issuing the soft-
ware command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WP
remains high. When WP is Low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP was high. Device reset or power-down
resets all blocks, including those in Lock-Down, to
the Locked state.
Locking Operations During Erase SuspendChanges to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operations cannot be performed during a
program suspend. Refer to APPENDIX D., COM-
MAND INTERFACE STATE TABLES, for detailed
information on which commands are valid during
erase suspend.
35/86
M58WR032FT, M58WR032FB
Table 13. Lock Status Note:1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = VIH and A0 = VIL. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
M58WR032FT, M58WR032FB
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLESThe Program and Erase times and the number of
Program/ Erase cycles per block are shown in Ta-
ble 14. Exact erase times may change depending
on the memory array condition. The best case is
when all the bits in the block or bank are at ‘0’ (pre-
programmed). The worst case is when all the bits
in the block or bank are at ‘1’ (not prepro-
grammed). Usually, the system overhead is negli-
gible with respect to the erase time.
In the M58WR032FT/B the maximum number of
Program/ Erase cycles depends on the VPP volt-
age supply used.
Table 14. Program/Erase Times and Endurance Cycles
37/86
M58WR032FT, M58WR032FBNote:1. TA= –40 to 85°C; VDD = 1.7V to 2V; VDDQ = 1.7V to 2.24V. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms). Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). Measurements performed at 25°C. TA = 25°C ±5°C for Quadruple Word, Double Word and Quadruple Enhanced Factory Program.
M58WR032FT, M58WR032FB
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 15. Absolute Maximum RatingsNote:1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
39/86
M58WR032FT, M58WR032FB
DC AND AC PARAMETERSThis section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 16., Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
Table 17. CapacitanceNote: Sampled only, not 100% tested.
M58WR032FT, M58WR032FB
Table 18. DC Characteristics - CurrentsNote:1. Sampled only, not 100% tested. VDD Dual Operation current is the sum of read and program or erase currents.
41/86
M58WR032FT, M58WR032FB
Table 19. DC Characteristics - Voltages
M58WR032FT, M58WR032FB
43/86
M58WR032FT, M58WR032FB
