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M58MR032C100ZC6TN/a2500avai32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory


M58MR032C100ZC6T ,32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash MemoryLogic Diagram– Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS– Read within one Bank wh ..
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M58MR032C100ZC6T
32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
1/52
PRELIMINARY DATA

August 2002
M58MR032C
M58MR032D

32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst)
1.8V Supply Flash Memory SUPPLY VOLTAGE
–VDD = VDDQ = 1.7V to 2.0V for Program,
Erase and Read
–VPP = 12V for fast Program (optional) MULTIPLEXED ADDRESS/DATA SYNCHRONOUS / ASYNCHRONOUS READ Burst mode Read: 40MHz Page mode Read (4 Words Page) Random Access: 100ns PROGRAMMING TIME 10μs by Word typical Two or four words programming option MEMORY BLOCKS Dual Bank Memory Array: 8/24 Mbit Parameter Blocks (Top or Bottom location) DUAL OPERATIONS Read within one Bank while Program or
Erase within the other No delay between Read and Write operations PROTECTION/SECURITY All Blocks protected at Power-up Any combination of Blocks can be protected 64 bit unique device identifier 64 bit user programmable OTP cells One parameter block permanently lockable COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M58MR032C: 88DAh Bottom Device Code, M58MR032D: 88DBh
Figure 1. Logic Diagram
M58MR032C, M58MR032D
Figure 2. TFBGA Connections (Top view through package)
DESCRIPTION

The M58MR032 is a 32 Mbit non-volatile Flash
memory that may be erased electrically at block
level and programmed in-system on a Word-by-
Word basis using a 1.7V to 2.0V VDD supply for the
circuitry. For Program and Erase operations the
necessary high voltages are generated internally.
The device supports synchronous burst read and
asynchronous read from all the blocks of the mem-
ory array; at power-up the device is configured for
page mode read. In synchronous burst mode, a
new data is output at each clock cycle for frequen-
cies up to 40MHz.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against pro-
gramming and erase at Power-up.
Blocks can be unprotected to make changes in the
application and then re-protected.
A parameter block "Security block" can be perma-
nently protected against programming and erasing
in order to increase the data security. An optional
12V VPP power supply is provided to speed up the
program phase at costumer production. An inter-
nal command interface (C.I.) decodes the instruc-
tions to access/modify the memory content. The
program/erase controller (P/E.C.) automatically
executes the algorithms taking care of the timings
necessary for program and erase operations. Two
status registers indicate the state of each bank.
Instructions for Read Array, Read Electronic Sig-
nature, Read Status Register, Clear Status Regis-
ter, Write Read Configuration Register, Program,
Block Erase, Bank Erase, Program Suspend, Pro-
gram Resume, Erase Suspend, Erase Resume,
Block Protect, Block Unprotect, Block Locking,
Protection Program, CFI Query, are written to the
memory through a Command Interface (C.I.) using
standard micro-processor write timings.
The memory is offered in TFBGA48, 0.5 mm ball
pitch packages and it is supplied with all the bits
erased (set to ’1’).
3/52
M58MR032C, M58MR032D
Table 1. Signal Names
Organization

The M58MR032 is organized as 2Mb by 16 bits.
The first sixteen address lines are multiplexed with
the Data Input/Output signals on the multiplexed
address/data bus ADQ0-ADQ15. The remaining
address lines A16-A20 are the MSB addresses.
Chip Enable E, Output Enable G and Write Enable
W inputs provide memory control.
The clock K input synchronizes the memory to the
microprocessor during burst read.
Reset RP is used to reset all the memory circuitry
and to set the chip in power-down mode if a proper
setting of the Read Configuration Register en-
ables this function.
WAIT output indicates to the microprocessor the
status of the memory during the burst mode oper-
ations.
Memory Blocks

The device features asymmetrically blocked archi-
tecture. M58MR032 has an array of 71 blocks and
is divided into two banks A and B, providing Dual
Bank operations. While programming or erasing in
Bank A, read operations are possible into Bank B
or vice versa. Only one bank at the time is allowed
to be in program or erase mode. It is possible to
perform burst reads that cross bank boundaries.
The memory features an erase suspend allowing
reading or programming in another block. Once
suspended the erase can be resumed. Program
can be suspended to read data in another block
and then resumed. The Bank Size and sectoriza-
tion are summarized in Table 3. Parameter Blocks
are located at the top of the memory address
space for the M58MR032C, and at the bottom for
the M58MR032D. The memory maps are shown in
Figure 3.
Table 2. Absolute Maximum Ratings (1)

Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Depends on range. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
M58MR032C, M58MR032D
The architecture includes a 128 bits Protection
register that is divided into two 64-bits segments.
In the first one is written a unique device number,
while the second one is programmable by the us-
er. The user programmable segment can be per-
manently protected programming the bit 1 of the
Protection Lock Register (see protection register
and Security Block). The parameter block (# 0) is
a security block. It can be permanently protected
by the user programming the bit 2 of the Protection
Lock Register.
Block protection against Program or Erase pro-
vides additional data security. All blocks are pro-
tected and unlocked at Power-up. Instructions are
provided to protect or un-protect any block in the
application. A second register locks the protection
status while WP is low (see Block Locking descrip-
tion).
Table 3. Bank Size and Sectorization
Figure 3. Memory Map
5/52
M58MR032C, M58MR032D
SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.
Address Inputs or Data Input/Output (ADQ0-
ADQ15).
When Chip Enable E is at VIL and Out-
put Enable G is at VIH the multiplexed address/
data bus is used to input addresses for the memo-
ry array, data to be programmed in the memory ar-
ray or commands to be written to the C.I. The
address inputs for the memory array are latched
on the rising edge of Latch Enable L. The address
latch is transparent when L is at VIL. In synchro-
nous operations the address is also latched on the
first rising/falling edge of K (depending on clock
configuration) when L is low. Both input data and
commands are latched on the rising edge of Write
Enable W. When Chip Enable E and Output En-
able G are at VIL the address/data bus outputs
data from the Memory Array, the Electronic Signa-
ture Manufacturer or Device codes, the Block Pro-
tection status the Read Configuration Register
status, the protection register or the Status Regis-
ter. The address/data bus is high impedance when
the chip is deselected, Output Enable G is at VIH,
or RP is at VIL.
Address Inputs (A16-A20).
The five MSB ad-
dresses of the memory array are latched on the
rising edge of Latch Enable L. In synchronous op-
eration these inputs are also latched on the first
rising/falling edge of K (depending on clock config-
uration) when L is low.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at VIH deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at VIL.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is at VIH the outputs are High im-
pedance.
Write Enable (W).
This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP).
This input gives an addition-
al hardware protection level against program or
erase when pulled at VIL, as described in the Block
Lock instruction description.
Reset/Power-down Input (RP).
The RP input
provides hardware reset of the memory, and/or
Power-down functions, depending on the Read
Configuration Register status. Reset/Power-down
of the memory is achieved by pulling RP to VIL for
at least tPLPH. When the reset pulse is given, the
memory will recover from Power-down (when en-
abled) in a minimum of tPHEL, tPHLL or tPHWL (see
Table 31 and Figure 15) after the rising edge of
RP. Exit from Reset/Power-down changes the
contents of the Read Configuration Register bits
14 and 15, setting the memory in asynchronous
page mode read and power save function dis-
abled. All blocks are protected and unlocked after
a Reset/Power-down.
Latch Enable (L).
L latches the address bits
ADQ0-ADQ15 and A16-A20 on its rising edge.
The address latch is transparent when L is at VIL
and it is inhibited when L is at VIH.
Clock (K).
The clock input synchronizes the
memory to the micro controller during burst mode
read operation; the address is latched on a K edge
(rising or falling, according to the configuration set-
tings) when L is at VIL. K is don’t care during asyn-
chronous page mode read and in write operations.
Wait (WAIT).
WAIT is an output signal used dur-
ing burst mode read, indicating whether the data
on the output bus are valid or a wait state must be
inserted. This output is high impedance when E or
G are high or RP is at VIL, and can be configured
to be active during the wait cycle or one clock cy-
cle in advance.
Bus Invert (BINV).
BINV is an input/output signal
used to reduce the amount of power needed to
switch the external address/data bus. The power
saving is achieved by inverting the data output on
ADQ0-ADQ15 every time this gives an advantage
in terms of number of toggling bits. In burst mode
read, each new data output from the memory is
compared with the previous data. If the number of
transitions required on the data bus is in excess of
8, the data is inverted and the BINV signal will be
driven by the memory at VOH to inform the receiv-
ing system that data must be inverted before any
further processing. By doing so, the actual transi-
tions on the data bus will be less than 8.
In a similar way, when a command is given, BINV
may be driven by the system at VIH to inform the
memory that the data input must be inverted.
Like the other input/output pins, BINV is high im-
pedance when the chip is deselected, output en-
able G is at VIH or RP is at VIL; when used as an
input, BINV must follow the same set-up and hold
timings of the data inputs.
VDD and VDDQ Supply Voltage (1.7V to 2.0V).

VDD is the main power supply for all operations
(Read, Program and Erase). VDDQ is the supply
voltage for Input and Output.
M58MR032C, M58MR032D
VPP Program Supply Voltage (12V).
VPP is both
a control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin; if VPP is kept in a low voltage range
(0 to 2V) VPP is seen as a control input, and the
current absorption is limited to 5μA (0.2μA typical).
In this case with VPP = VIL we obtain an absolute
protection against program or erase; with VPP =
VPP1 these functions are enabled (see Table 26).
VPP value is only sampled during program or
erase write cycles; a change in its value after the
operation has been started does not have any ef-
fect and program or erase are carried on regularly.
If VPP is used in the 11.4V to 12.6V range (VPPH)
then the pin acts as a power supply (see Table
26). This supply voltage must remain stable as
long as program or erase are running. In read
mode the current sunk is less then 0.5mA, while
during program and erase operations the current
may increase up to 10mA.
VSS Ground.
VSS is the reference for all the volt-
age measurements.
7/52
M58MR032C, M58MR032D
Table 4. User Bus Operations (1)

Note:1. X = Don’t care.
Table 5. Read Electronic Signature (AS and Read CFI instructions) (1)

Note:1. Addresses are latched on the rising edge of L input. EA means Electronic Signature Address (see Read Electronic Signature) Value during address latch.
Table 6. Read Block Protection (AS and Read CFI instructions) (1)

Note:1. Addresses are latched on the rising edge of L input. A locked block can be unprotected only with WP at VIH. Value during address latch. BA means Block Address. First cycle command address should indicate the bank of the block address.
DEVICE OPERATIONS

The following operations can be performed using
the appropriate bus cycles: Address Latch, Read
Array (Random, and Page Modes), Write com-
mand, Output Disable, Standby, reset/Power-
down and Block Locking. See Table 4.
Address Latch.
In asynchronous operation, the
address is latched on the rising edge of L input. In
burst mode the address is latched either on the ris-
ing edge of L or on the first rising/falling edge of K
(depending on configuration settings) when L is
low.
Read.
Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status, the Read Configuration Regis-
ter status and the Protection Register.
Read operation of the Memory Array may be per-
formed in asynchronous page mode or synchro-
nous burst mode. In asynchronous page mode
data is internally read and stored in a page buffer.
The page has a size of 4 words and is addressed
by ADQ0 and ADQ1 address inputs.
According to the device configuration the following
Read operations: Electronic Signature - Status
Register - CFI - Block Protection Status - Read
Configuration Register Status - Protection Regis-
ter must be accessed as asynchronous read or as
single synchronous read (see Figure 4).
M58MR032C, M58MR032D
Table 7. Read Protection Register (RSIG and RCFI Instruction) (1)

Note:1. Addresses are latched on the rising edge of L input. X = Don’t care.
Table 8. Dual Bank Operations (1, 2, 3)

Note:1. For detailed description of command see Table 33 and 34. There is a status register for each bank; status register indicates bank state, not P/E.C. status. Command must be written to an address within the block targeted by that command.
9/52
M58MR032C, M58MR032D
Figure 4. Single Synchronous Read Sequence (RSIG, RCFI, RSR instructions)

Both Chip Enable E and Output Enable G must be
at VIL in order to read the output of the memory.
Read array is the default state of the device when
exiting power down or after power up.
Burst Read.
The device also supports a burst
read. In this mode a burst sequence is started at
the first clock edge (rising or falling according to
configuration settings) after the falling edge of L.
After a configurable delay of 2 to 5 clock cycles a
new data is output at each clock cycle. The burst
sequence may be configured for linear or inter-
leaved order and for a length of 4, 8 words or for
continuous burst mode. Wrap and no-wrap modes
are also supported.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur. This delay
will depend on the starting address of the burst se-
quence; the worst case delay will occur when the
sequence is crossing a 64 word boundary and the
starting address was at the end of a four word
boundary. See the Write Read Configuration Reg-
ister (CR) Instruction for more details on all the
possible settings for the synchronous burst read
(see Table 14). It is possible to perform burst read
across bank boundary (all banks in read array
mode).
Write.
Write operations are used to give Instruc-
tion Commands to the memory or to latch Input
Data to be programmed. A write operation is initi-
ated when Chip Enable E and Write Enable W are
at VIL with Output Enable G at VIH. Addresses are
latched on the rising edge of L. Commands and In-
put Data are latched on the rising edge of W or E
whichever occurs first. Noise pulses of less than
5ns typical on E, W and G signals do not start a
write cycle. Write operations are asynchronous
and clock is ignored during write.
Dual Bank Operations.
The Dual Bank allows to
run different operations simultaneously in the two
banks. It is possible to read array data from one
bank while the other is programming, erasing or
reading any data (CFI, status register or electronic
signature).
Read and write cycles can be initiated for simulta-
neous operations in different banks without any
delay. Only one bank at a time is allowed to be in
program or erase mode, while the other must be in
one of the read modes (see Table 8).
Commands must be written to an address within
the block targeted by that command.
Output Disable.
The data outputs are high im-
pedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby.
The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The pow-
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Automatic Standby.
When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus. The automatic standby fea-
ture is not available when the device is configured
for synchronous burst mode.
M58MR032C, M58MR032D
Reset/Power-down.
The memory is in Power-
down when the Read Configuration Register is set
for Power-down and RP is at VIL. The power con-
sumption is reduced to the Power-down level, and
Outputs are in high impedance, independent of the
Chip Enable E, Output Enable G or Write Enable
W inputs. The memory is in reset when the Read
Configuration Register is set for Reset and RP is
at VIL. The power consumption is the same of the
standby and the outputs are in high impedance.
After a Reset/Power down the device defaults to
read array mode, the status register is set to 80h
and the read configuration register defaults to
asynchronous read.
Block Locking.
Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to VIL. The following summarizes the locking oper-
ation. All blocks are protected on power-up. They
can then be unprotected or protected with the Un-
protect and Protect commands. The Lock com-
mand protects a block and prevents it from being
unlocked when WP = 0. When WP = 1, Lock is
overridden. Lock is cleared only when the device
is reset or powered-down (see Protect instruction).
Table 9. Identifier Codes

Note:1. DRC means Die Revision Code.
CR means Read Configuration Register.
LPR means Lock Protection Register.
PR means Unique Device Number and User Programmable OTP.
11/52
M58MR032C, M58MR032D
Table 10. Commands
INSTRUCTIONS AND COMMANDS

Eighteen instructions are available (see Tables 10
and 11) to perform Read Memory Array, Read Sta-
tus Register, Read Electronic Signature, CFI Que-
ry, Block Erase, Bank Erase, Program, Tetra Word
Program, Double Word Program, Clear Status
Register, Program/Erase Suspend, Program/
Erase Resume, Block Protect, Block Unprotect,
Block Lock, Protection Register Program, Read
Configuration Register and Lock Protection Pro-
gram.
Status Register output may be read at any time,
during programming or erase, to monitor the
progress of the operation.
An internal Command Interface (C.I.) decodes the
instructions while an internal Program/Erase Con-
troller (P/E.C.) handles all timing and verifies the
correct execution of the Program and Erase in-
structions. P/E.C. provides a Status Register
whose bits indicate operation and exit status of the
internal algorithms. The Command Interface is re-
set to Read Array when power is first applied,
when exiting from Reset or whenever VDD is lower
than VLKO. Command sequence must be followed
exactly. Any invalid combination of commands will
reset the device to Read Array.
Read (RD)

The Read instruction consists of one write cycle
(refer to Device Operations section) and places
the addressed bank in Read Array mode. When a
device reset occurs, the memory is in Read Array
as default. A read array command will be ignored
while a bank is programming or erasing. However
in the other bank a read array command will be ac-
cepted.
Read Status Register (RSR)
bank’s Status Register indicates when a pro-
gram or erase operation is complete and the suc-
cess or failure of operation itself. Issue a Read
Status Register Instruction (70h) to read the Sta-
tus Register content of the addressed bank. The
status of the other bank is not affected by the com-
mand. The Read Status Register instruction may
be issued at any time, also when a Program/Erase
operation is ongoing. The following Read opera-
tions output the content of the Status Register of
the addressed bank. The Status Register is
latched on the falling edge of E or G signals, and
can be read until E or G returns to VIH. Either E or
G must be toggled to update the latched data.
Read Electronic Signature (RSIG)

The Read Electronic Signature instruction con-
sists of one write cycle (refer to Device Operations
section) giving the command 90h to an address
within the bank A. A subsequent read in the ad-
dress of bank A will output the Manufacturer Code,
the Device Code, the protection Status of Blocks
of bank A, the Die Revision Code, the Protection
Register, or the Read Configuration Register (see
Table 9).
If the first write cycle of Read Electronic Signature
instruction is issued to an address within the bank
B, a subsequent read in an address of bank B will
output the protection Status of Blocks of bank B.
The status of the other bank is not affected by the
command (see Table 8).
See Tables 5, 6, 7 and 8 for the valid address. The
Electronic Signature can be read from the memory
allowing programming equipment or applications
to automatically match their interface to the char-
acteristics of M58MR032C and M58MR032D.
M58MR032C, M58MR032D
Table 11. Instructions
13/52
M58MR032C, M58MR032D
CFI Query (RCFI)

The CFI Query Mode is associated to bank A. The
address of the first write cycle must be within the
bank A. The status of the other bank is not affected
by the command (see Table 8). Writing 98h the de-
vice enters the Common Flash Interface Query
mode. Next read operations in the bank A will read
the CFI data. Write a read instruction to return to
Read mode (refer to the Common Flash Interface
section).
Clear Status Register (CLSR)

The Clear Status Register uses a single write op-
eration, which resets bits b1, b3, b4 e b5 of the sta-
tus register. The Clear Status Register is executed
writing the command 50h independently of the ap-
plied VPP voltage. After executing this command
the device returns to read array mode. The Clear
Status Register command clears only the status
register of the addressed bank.
Block Erase (EE)

Block erasure sets all the bits within the selected
block to ’1’. One block at a time can be erased. It
is not necessary to pre-program the block as the
P/E.C. will do it automatically before erasing. This
instruction use two writes cycles. The first com-
mand written is the Block Erase Set up command
20h. The second command is the Erase Confirm
command D0h. An address within the block to be
erased should be given to the memory during the
two cycles command. If the second command giv-
en is not an erase confirm, the status register bits
b4 and b5 are set and the instruction aborts.
After writing the command, the device outputs sta-
tus register data when any address within the bank
is read. At the end of the operation the bank will re-
main in read status register until a read array com-
mand is written.
Status Register bit b7 is ’0’ while the erasure is in
progress and ’1’ when it has completed. After com-
pletion the Status Register bit b5 returns ’1’ if there
has been an Erase Failure. Status register bit b1
returns ’1’ if the user is attempting to erase a pro-
tected block. Status Register bit b3 returns a ’1’ if
VPP is below VPPLK. Erase aborts if RP turns to
VIL. As data integrity cannot be guaranteed when
the erase operation is aborted, the erase must be
repeated (see Table 12). A Clear Status Register
instruction must be issued to reset b1, b3, b4 and
b5 of the Status Register. During the execution of
the erase by the P/E.C., the bank with the block in
erase accepts only the RSR (Read Status Regis-
ter) and PES (Program/Erase Suspend) instruc-
tions. See figure 19 for Erase Flowchart and
Pseudo Code.
Bank Erase (BE)

Bank erase sets all the bits within the selected
bank to ’1’. It is not necessary to pre-program the
block as the P/E.C. will do it automatically before
erasing.
This instruction uses two writes cycles. The first
command written is the Bank Erase set-up com-
mand 80h. The second command is the Erase
Confirm command D0h. An address within the
bank to be erased should be given to the memory
during the two cycles command. See the Block
Erase command section for status register bit de-
tails.
Note:1. First cycle command address should be the same as the operation’s target address. The first cycle of the RD, RSR, RSIG or RCFI
instruction is followed by read operations in the bank array or special register. Any number of read cycles can occur after one com-
mand cycle. BKA means Address within the bank;
BA means Block Address;
EA means Electronic Signature Address;
CA means Common Flash Interface Address;
WA means Word Address;
PA means Protection Register Address (see Table 7);
LPA means Lock Protection Register Address (see Table 7);
RCA means Read Configuration Register Address. PD means Protection Data;
CD means Common Flash Interface Data;
ED means Electronic Signature Data;
WD means Data to be programmed at the address location WA;
LPD means Lock protection Register Data WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0. Read cycle after e CLSR instruction will output the memory array.
M58MR032C, M58MR032D
Table 12. Status Register Bits

Note: Logic level ’1’ is VIH and ’0’ is VIL.
Program (PG)

The Program instruction programs the array on a
word-by-word basis. The first command must be
given to the target block and only one partition can
be programmed at a time; the other partition must
be in one of the read modes or in the erase sus-
pended mode (see Table 8).
This instruction uses two write cycles. The first
command written is the Program Set-up command
40h (or 10h). A second write operation latches the
Address and the Data to be written and starts the
P/E.C.
Read operations in the targeted bank output the
Status Register content after the programming
has started.
The Status Register bit b7 returns ’0’ while the pro-
gramming is in progress and ’1’ when it has com-
pleted. After completion the Status register bit b4
returns ’1’ if there has been a Program Failure (see
Table 12). Status register bit b1 returns ’1’ if the
user is attempting to program a protected block.
Status Register bit b3 returns a ’1’ if VPP is below
VPPLK. Any attempt to write a ’1’ to an already pro-
grammed bit will result in a program fail (status
register bit b4 set) if VPP = VPPH and will be ig-
nored if VPP = VPP1.
Programming aborts if RP goes to VIL. As data in-
tegrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed. A Clear Status Register instruction
must be issued to reset b5, b4, b3 and b1 of the
Status Register.
During the execution of the program by the P/E.C.,
the bank in programming accepts only the RSR
(Read Status Register) and PES (Program/Erase
Suspend) instructions. See Figure 16 for Program
Flowchart and Pseudo Code.
15/52
M58MR032C, M58MR032D
Table 13. Protection States (1)

Note:1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect in and by
DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = VIH
and A0 = VIL. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
its logic value. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Figure 5. Security Block Memory Map
M58MR032C, M58MR032D
Double Word Program (DPG)

This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. The first command must be given to the
target block and only one partition can be pro-
grammed at a time; the other partition must be in
one of the read modes or in the erase suspended
mode (see Table 8).
The two words must differ only for the address A0.
Programming should not be attempted when VPP
is not at VPPH. The operation can also be executed
if VPP is below VPPH but result could be uncertain.
These instruction uses three write cycles. The first
command written is the Double Word Program
Set-Up command 30h. A second write operation
latches the Address and the Data of the first word
to be written, the third write operation latches the
Address and the Data of the second word to be
written and starts the P/E.C. (see Table 11).
Read operations in the targeted bank output the
Status Register content after the programming
has started. The Status Register bit b7 returns ’0’
while the programming is in progress and ’1’ when
it has completed. After completion the Status reg-
ister bit b4 returns ’1’ if there has been a Program
Failure. Status register bit b1 returns ’1’ if the user
is attempting to program a protected block. Status
Register bit b3 returns a ’1’ if VPP is below VPPLK.
Any attempt to write a ’1’ to an already pro-
grammed bit will result in a program fail (status
register bit b4 set). (See Table 12).
Programming aborts if RP goes to VIL. As data in-
tegrity cannot be guaranteed when the program
operation is aborted, the memory location must be
erased and reprogrammed. A Clear Status Regis-
ter instruction must be issued to reset b5, b4, b3
and b1 of the Status Register. During the execu-
tion of the program by the P/E.C., the bank in pro-
gramming accepts only the RSR (Read Status
Register) instruction. See Figure 17 for Double
Word Program Flowchart and Pseudo code.
Tetra Word Program (TPG)

This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel. The first command must be given to the
target block and only one partition can be pro-
grammed at a time; the other partition must be in
one of the read modes or in the erase suspended
mode (see Table 8).
The four words must differ only for the addresses
A0 and A1. Programming should not be attempted
when VPP is not at VPPH. The operation can also
be executed if VPP is below VPPH but result could
be uncertain. These instruction uses five write cy-
cles. The first command written is the Tetra Word
Program Set-Up command 55h. A second write
operation latches the Address and the Data of the
first word to be written, the third write operation
latches the Address and the Data of the second
word to be written, the fourth write operation latch-
es the Address and the Data of the third word to be
written, the fifth write operation latches the Ad-
dress and the Data of the fourth word to be written
and starts the P/E.C. (see Table 11).
Read operations in the targeted bank output the
Status Register content after the programming
has started. The Status Register bit b7 returns '0'
while the programming is in progress and '1' when
it has completed. After completion the Status reg-
ister bit b4 returns '1' if there has been a Program
Failure. Status register bit b1 returns '1' if the user
is attempting to program a protected block. Status
Register bit b3 returns a '1' if VPP is below VPPLK.
Any attempt to write a ’1’ to an already pro-
grammed bit will result in a program fail (status
register bit b4 set). (See Table 12).
Programming aborts if RP goes to VIL. As data in-
tegrity cannot be guaranteed when the program
operation is aborted, the memory location must be
erased and reprogrammed. A Clear Status Regis-
ter instruction must be issued to reset b5, b4, b3
and b1 of the Status Register. During the execu-
tion of the program by the P/E.C., the bank in pro-
gramming accepts only the RSR (Read Status
Register) instruction. See Figure 17 for Tetra Word
Program Flowchart and Pseudo code.
Erase Suspend/Resume (PES/PER)

The Erase Suspend freezes, after a certain laten-
cy period (within 25us), the erase operation and al-
lows read in another block within the targeted bank
or program in the other block.
This instruction uses one write cycle B0h and the
address should be within the bank with the block
in erase (see Table 11). The device continues to
output status register data after the erase suspend
is issued. The status register bit b7 and bit b6 are
set to ’1’ then the erase operation has been sus-
pended. Bit b6 is set to '0' in case the erase is com-
pleted or in progress (see Table 12).
The valid commands while erase is suspended
are: Program/Erase Resume, Program, Read
Memory Array, Read Status Register, Read Elec-
tronic Signature, CFI Query, Block Protect, Block
Unprotect and Block Lock. The user can protect
the Block being erased issuing the Block Protect
or Block Lock commands.
During a block erase suspend, the device goes
into standby mode by taking E to VIH, which reduc-
es active current draw. Erase is aborted if RP turns
to VIL.
If an Erase Suspend instruction was previously ex-
ecuted, the erase operation may be resumed by
issuing the command D0h using an address within
the suspended bank. The status register bit b6 and
bit b7 are cleared when erase resumes and read
17/52
M58MR032C, M58MR032D

operations output the status register after the
erase is resumed. Block erase cannot resume until
program operations initiated during block erase
suspend have completed. It is also possible to
nest suspends as follows: suspend erase in the
first partition, start programming in the second or
in the same partition, suspend programming and
then read from the second or the same partition.
The suggested flowchart for erase suspend/re-
sume features of the memory is shown from Fig-
ure 20.
Program Suspend/Resume (PES/PER)

Program suspend is accepted only during the Pro-
gram instruction execution. When a Program Sus-
pend command is written to the C.I., the P/E.C.
freezes the Program operation.
Program Resume (PER) continues the Program
operation. Program Suspend (PES) consists of
writing the command B0h and the address should
be within the bank with the word in programming
(see Table 11).
The Status Register bit b2 is set to '1' (within 5μs)
when the program has been suspended. Bit b2 is
set to '0' in case the program is completed or in
progress (see Table 12).
The valid commands while program is suspended
are: Program/Erase Resume, Read Array, Read
Status Register, Read Electronic Signature, CFI
Query. During program suspend mode, the device
goes in standby mode by taking E to VIH. This re-
duces active current consumption. Program is
aborted if RP turns to VIL.
If a Program Suspend instruction was previously
executed, the Program operation may be resumed
by issuing the command D0h using an address
within the suspended bank (see Table 11). The
status register bit b2 and bit b7 are cleared when
program resumes and read operations output the
status register after the erase is resumed (see Ta-
ble 12). The suggested flowchart for program sus-
pend/resume features of the memory is shown
from Figure 18.
Block Protect (BP)

The BP instruction use two write cycles. The first
command written is the protection set-up 60h. The
second command is block Protect command 01h,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands (see Table 12). To read the
status register write the RSR command.
Block Unprotect (BU)

The instruction use two write cycles. The first com-
mand written is the protection set-up 60h. The sec-
ond command is block Unprotect command D0h,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands (see Table 12). To read the
status register write the RSR command.
Block Lock (BL)

The instruction use two write cycles. The first com-
mand written is the protection set-up 60h. The sec-
ond command is block Lock command 2Fh,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands. To read the status register
write the RSR command (see Table 12).
M58MR032C, M58MR032D
BLOCK PROTECTION

The M58MR032C/M58MR032D provide a flexible
protection of all the memory providing the protec-
tion, un-protection and locking of any blocks. All
blocks are protected at power-up. Each block of
the array has two levels of protection against pro-
gramming or erasing operation. The first level is
set by the Block Protect instruction; a protected
block cannot be programmed or erased until a
Block Unprotect instruction is given for that block.
A second level of protection is set by the Block
Lock instruction, and requires the use of the WP
pin, according to the following scheme: when WP is at VIH, the Lock status is overridden
and all blocks can be protected or unprotected; when WP is at VIL, Lock status is enabled; the
locked blocks are protected, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status; the lock status is cleared for all blocks at power
up.
The protection and lock status can be monitored
for each block using the Read Electronic Signature
(RSIG) instruction. Protected blocks will output a
'1' on DQ0 and locked blocks will output a '1' in
DQ1 (see Table 13).
PROTECTION REGISTER PROGRAM (PRP)
and LOCK PROTECTION REGISTER
PROGRAM (LPRP)

The M58MR032C/M58MR032D features a 128-bit
protection register and a security Block in order to
increase the protection of a system design. The
Protection Register is divided in two 64-bit seg-
ments. The first segment (81h to 84h) is a unique
device number, while the second one (85h to 88h)
can be programmed by the user. When shipped
the user programmable segment is read at '1'. It
can be only programmed at '0'.
The user programmable segment can be protect-
ed writing the bit 1 of the Protection Lock register
(80h). The bit 1 protects also the bit 2 of the Pro-
tection Lock Register.
The M58MR032C/M58MR032D feature a security
Block. The security Block is located at 1FF000-
1FFFFF (M58MR032C) or at 000000-000FFF
(M58MR032D) of the device. This block can be
permanently protected by the user programming
the bit 2 of the Protection Lock Register (see Fig-
ure 5).
The protection Register and the Protection Lock
Register can be read using the RSIG and RCFI in-
structions. A subsequent read in the address start-
ing from 80h to 88h, the user will retrieve
respectively the Protection Lock register, the
unique device number segment and the OTP user
programmable register segment (see Table 23).
WRITE READ CONFIGURATION REGISTER
(CR).

This instruction uses two Coded Cycles, the first
write cycle is the write Read Configuration Regis-
ter set-up 60h, the second write cycle is write
Read Configuration Register confirm 03h both to
Read Configuration Register address (see Table
11).
This instruction writes the contents of address bits
ADQ15-ADQ0 to bits CR15-CR0 of the Read Con-
figuration Register (A20-A16 are don't care). At
Power-up the Read Configuration Register is set
to asynchronous Read mode, Power-down dis-
abled and bus invert (power save function) dis-
abled. A description of the effects of each
configuration bit is given in Table 14.
Read mode (CR15).
The device supports an
asynchronous page mode and a synchronous
burst mode. In asynchronous page mode, the de-
fault at power-up, data is internally read and stored
in a buffer of 4 words selected by ADQ0 and ADQ1
address inputs. In synchronous burst mode, the
device latches the starting address and then out-
puts a sequence of data that depends on the Read
Configuration Register settings (see Figures 10,
11 and 12).
Synchronous burst mode is supported in both pa-
rameter and main blocks; it is also possible to per-
form burst mode read across the banks.
Bus Invert configuration (CR14).
This register
bit is used to enable the BINV pin functionality.
BINV functionality depends upon configuration
bits CR14 and CR15 (see Table 14 for configura-
tion bits definition) as shown in Table 15. As output
pin BINV is active only when enabled (CR14 = 1)
in Read Array burst mode (CR15 = 0). As input pin
BINV is active only when enabled (CR14 = 1).
BINV is ignored when ADQ0-ADQ15 lines are
used as address inputs (addresses must not be in-
verted).
X-Latency (CR13-CR11).
These configuration
bits define the number of clock cycles elapsing
from L going low to valid data available in burst
mode (see Figure 6). The correspondence be-
tween X-Latency settings and the maximum sus-
tainable frequency must be calculated taking into
account some system parameters.
Two conditions must be satisfied:
–(n + 2) tK ≥ tACC + tQVK_CPU + tAVK_CPU
–tK > tKQV + tQVK_CPU
where "n" is the chosen X-Latency configuration
code, tK is the clock period, tAVK_CPU is the ad-
dress setup time guaranteed by the system CPU,
and tQVK_CPU is the data setup time required by
the system CPU.
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M58MR032C, M58MR032D
Table 14. Read Configuration Register (AS and Read CFI instructions) (1)

Note:1. The RCR can be read via the RSIG command (90h). Bank A Address + 05h contains the RCR data. See Table 9. All the bits in the RCR are set to default on device power-up or reset.
Table 15. BINV Configuration Bits
M58MR032C, M58MR032D
Power-down configuration (CR10).
The RP pin
may be configured to give very low power con-
sumption when driven low (power-down state). In
power-down the ICC supply current is reduced to a
typical figure of ICC2; if this function is disabled
(default at power-up) the RP pin causes only a re-
set of the device and the supply current is the
stand-by value. The recovery time after a RP pulse
is significantly longer when power-down is en-
abled (see Table 31).
Wait configuration (CR8).
In burst mode WAIT
indicates whether the data on the output bus are
valid or a wait state must be inserted. The config-
uration bit determines if WAIT will be asserted one
clock cycle before the wait state or during the wait
state (see Figure 7). WAIT is asserted during a
continuous burst and also during a 4 or 8 burst
length if no-wrap configuration is selected.
Burst order configuration (CR7) and Burst
Wrap configuration (CR3).
See Table 16 for
burst order and length.
Clock configuration (CR6).
In burst mode deter-
mines if address is latched and data is output on
the rising or falling edge of the clock.
Burst length (CR2-CR0).
In burst mode deter-
mines the number of words output by the memory.
It is possible to have 4 words, 8 words or a contin-
uous burst mode, in which all the words are read
sequentially. In continuous burst mode the burst
sequence can cross the end of each of the two
banks (all banks in read array mode). In continu-
ous burst mode or in 4, 8 words no-wrap it may
happen that the memory will stop the data output
flow for a few clock cycles; this event is signaled by
WAIT going low until the output flow is resumed.
The initial address determines if the output delay
will occur as well as its duration. If the starting ad-
dress is aligned to a four words boundary no wait
states will be needed. If the starting address is
shifted by 1,2 or 3 positions from the four word
boundary, WAIT will be asserted for 1, 2 or 3 clock
cycles when the burst sequence is crossing the
first 64 word boundary. WAIT will be asserted only
once during a continuous burst access. See also
Table 16.
Figure 6. X-Latency Configuration Sequence
21/52
M58MR032C, M58MR032D
Figure 7. Wait Configuration Sequence
M58MR032C, M58MR032D
23/52
M58MR032C, M58MR032D
POWER CONSUMPTION
Power-down

The memory provides Reset/Power-down control
input RP. The Power-down function can be acti-
vated only if the relevant Read Configuration Reg-
ister bit is set to ’1’. In this case, when the RP
signal is pulled at VSS the supply current drops to
typically ICC2 (see Table 26), the memory is dese-
lected and the outputs are in high impedance. If
RP is pulled to VSS during a Program or Erase op-
eration, this operation is aborted and the memory
content is no longer valid (see Reset/Power-down
input description).
Power-up

The memory Command Interface is reset on Pow-
er-up to Read Array. Either E or W must be tied to
VIH during Power-up to allow maximum security
and the possibility to write a command on the first
rising edge of W. At Power-up the device is config-
ured as: Page mode: (CR15 = 1) Power-down disabled: (CR10 = 0) BINV disabled: (CR14 = 0).
All blocks are protected and unlocked.
VDD, VDDQ and VPP are independent power sup-
plies and can be biased in any order.
Supply Rails

Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the VDD rails decoupled with a 0.1μF capac-
itor close to the VDD, VDDQ and VSS pins. The PCB
trace widths should be sufficient to carry the re-
quired VDD program and erase currents.
M58MR032C, M58MR032D
COMMON FLASH INTERFACE (CFI)

The Common Flash Interface (CFI) specification is
a JEDEC approved, standardized data structure
that can be read from the Flash memory device.
CFI allows a system software to query the flash
device to determine various electrical and timing
parameters, density information and functions
supported by the device. CFI allows the system to
easily interface to the Flash memory, to learn
about its features and parameters, enabling the
software to configure itself when necessary.
Tables 17, 18, 19, 20, 21, 22 and 23 show the ad-
dress used to retrieve each data. The CFI data
structure gives information on the device, such as
the sectorization, the command set and some
electrical specifications. The CFI data structure
contains also a security area; in this section, a 64
bit unique security number is written, starting at
address 81h. This area can be accessed only in
read mode and there are no ways of changing the
code after it has been written by ST. Write a read
instruction to return to Read mode (see Table 11).
Refer to the CFI Query instruction to understand
how the M58MR032 enters the CFI Query mode.
Table 17. Query Structure Overview

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 18, 19, 20, 21, 22 and 23. Query data are always presented on the lowest order data outputs.
Table 18. CFI Query Identification String

Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’. DRC means Die Revision Code.
25/52
M58MR032C, M58MR032D
Table 19. CFI Query System Interface Information
M58MR032C, M58MR032D
Table 20. Device Geometry Definition
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