M58LW032A ,32 MBIT (2MB X16, UNIFORM BLOCK, BURST)3V SUPPLY FLASH MEMORYLogic Diagram . 7Table 1. Signal Names . . 7Figure 3. TSOP56 Connections . . . ..
M58LW032C ,32 MBIT (2MB X16, UNIFORM BLOCK, BURST)3V SUPPLY FLASH MEMORYLogic Diagram . 7Table 1. Signal Names . . 7Figure 3. TSOP56 Connections . . . ..
M58LW032C110N1 ,32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash MemoryFEATURES SUMMARY WIDE x16 DATA BUS for HIGH BANDWIDTH Figure 1. Packages SUPPLY VOLTAGE–V = 2.7 t ..
M58LW032C110N1 ,32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash MemoryFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1SUMMARY DESCRIPTION ..
M58LW032C-110N1 ,32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash MemoryM58LW032C32 Mbit (2Mb x16, Uniform Block, Burst)3V Supply Flash Memory
M58LW032C90N1 ,32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash MemoryLogic Diagram . . 7Table 1. Signal Names . . 7Figure 3. TSOP56 Connections . . ..
M95256 ,256/128 Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95256-MW6 ,256 Kbit (32K x8)serial SPI bus EEPROM with high speed clock, operating = 4.5 V to 5.5 VFEATURES SUMMARY . . . . . 1Table 1. Product List . . . . 1Figure 1. Packages . ..
M95256-MW6T ,256Kbit Serial SPI Bus EEPROM With High Speed ClockAbsolute Maximum Ratings . . . . . . . 21DC AND AC PARAMETERS . 22Table 8. Operating Cond ..
M95256-RMW6TP ,256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES SUMMARY . . . . . 1Table 1. Product List . . . . 1Figure 1. Packages . ..
M95256VMW6 ,256Kbit Serial SPI Bus EEPROM With High Speed ClockM95256M95128256Kbit and 128Kbit Serial SPI Bus EEPROMWith High Speed Clock
M95256-VMW6 ,256Kbit Serial SPI Bus EEPROM With High Speed ClockAbsolute Maximum Ratings . . . . . . . 21DC AND AC PARAMETERS . 22Table 8. Operating Cond ..
M58LW032A
32 MBIT (2MB X16, UNIFORM BLOCK, BURST)3V SUPPLY FLASH MEMORY
1/61February 2003
M58LW032A32 Mbit (2Mb x16, Uniform Block, Burst)
3V Supply Flash Memory
FEATURES SUMMARY WIDE x16 DATA BUS for HIGH BANDWIDTH SUPPLY VOLTAGE
–VDD = 2.7 to 3.6V core supply voltage for Pro-
gram, Erase and Read operations
–VDDQ = 1.8V to VDD for I/O Buffers SYNCHRONOUS/ASYNCHRONOUS READ Synchronous Burst read Asynchronous Random Read Asynchronous Address Latch Controlled
Read Page Read ACCESS TIME Synchronous Burst Read up to 56MHz Asynchronous Page Mode Read 90/25ns and
110/25ns Random Read 90ns, 110ns. PROGRAMMING TIME 16 Word Write Buffer
–18μs Word effective programming time 64 UNIFORM 32 KWord MEMORY BLOCKS BLOCK PROTECTION/ UNPROTECTION PROGRAM and ERASE SUSPEND 128 bit PROTECTION REGISTER COMMON FLASH INTERFACE 100, 000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code M58LW032A: 8816h
M58LW032A2/61
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. TBGA64 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Program/Erase Enable (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 2. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3. Synchronous Burst Read Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3/61
M58LW032AValid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 4. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Burst Configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 6. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 25
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 10. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
M58LW032A4/61
Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . 33
Figure 13. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 35
Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 35
Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . 37
Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 37
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 40
Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 42
Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 42
Figure 22. TBGA64 10x13mm - 8x8 ball array 1mm pitch, Package Outline . . . . . . . . . . . . . . . . 43
Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data. . . . . . . . . 43
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 25. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 23. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 50
5/61
M58LW032AFigure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 51
Figure 25. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 53
Figure 27. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 28. Blocks Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56
Figure 30. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 57
Figure 31. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 58
Figure 32. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 59
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M58LW032A6/61
SUMMARY DESCRIPTIONThe M58LW032 is a 32 Mbit (2Mb x16) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (2.7V to 3.6V) core sup-
ply. On power-up the memory defaults to Read
mode with an asynchronous bus where it can be
read in the same way as a non-burst Flash mem-
ory.
The memory is divided into 64 blocks of 512Kbit
that can be erased independently so it is possible
to preserve valid data while old data is erased.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
Individual block protection against Program or
Erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked when the Program Erase Enable
input Vpp is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in power-down mode.
In asynchronous mode Chip Enable, Output En-
able and Write Enable signals control the bus op-
eration of the memory. An Address Latch input can
be used to latch addresses. Together they allow
simple, yet powerful, connection to most micropro-
cessors, often without additional logic.
In synchronous mode all Bus Read operations are
synchronous with the Clock. Chip Enable and Out-
put Enable select the Bus Read operation and the
address is Latched using the Latch Enable input.
The signals are compatible with most micropro-
cessor burst interfaces.
The device includes a 128 bit Protection Register.
The Protection Register is divided into two 64 bit
segments, the first one is written by the manufac-
turer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the user. The user programma-
ble segment can be locked.
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10 x 13mm, 1mm pitch) packages.
7/61
M58LW032A
Table 1. Signal Names
M58LW032A8/61
9/61
M58LW032A
M58LW032A10/61
11/61
M58LW032A
SIGNAL DESCRIPTIONSSee Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A1-A21). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable and Latch Enable must be low when
selecting the addresses.
The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a Write operation. The
address latch is transparent when Latch Enable is
low, VIL. The address is internally latched in an
Erase or Program operation.
Data Inputs/Outputs (DQ0-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
low, VIL, the data bus outputs data from the mem-
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the chip is deselected, Output Enable
is high, VIH, or the Reset/Power-Down signal is
low, VIL. When the Program/Erase Controller is
active the Ready/Busy status is given on DQ7.
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
VIH deselects the memory and reduces the power
consumption to the Standby level, IDD1.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at VIH
the outputs are high impedance. Output Enable,
G, can be used to inhibit the data output during a
burst read operation.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The Reset/Power-
Down pin can be used to apply a Hardware Reset
to the memory.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, VIL, for at least tPLPH. When
Reset/Power-Down is Low, VIL, the Status Regis-
ter information is cleared and the power consump-
tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re-
set/Power-Down goes low, VIL,during a Block
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the Ready/
Busy pin stays low, VIL, for a maximum timing of
tPLPH + tPHRH, until the completion of the Reset/
Power-Down pulse.
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read and Bus Write
operations after tPHQV. Note that Ready/Busy
does not fall during a reset, see Ready/Busy Out-
put section.
In an application, it is recommended to either as-
sociate the Reset/Power-Down pin, RP, with the
reset signal of the microprocessor, or to ensure
that the Reset/Power-Down pin is kept Low during
Power-on. Otherwise, if a reset operation occurs
while the memory is performing an Erase or Pro-
gram operation, the memory may output the Sta-
tus Register information instead of being initialized
to the default Asynchronous Random Read.
Latch Enable (L). The Bus Interface is config-
ured to latch the Address Inputs on the rising edge
of Latch Enable, L. In synchronous bus operations
the address is latched on the active edge of the
Clock when Latch Enable is Low, VIL or on the ris-
ing of Latch Enable, whichever occurs first. Once
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
Enable is Low, VIL, the latch is transparent.
Clock (K). The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
low, VIL, or on the rising edge of Latch Enable,
whichever occurs first.
During asynchronous bus operations the Clock is
not used.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
M58LW032A12/61
one cycle before. Valid Data Ready Low, VOL, in-
dicates that the data is not, or will not be valid. Val-
id Data Ready in a high-impedance state indicates
that valid data is or will be available.
Unless Synchronous Burst Read has been select-
ed, Valid Data Ready is high-impedance. It may be
tied to other components with the same Valid Data
Ready signal to create a unique System Ready
signal.
The Valid Data Ready, R, output has an internal
pull-up resistor of approximately 1 MΩ powered
from VDDQ, designers should use an external pull-
up resistor of the correct value to meet the external
timing requirements for Valid Data Ready rising.
Refer to Figure 19.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the Program/Erase Controller is currently active.
When Ready/Busy is high impedance, the memo-
ry is ready for any Read, Program or Erase opera-
tion. Ready/Busy is Low, VOL, during Program and
Erase operations. When the device is busy it will
not accept any additional Program or Erase com-
mands except Program/Erase Suspend. When the
Program/Erase Controller is idle, or suspended,
Ready Busy can float High through a pull-up resis-
tor.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Ready/Busy is not Low during a reset unless the
reset was applied when the Program/Erase Con-
troller was active; Ready/Busy can rise before Re-
set/Power-Down rises.
Program/Erase Enable (VPP). The Program/
Erase Enable input, VPP, is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
It is recommended to power-up and power-down
VDD and VDDQ together to avoid any condition that
would result in data corruption.
VSS Ground. Ground, VSS, is the reference for
the core power supply. It must be connected to the
system ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS.
Note: Each device in a system should have
VDD and VDDQ decoupled with a 0.1μF ceramic
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 10, AC Measurement Load Circuit.
13/61
M58LW032A
BUS OPERATIONSThere are 12 bus operations that control the mem-
ory. Each of these is described in this section, see
Tables 2 and 3, Bus Operations, for a summary.
The bus operation is selected through the Burst
Configuration Register; the bits in this register are
described at the end of this section.
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Latch Enable Con-
trolled Read and Asynchronous Bus Write, no
other bus operation can be performed until the
Burst Control Register has been configured.
The Electronic Signature, CFI or Status Register
will be read in asynchronous mode or single syn-
chronous burst mode.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus OperationsFor asynchronous bus operations refer to Table 3
together with the text below.
Asynchronous Bus Read. Asynchronous Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Status
Register, CFI and Block Protection Status) in the
Command Interface. A valid bus operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable,
Output Enable and Latch Enable and keeping
Write Enable High, VIH. The Data Inputs/Outputs
will output the value, see Figure 11, Asynchronous
Bus Read AC Waveforms, and Table 15, Asyn-
chronous Bus Read AC Characteristics, for details
of when the output becomes valid.
Asynchronous Latch Controlled Bus Read.Asynchronous Latch Controlled Bus Read opera-
tions read from the memory cells or specific regis-
ters in the Command Interface. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Latch Enable Low, VIL and keeping Write
Enable High, VIH; the address is latched on the ris-
ing edge of Address Latch. Once latched, the Ad-
dress Inputs can change. Set Output Enable Low,
VIL, to read the data on the Data Inputs/Outputs;
see Figure 12, Asynchronous Latch Controlled
Bus Read AC Waveforms and Table 16, Asyn-
chronous Latch Controlled Bus Read AC Charac-
teristics for details on when the output becomes
valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, VIL, Asynchronous Bus Read
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, VIL
throughout the bus operation.
Asynchronous Page Read. Asynchronous Page
Read operations are used to read from several ad-
dresses within the same memory page. Each
memory page is 4 Words and has the same A3-
A21, only A1 and A2 may change.
Valid bus operations are the same as Asynchro-
nous Bus Read operations but with different tim-
ings. The first read operation within the page has
identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. See Figure 13, Asynchronous Page
Read AC Waveforms and Table 17, Asynchro-
nous Page Read AC Characteristics for details on
when the outputs become valid.
Asynchronous Bus Write. Asynchronous Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts and setting Latch Enable Low, VIL. The Ad-
dress Inputs are latched by the Command
Interface on the rising edge of Chip Enable or
Write Enable, whichever occurs first. The Data In-
puts/Outputs are latched by the Command Inter-
face on the rising edge of Chip Enable or Write
Enable, whichever occurs first. Output Enable
must remain High, VIH, during the whole Asyn-
chronous Bus Write operation. See Figures 14,
and 16, Asynchronous Write AC Waveforms, and
Tables 18 and 19, Asynchronous Write and Latch
Controlled Write AC Characteristics, for details of
the timing requirements.
Asynchronous Latch Controlled Bus Write.Asynchronous Latch Controlled Bus Write opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data to program. Bus Write op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,
VIL. The Address Inputs are latched by the Com-
mand Interface on the rising edge of Latch Enable,
Chip Enable or Write Enable, whichever occurs
first. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip En-
able or Write Enable, whichever occurs first. Out-
M58LW032A14/61
put Enable must remain High, VIH, during the
whole Asynchronous Bus Write operation. See
Figures 15 and 17 Asynchronous Latch Controlled
Write AC Waveforms, and Tables 18 and 19,
Asynchronous Write and Latch Controlled Write
AC Characteristics, for details of the timing re-
quirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, IDD1.
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Current, IDD3, for Program or Erase operations un-
til the operation completes.
Automatic Low Power. If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current, IDD5. The Data Inputs/Outputs will
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, IDD2, and the outputs are high impedance,
independent of Chip Enable, Output Enable or
Write Enable.
Table 2. Asynchronous Bus Operations Note:1. X = Don’t Care VIL or VIH. High = VIH or VHH.
15/61
M58LW032A
Synchronous Bus OperationsFor synchronous bus operations refer to Table 3
together with the text below.
Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external ref-
erence clock. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion.
A valid Synchronous Burst Read operation begins
when the address is set on the Address Inputs,
Write Enable is High, VIH, and Chip Enable and
Latch Enable are Low, VIL, during the active edge
of the Clock. The address is latched on the first ac-
tive clock edge when Latch Enable is low, or on
the rising edge of Latch Enable, whichever occurs
first. The data becomes available for output after
the X-latency specified in the Burst Control Regis-
ter has expired. The output buffers are activated
by setting Output Enable Low, VIL. See Figures 6
and 7 for examples of Synchronous Burst Read
operations.
In Continuous Burst mode one Burst Read opera-
tion can access the entire memory sequentially. If
the starting address is not associated with a page
(4 Word) boundary the Valid Data Ready, R, out-
put goes Low, VIL, to indicate that the data will not
be ready in time and additional wait-states are re-
quired. The Valid Data Ready output timing (bit
M8) can be changed in the Burst Configuration
Register.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 18, 19
and Table 20.
Table 3. Synchronous Burst Read Bus OperationsNote:1. X = Don't Care, VIL or VIH. M15 = 0, Bit M15 is in the Burst Configuration Register. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.
M58LW032A16/61
Burst Configuration RegisterThe Burst Configuration Register is used to config-
ure the type of bus access that the memory will
perform. The Burst Configuration Register bits are
described in Table 4. They specify the selection of
the burst length, burst type, burst X and Y laten-
cies and the Read operation. See figures 6 and 7
for examples of Synchronous Burst Read configu-
rations.
The Burst Configuration Register is set through
the Command Interface and will retain its informa-
tion until it is re-configured, the device is reset, or
the device goes into Reset/Power-Down mode.
The Burst Configuration Register is read using the
Read Electronic Signature Command at address
05h.
Read Select Bit (M15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.
On reset or power-up the Read Select bit is set to
’1’ for asynchronous access.
X-Latency Bits (M13-M11). The X-Latency bits
are used during Synchronous Bus Read opera-
tions to set the number of clock cycles between
the address being latched and the first data be-
coming available. For correct operation the X-La-
tency bits can only assume the values in Table 4,
Burst Configuration Register.
Internal Clock Divider Bit (M10). The Internal
Clock Divider Bit is used to divide the internal clock
by two. When M10 is set to ‘1’ the internal clock is
divided by two, which effectively means that the X
and Y-Latency values are multiplied by two, that is
the number of clock cycles between the address
being latched and the first data becoming avail-
able will be twice the value set in M13-M11, and
the number of clock cycles between consecutive
reads will be twice the value set in M9. For exam-
ple 8-1-1-1 will become 16-2-2-2. When M10 is set
to ‘0’ the internal clock runs normally and the X
and Y-Latency values are those set in M13-M11
and M9.
Y-Latency Bit (M9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in M9.
When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every second clock cycle. See Table 4,
Burst Configuration Register for valid combina-
tions of the Y-Latency, the X-Latency and the
Clock frequency.
Valid Data Ready Bit (M8). The Valid Data
Ready bit controls the timing of the Valid Data
Ready output pin, R. When the Valid Data Ready
bit is ’0’ the Valid Data Ready output pin is driven
Low for the active clock edge when invalid data is
output on the bus. When the Valid Data Ready bit
is ’1’ the Valid Data Ready output pin is driven Low
one clock cycle prior to invalid data being output
on the bus.
Burst Type Bit (M7). The Burst Type bit is used
to configure the sequence of addresses read as
sequential or interleaved. When the Burst Type bit
is ’0’ the memory outputs from interleaved ad-
dresses; when the Burst Type bit is ’1’ the memory
outputs from sequential addresses. See Tables 5,
Burst Type Definition, for the sequence of ad-
dresses output from a given starting address in
each mode.
Valid Clock Edge Bit (M6). The Valid Clock Edge
bit, M6, is used to configure the active edge of the
Clock, K, during Synchronous Burst Read opera-
tions. When the Valid Clock Edge bit is ’0’ the fall-
ing edge of the Clock is the active edge; when the
Valid Clock Edge bit is ’1’ the rising edge of the
Clock is active.
Burst Length Bit (M2-M0). The Burst Length bits
set the maximum number of Words that can be
output during a Synchronous Burst Read opera-
tion.
Table 4, Burst Configuration Register gives the
valid combinations of the Burst Length bits that the
memory accepts; Tables 5, Burst Type Definition,
give the sequence of addresses output from a giv-
en starting address for each length.
M5 M4 and M3 are reserved for future use.
17/61
M58LW032A
Table 4. Burst Configuration RegisterNote:1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed. X latencies can be calculated as: (tAVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK
is the clock period). Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK. tSYSTEM MARGIN is the time margin required for the calculation.
M58LW032A18/61
19/61
M58LW032A
M58LW032A20/61
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
6, Commands. Refer to Table 6 in conjunction with
the text descriptions below.
After power-up or a Reset operation the memory
enters Read mode.
Synchronous Read operations and Latch Con-
trolled Bus Read operations can only be used to
read the memory array. The Electronic Signature,
CFI or Status Register will be read in asynchro-
nous mode or single synchronous burst mode.
Once the memory returns to Read Memory Array
mode the bus will resume the setting in the Burst
Configuration Register automatically.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to Read
mode. One Bus Write cycle is required to issue the
Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read commands will access the memory array.
While the Program/Erase Controller is executing a
Program, Erase, Block Protect, Blocks Unprotect
or Protection Register Program operation the
memory will not accept the Read Memory Array
command until the operation completes.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status, the Burst Configuration Regis-
ter and the Protection Register. One Bus Write cy-
cle is required to issue the Read Electronic
Signature command. Once the command is is-
sued subsequent Bus Read operations read the
Manufacturer Code, the Device Code, the Block
Protection Status, the Burst Configuration Regis-
ter or the Protection Register until another com-
mand is issued. Refer to Table 7, Read Electronic
Signature, Table 8, Read Protection Register and
Figure 8, Protection Register Memory Map for in-
formation on the addresses.
Read Query Command. The Read Query Com-
mand is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash In-
terface Memory Area. See Appendix B, Tables 26,
27, 28, 29, 30 and 31 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
Read Status Register Command. The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued.
The Status Register information is present on the
output data bus (DQ1-DQ7) when both Chip En-
able and Output Enable are low, VIL.
See the section on the Status Register and Table
10 for details on the definitions of the Status Reg-
ister bits
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect, Blocks
Unprotect or Protection Register Program com-
mand is issued. If any error occurs then it is essen-
tial to clear any error bits in the Status Register by
issuing the Clear Status Register command before
attempting a new Program, Erase or Resume
command.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 9.
See Appendix C, Figure 25, Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Word Program Command. The Word Program
command is used to program a single word in the
memory array. Two Bus Write operations are re-
quired to issue the command; the first write cycle
sets up the Word Program command, the second
write cycle latches the address and data to be pro-
grammed in the internal state machine and starts
the Program/Erase Controller.
21/61
M58LW032AIf the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command.
Write to Buffer and Program Command. The
Write to Buffer and Program command is used to
program the memory array.
Up to 16 Words can be loaded into the Write Buffer
and programmed into the memory. Each Write
Buffer has the same A5-A21 addresses.
Four successive steps are required to issue the
command. One Bus Write operation is required to set up
the Write to Buffer and Program Command. Is-
sue the set up command with the selected
memory Block Address where the program op-
eration should occur (any address in the block
where the values will be programmed can be
used). Any Bus Read operations will start to out-
put the Status Register after the 1st cycle. Use one Bus Write operation to write the same
block address along with the value N on the
Data Inputs/Output, where N+1 is the number of
Words to be programmed. Use N+1 Bus Write operations to load the ad-
dress and data for each Word into the Write
Buffer. The addresses must have the same A5-
A21. Finally, use one Bus Write operation to issue the
final cycle to confirm the command and start the
Program operation.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper-
ation without affecting the data in the memory ar-
ray. The Status Register should be cleared before
re-issuing the command.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command.
See Appendix C, Figure 23, Write to Buffer and
Program Flowchart and Pseudo Code, for a sug-
gested flowchart on using the Write to Buffer and
Program command.
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command is used to pause a
Write to Buffer and Program or Erase operation.
The command will only be accepted during a Pro-
gram or an Erase operation. It can be issued at
any time during an Erase operation but will only be
accepted during a Write to Buffer and Program
command if the Program/Erase Controller is run-
ning.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 9.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Word Program,
Write to Buffer and Program, and the Program
Suspend commands will also be accepted. When
a program operation is completed inside a Block
Erase Suspend the Read Memory Array command
must be issued to reset the device in Read mode,
then the Erase Resume command can be issued
to complete the whole sequence. Only the blocks
not being erased may be read or programmed cor-
rectly.
See Appendix C, Figure 24, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
26, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
Set Burst Configuration Register Command.The Set Burst Configuration Register command is
used to write a new value to the Burst Configura-
tion Control Register which defines the burst
length, type, X and Y latencies, Synchronous/
Asynchronous Read mode and the valid Clock
edge configuration.
M58LW032A22/61
Two Bus Write cycles are required to issue the Set
Burst Configuration Register command. Once the
command is issued the memory returns to Read
mode as if a Read Memory Array command had
been issued.
The value for the Burst Configuration Register is
presented on A1-A16. M0 is on A1, M1 on A2, etc.;
the other address bits are ignored.
Block Protect Command. The Block Protect
command is used to protect a block and prevent
Program or Erase operations from changing the
data in it. Two Bus Write cycles are required to is-
sue the Block Protect command; the second Bus
Write cycle latches the block address in the inter-
nal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits. Typical Block Protection times are given in
Table 9.
The Block Protection bits are non-volatile, once
set they remain set through reset and power-
down/power-up. They are cleared by a Blocks Un-
protect command.
See Appendix C, Figure 27, Block Protect Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Protect command.
Blocks Unprotect Command. The Blocks Un-
protect command is used to unprotect all of the
blocks. Two Bus Write cycles are required to issue
the Blocks Unprotect command; the second Bus
Write cycle starts the Program/Erase Controller.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. Typical
Block Protection times are given in Table 9.
See Appendix C, Figure 28, Blocks Unprotect
Flowchart and Pseudo Code, for a suggested flow-
chart on using the Blocks Unprotect command.
Protection Register Program Command. The
Protection Register Program command is used to
Program the 64 bit user segment of the Protection
Register. The segment is programmed 16 bits at a
time. The memory must be reset by issuing the
Read Memory Array command before the Protec-
tion Register Program command can be issued.
Two write cycles are required to issue the Protec-
tion Register Program command. The first bus cycle sets up the Protection
Register Program command. The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The user-programmable segment can be locked
by programming bit 1 of the Protection Register
Lock location to ‘0’ (see Table 8). Bit 0 of the Pro-
tection Register Lock location locks the factory
programmed segment and is programmed to ‘0’ in
the factory. The locking of the Protection Register
is not reversible, once the lock bits are pro-
grammed no further changes can be made to the
values stored in the Protection Register, see Fig-
ure 8, Protection Register Memory Map. Attempt-
ing to program a previously protected Protection
Register will result in a Status Register error.
The Protection Register Program cannot be sus-
pended. See Appendix C, Figure 29, Protection
Register Program Flowchart and Pseudo Code,
for the flowchart for using the Protection Register
Program command.
23/61
M58LW032A
Table 6. CommandsNote:1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program
Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register
value. Base Address, refer to Figure 8 and Table 8 for more information. For Identifier addresses and data refer to table 7, Read Electronic Signature. For Query Address and Data refer to Appendix B, CFI.
Table 7. Read Electronic SignatureNote:1. SBA is the Start Base Address of each block, BCR is Burst Configuration Register data, PRD is Protection Register Data. Base Address, refer to Figure 8 and Table 8 for more information.
M58LW032A24/61
25/61
M58LW032A
Table 9. Program, Erase Times and Program Erase Endurance CyclesNote: TA = 0 to 70°C; VDD = 2.7V to 3.6V; VDDQ =1.8V
M58LW032A26/61
STATUS REGISTERThe Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re-
sume commands. The Status Register can be
read from any address.
The Status Register can only be read using Asyn-
chronous Bus Read operations. Once the memory
returns to Read Memory Array mode the bus will
resume the setting in the Burst Configuration Reg-
ister automatically.
The contents of the Status Register can be updat-
ed during an Erase or Program operation by tog-
gling the Output Enable pin or by dis-activating
(Chip Enable, VIH) and then reactivating (Chip En-
able and Output Enable, VIL) the device.
Status Register bits 5, 4, 3 and 1 are associated
with various error conditions and can only be reset
with the Clear Status Register command. The Sta-
tus Register bits are summarized in Table 10, Sta-
tus Register Bits. Refer to Table 10 in conjunction
with the following text descriptions.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low, VOL, the Program/Erase Controller is active
and all other Status Register bits are High Imped-
ance; when the bit is High, VOH, the Program/
Erase Controller is inactive.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control-
ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con-
troller completes the operation and the bit is High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is Low, VOL,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is High, VOH, a
Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
When the Erase Status bit is Low, VOL, the mem-
ory has successfully verified that the block has
erased correctly or all blocks have been unprotect-
ed successfully. When the Erase Status bit is
High, VOH, the erase operation has failed. De-
pending on the cause of the failure other Status
Register bits may also be set to High, VOH. If only the Erase Status bit (bit 5) is set High,
VOH, then the Program/Erase Controller has
applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have been
unprotected successfully. If the failure is due to an erase or blocks
unprotect with VPP low, VOL, then VPP Status bit
(bit 3) is also set High, VOH. If the failure is due to an erase on a protected
block then Block Protection Status bit (bit 1) is
also set High, VOH. If the failure is due to a program or erase
incorrect command sequence then Program
Status bit (bit 4) is also set High, VOH.
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program or Block Protect fail-
ure. The Program Status bit should be read once
the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
When the Program Status bit is Low, VOL, the
memory has successfully verified that the Write
Buffer has programmed correctly or the block is
protected. When the Program Status bit is High,
VOH, the program or block protect operation has
27/61
M58LW032Afailed. Depending on the cause of the failure other
Status Register bits may also be set to High, VOH. If only the Program Status bit (bit 4) is set High,
VOH, then the Program/Erase Controller has
applied the maximum number of pulses to the
byte and still failed to verify that the Write Buffer
has programmed correctly or that the Block is
protected. If the failure is due to a program or block protect
with VPP low, VOL, then VPP Status bit (bit 3) is
also set High, VOH. If the failure is due to a program on a protected
block then Block Protection Status bit (bit 1) is
also set High, VOH. If the failure is due to a program or erase
incorrect command sequence then Erase
Status bit (bit 5) is also set High, VOH.
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify if a Word Program, Erase, Block
Protection or Blocks Unprotection operation has
been attempted when VPP is Low, VIL. The VPP
Status bit cannot be used during a Write to Buffer
and Program operation.
When the VPP Status bit is Low, VOL, no Word Pro-
gram, Erase, Block Protection or Blocks Unprotec-
tion operations have been attempted with VPP
Low, VIL, since the last Clear Status Register com-
mand, or hardware reset. When the VPP Status bit
is High, VOH, a Word Program, Erase, Block Pro-
tection or Blocks Unprotection operation has been
attempted with VPP Low, VIL.
Once set High, the VPP Status bit can only be reset
by a Clear Status Register command or a hard-
ware reset. If set High it should be reset before a
new Program, Erase, Block Protection or Blocks
Unprotection command is issued, otherwise the
new command will appear to fail.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive); after a Program/Erase Suspend
command is issued the memory may still complete
the operation rather than entering the Suspend
mode.
When the Program Suspend Status bit is Low,
VOL, the Program/Erase Controller is active or has
completed its operation; when the bit is High, VOH,
a Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a protected block.
When the Block Protection Status bit is Low, VOL,
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is High, VOH,
a Program (Program Status bit 4 set High) or
Erase (Erase Status bit 5 set High) operation has
been attempted on a protected block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
M58LW032A28/61
Table 10. Status Register Bits
29/61
M58LW032A
MAXIMUM RATINGStressing the device above the ratings listed in Ta-
ble 11, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 11. Absolute Maximum Ratings
M58LW032A30/61
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 12,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Table 13. Capacitance Note:1. TA = 25°C, f = 1 MHz Sampled only, not 100% tested.
31/61
M58LW032A
Table 14. DC Characteristics
