M58LR128FB85ZB6 ,128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash MemoryLogic Diagram . . 7Table 1. Signal Names . . 7Figure 3. VFBGA Connections (Top view t ..
M58LR128GB85ZB5 , 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M58LT128GSB1ZA5E , 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5 , 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128HSB8ZA6 , 128 Mbit (8 Mb ×16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories
M58LT128HST8ZA6E , 128-Mbit (8 Mb ×16, Multiple Bank, Multilevel interface, Burst) 1.8 V supply, Secure Flash memories
M95160-RMN6TP ,16 Kbit SPI bus EEPROM with high-speed clockfeatures . 135.1 Supply voltage (V ) 13CC5.1.1 Operating supply voltage (V ) . . . . ..
M95160-WBN6 ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKBlock Diagram . 11INSTRUCTIONS . . 12Table 5. Instruction Set . 12Write Enabl ..
M95160-WDW6TP ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95160-WMN3 ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95160-WMN3T/W ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95160WMN3TP/S ,Automotive 16 Kbit serial SPI bus EEPROMFeatures■ Compatible with the Serial Peripheral Interface (SPI) bus■ Memory array– 16 Kb (2 Kbytes) ..
M58LR128FB85ZB6
128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
1/82September 2004
M58LR128FT
M58LR128FB128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)
1.8V Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VDD = 1.7V to 2.0V for program, erase and
read
–VDDQ = 1.7V to 2.0V for I/O Buffers
–VPP = 9V for fast program (12V tolerant) SYNCHRONOUS / ASYNCHRONOUS READ Synchronous Burst Read mode: 54MHz Asynchronous Page Read mode Random Access: 85, 95ns SYNCHRONOUS BURST READ SUSPEND PROGRAMMING TIME 10µs typical Word program time using
Buffer Program MEMORY ORGANIZATION Multiple Bank Memory Array: 8 Mbit
Banks Parameter Blocks (Top or Bottom
location) DUAL OPERATIONS program/erase in one Bank while read in
others No delay between read and write
operations BLOCK LOCKING All blocks locked at power-up Any combination of blocks can be locked
with zero latency
–WP for Block Lock-Down Absolute Write Protection with VPP = VSS SECURITY 64 bit unique device number 2112 bit user programmable OTP Cells COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per
BLOCK
M58LR128FT, M58LR128FB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3. VFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3/82
M58LR128FT, M58LR128FB
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Buffer Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Buffer Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 6. Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 7. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 8. Protection Register Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Burst length Bits (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 10. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 11. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
M58LR128FT, M58LR128FB
READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 12. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 13. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 14. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Table 15. Program, Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Table 16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Table 17. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 18. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 19. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 20. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 10.Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 11.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 21. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 13.Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 14.Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 15.Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 22. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 16.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 23. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 17.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 24. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 18.Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 25. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5/82
M58LR128FT, M58LR128FB
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52Figure 19.VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Bottom View Package Outline. . . .52
Table 26. VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Package Mechanical Data. . . . . . .52
Figure 20.VFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . .53
Figure 21.VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . .54
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 28. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56Table 29. Top Boot Block Addresses, M58LR128FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 30. Bottom Boot Block Addresses, M58LR128FB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Table 31. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 32. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 33. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 34. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 35. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 36. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 37. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 38. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 39. Bank and Erase Block Region 1 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 40. Bank and Erase Block Region 2 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 23.Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 24.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .70
Figure 25.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 26.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 27.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 28.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . .74
Figure 29.Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . .75
APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76Table 41. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 42. Command Interface States - Modify Table, Next Output State . . . . . . . . . . . . . . . . . . . .78
Table 43. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 44. Command Interface States - Lock Table, Next Output State. . . . . . . . . . . . . . . . . . . . . .80
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Table 45. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
M58LR128FT, M58LR128FB
SUMMARY DESCRIPTIONThe M58LR128FT/B is a 128 Mbit (8Mbit x16)
non-volatile Flash memory that may be erased
electrically at block level and programmed in-sys-
tem on a Word-by-Word basis using a 1.7V to 2.0V
VDD supply for the circuitry and a 1.7V to 2.0V
VDDQ supply for the Input/Output pins. An optional
9V VPP power supply is provided to speed up fac-
tory programming.
The device features an asymmetrical block archi-
tecture and is based on a multi-level cell technolo-
gy. M58LR128FT/B has an array of 131 blocks,
and is divided into 8 Mbit banks. There are 15
banks each containing 8 main blocks of 64
KWords, and one parameter bank containing 4 pa-
rameter blocks of 16 KWords and 7 main blocks of
64 KWords. The Multiple Bank Architecture allows
Dual Operations, while programming or erasing in
one bank, read operations are possible in other
banks. Only one bank at a time is allowed to be in
program or erase mode. It is possible to perform
burst reads that cross bank boundaries. The bank
architecture is summarized in Table 2., and the
memory maps are shown in Figure 4. The Param-
eter Blocks are located at the top of the memory
address space for the M58LR128FT, and at the
bottom for the M58LR128FB.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage VDD. There is a Buffer Enhanced Factory
programming command available to speed up pro-
gramming.
Program and erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The device supports Synchronous Burst Read and
Asynchronous Read from all blocks of the memory
array; at power-up the device is configured for
Asynchronous Read. In Synchronous Burst Read
mode, data is output on each clock cycle at fre-
quencies of up to 54MHz. The Synchronous Burst
Read operation can be suspended and resumed.
The device features an Automatic Standby mode.
When the bus is inactive during Asynchronous
Read operations, the device automatically switch-
es to the Automatic Standby mode. In this condi-
tion the power consumption is reduced to the
standby value and the outputs are still driven.
The M58LR128FT/B features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at power-
up.
The device includes 17 Protection Registers and 2
Protection Register locks, one for the first Protec-
tion Register and the other for the 16 One-Time-
Programmable (OTP) Protection Registers of 128
bits each. The first Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 64 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected. Figure 5., shows the Pro-
tection Register Memory Map.
The memory is available in a VFBGA56, 7.7x9mm,
0.75 pitch package and is supplied with all the bits
erased (set to ’1’).
7/82
M58LR128FT, M58LR128FB Table 1. Signal Names
M58LR128FT, M58LR128FB
9/82
M58LR128FT, M58LR128FB
M58LR128FT, M58LR128FB
SIGNAL DESCRIPTIONSSee Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Bus Write
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable or Write Enable
whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the Lock-
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or un-
locked. (refer to Table 14., Lock Status).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at VIL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is re-
duced to the Reset Supply Current IDD2. Refer to
Table 19., DC Characteristics - Currents, for the
value of IDD2. After Reset all blocks are in the
Locked state and the Configuration Register is re-
set. When Reset is at VIH, the device is in normal
operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 20., DC Characteristics - Voltages).
Latch Enable (L). Latch Enable latches the ad-
dress bits on its rising edge. The address
latch is transparent when Latch Enable is at
VIL and it is inhibited when Latch Enable is at
VIH. Latch Enable can be kept Low (also at
board level) when the Latch Enable function
is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at VIL. Clock is
ignored during asynchronous read and in write op-
erations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable is at VIH, Output Enable is
at VIH, or Reset is at VIL. It can be configured to be
active during the wait cycle or one clock cycle in
advance.
VDD Supply Voltage . VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin.
If VPP is kept in a low voltage range (0V to VDDQ)
VPP is seen as a control input. In this case a volt-
age lower than VPPLK gives an absolute protection
against program or erase, while VPP > VPP1 en-
ables these functions (see Tables 19 and 20, DC
Characteristics for the relevant values). VPP is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If VPP is in the range of VPPH it acts as a power
supply pin. In this condition VPP must be stable un-
til the Program/Erase algorithm is completed.
VSS Ground. VSS ground is the reference for the
core supply. It must be connected to the system
ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1µF ce-
ramic capacitor close to the pin (high frequen-
cy, inherently low inductance capacitors
11/82
M58LR128FT, M58LR128FB
should be as close as possible to the pack-
age). See Figure 9., AC Measurement Load Cir-
cuit. The PCB trace widths should be sufficient
to carry the required VPP program and erase
currents.
BUS OPERATIONSThere are six standard bus operations that control
the device. These are Bus Read, Bus Write, Ad-
dress Latch, Output Disable, Standby and Reset.
See Table 3., Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
See Figures 10, 11, 12 and 13 Read AC Wave-
forms, and Tables 21 and 22 Read AC Character-
istics, for details of when the output becomes
valid.
Bus Write. Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at VIL with
Output Enable at VIH. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the
bus write operation.
See Figures 16 and 17, Write AC Waveforms, and
Tables 23 and 24, Write AC Characteristics, for
details of the timing requirements.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at VIL during address latch opera-
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high imped-
ance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in standby when
Chip Enable and Reset are at VIH. The power con-
sumption is reduced to the standby level IDD4 and
the outputs are set to high impedance, indepen-
dently from the Output Enable or Write Enable in-
puts. If Chip Enable switches to VIH during a
program or erase operation, the device enters
Standby mode when finished.
Reset. During Reset mode the memory is dese-
lected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL.
The power consumption is reduced to the Standby
level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to
VSS during a Program or Erase, this operation is
aborted and the memory content is no longer valid.
Table 3. Bus Operations Note:1. X = Don't care. L can be tied to VIH if the valid address has been previously latched. Depends on G. WAIT signal polarity is configured using the Set Configuration Register command.
M58LR128FT, M58LR128FB
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the program and erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
The Command Interface is reset to read mode
when power is first applied, when exiting from Re-
set or whenever VDD is lower than VLKO. Com-
mand sequences must be followed exactly. Any
invalid combination of commands will be ignored.
Refer to Table 4., Command Codes, Table
5., Standard Commands, and Table 6., Factory
Program Command, for a summary of the Com-
mand Interface.
Table 4. Command Codes
Read Array CommandThe Read Array command returns the addressed
bank to Read Array mode.
One Bus Write cycle is required to issue the Read
Array command. Once a bank is in Read Array
mode, subsequent read operations will output the
data from the memory array.
A Read Array command can be issued to any
banks while programming or erasing in another
bank.
If the Read Array command is issued to a bank
currently executing a program or erase operation,
the bank will return to Read Array mode but the
program or erase operation will continue, however
the data output from the bank is not guaranteed
until the program or erase operation has finished.
The read modes of other banks are not affected.
Read Status Register CommandThe device contains a Status Register that is used
to monitor program or erase operations.
The Read Status Register command is used to
read the contents of the Status Register for the ad-
dressed bank.
One Bus Write cycle is required to issue the Read
Status Register command. Once a bank is in Read
Status Register mode, subsequent read opera-
tions will output the contents of the Status Regis-
ter.
The Status Register data is latched on the falling
edge of the Chip Enable or Output Enable signals.
Either Chip Enable or Output Enable must be tog-
gled to update the Status Register data
The Read Status Register command can be is-
sued at any time, even during program or erase
operations. The Read Status Register command
will only change the read mode of the addressed
bank. The read modes of other banks are not af-
fected. Only Asynchronous Read and Single Syn-
chronous Read operations should be used to read
the Status Register. A Read Array command is re-
quired to return the bank to Read Array mode.
See Table 9. for the description of the Status Reg-
ister Bits.
Read Electronic Signature Command The Read Electronic Signature command is used
to read the Manufacturer and Device Codes, the
Lock Status of the addressed bank, the Protection
Register, and the Configuration Register.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once a bank is in
Read Electronic Signature mode, subsequent
read operations in the same bank will output the
Manufacturer Code, the Device Code, the Lock
13/82
M58LR128FT, M58LR128FBStatus of the addressed bank, the Protection Reg-
ister, or the Configuration Register (see Table 7.).
The Read Electronic Signature command can be
issued at any time, even during program or erase
operations, except during Protection Register Pro-
gram operations.
If a Read Electronic Signature command is issued
to a bank that is executing a program or erase op-
eration the bank will go into Read Electronic Sig-
nature mode. Subsequent Bus Read cycles will
output the Electronic Signature data and the Pro-
gram/Erase controller will continue to program or
erase in the background.
The Read Electronic Signature command will only
change the read mode of the addressed bank. The
read modes of other banks are not affected. Only
Asynchronous Read and Single Synchronous
Read operations should be used to read the Elec-
tronic Signature. A Read Array command is re-
quired to return the bank to Read Array mode.
Read CFI Query Command The Read CFI Query command is used to read
data from the Common Flash Interface (CFI).
One Bus Write cycle is required to issue the Read
CFI Query command. Once a bank is in Read CFI
Query mode, subsequent Bus Read operations in
the same bank read from the Common Flash Inter-
face.
The Read CFI Query command can be issued at
any time, even during program or erase opera-
tions.
If a Read CFI Query command is issued to a bank
that is executing a program or erase operation the
bank will go into Read CFI Query mode. Subse-
quent Bus Read cycles will output the CFI data
and the Program/Erase controller will continue to
program or erase in the background.
The Read CFI Query command will only change
the read mode of the addressed bank. The read
modes of other banks are not affected. Only Asyn-
chronous Read and Single Synchronous Read op-
erations should be used to read from the CFI. A
Read Array command is required to return the
bank to Read Array mode.
See APPENDIX B., COMMON FLASH INTER-
FACE, Tables 31, 32, 33, 34, 35, 37, 38, 39 and 40
for details on the information contained in the
Common Flash Interface memory area.
Clear Status Register CommandThe Clear Status Register command can be used
to reset (set to ‘0’) all error bits (SR1, 3, 4 and 5) in
the Status Register.
One Bus Write cycle is required to issue the Clear
Status Register command. The Clear Status Reg-
ister command does not change the read mode of
the addressed bank.
The error bits in the Status Register do not auto-
matically return to ‘0’ when a new command is is-
sued. The error bits in the Status Register should
be cleared before attempting a new program or
erase command.
Block Erase CommandThe Block Erase command is used to erase a
block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost.
If the block is protected then the erase operation
will abort, the data in the block will not be changed
and the Status Register will output the error.
Two Bus Write cycles are required to issue the
command. The first bus cycle sets up the Block Erase
command. The second latches the block address and
starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Con-
firm code, Status Register bits SR4 and SR5 are
set and the command is aborted.
Once the command is issued the bank enters
Read Status Register mode and any read opera-
tion within the addressed bank will output the con-
tents of the Status Register. A Read Array
command is required to return the bank to Read
Array mode.
During Block Erase operations the bank contain-
ing the block being erased will only accept the
Read Array, Read Status Register, Read Electron-
ic Signature, Read CFI Query and the Program/
Erase Suspend command, all other commands
will be ignored.
The Block Erase operation aborts if Reset, RP,
goes to VIL. As data integrity cannot be guaran-
teed when the Block Erase operation is aborted,
the block must be erased again.
Refer to Dual Operations section for detailed infor-
mation about simultaneous operations allowed in
banks not being erased.
Typical Erase times are given in Table
15., Program, Erase Times and Endurance Cy-
cles.
See APPENDIX C., Figure 25., Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
for using the Block Erase command.
Program CommandThe program command is used to program a sin-
gle Word to the memory array.
Two Bus Write cycles are required to issue the
Program Command. The first bus cycle sets up the Program
command.
M58LR128FT, M58LR128FB The second latches the address and data to
be programmed and starts the Program/Erase
Controller.
Once the programming has started, read opera-
tions in the bank being programmed output the
Status Register content.
During a Program operation, the bank containing
the Word being programmed will only accept the
Read Array, Read Status Register, Read Electron-
ic Signature, Read CFI Query and the Program/
Erase Suspend command, all other commands
will be ignored. A Read Array command is re-
quired to return the bank to Read Array mode.
Refer to Dual Operations section for detailed infor-
mation about simultaneous operations allowed in
banks not being programmed.
Typical Program times are given in Table
15., Program, Erase Times and Endurance Cy-
cles.
The Program operation aborts if Reset, RP , goes
to VIL. As data integrity cannot be guaranteed
when the Program operation is aborted, the Word
must be reprogrammed.
See APPENDIX C., Figure 22., Program Flow-
chart and Pseudo Code, for the flowchart for using
the Program command.
Buffer Program CommandThe Buffer Program Command makes use of the
device’s 32-Word Write Buffer to speed up pro-
gramming. Up to 32 Words can be loaded into the
Write Buffer. The Buffer Program command dra-
matically reduces in-system programming time
compared to the standard non-buffered Program
command.
Four successive steps are required to issue the
Buffer Program command. The first Bus Write cycle sets up the Buffer
Program command. The setup code can be
addressed to any location within the targeted
block.
After the first Bus Write cycle, read operations in
the bank will output the contents of the Status
Register. Status Register bit SR7 should be read
to check that the buffer is available (SR7 = 1). If
the buffer is not available (SR7 = 0), re-issue the
Buffer Program command to update the Status
Register contents. The second Bus Write cycle sets up the
number of Words to be programmed. Value n
is written to the same block address, where
n+1 is the number of Words to be
programmed. Use n+1 Bus Write cycles to load the address
and data for each Word into the Write Buffer.
Addresses must lie within the range from the
start address to the start address + n.
Optimum performance is obtained when the
start address corresponds to a 32 Word
boundary. If the start address is not aligned to
a 32 word boundary, the total programming
time is doubled The final Bus Write cycle confirms the Buffer
Program command and starts the program
operation.
All the addresses used in the Buffer Program op-
eration must lie within the same block.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper-
ation without affecting the data in the memory ar-
ray.
If the Status Register bits SR4 and SR5 are set to
'1', the Buffer Program Command is not accepted.
Clear the Status Register before re-issuing the
command.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array.
During Buffer Program operations the bank being
programmed will only accept the Read Array,
Read Status Register, Read Electronic Signature,
Read CFI Query and the Program/Erase Suspend
command, all other commands will be ignored.
Refer to Dual Operations section for detailed infor-
mation about simultaneous operations allowed in
banks not being programmed.
See Appendix C, figure 27, Buffer Program Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Buffer Program command.
Buffer Enhanced Factory Program CommandThe Buffer Enhanced Factory Program command
has been specially developed to speed up pro-
gramming in manufacturing environments where
the programming time is critical.
It is used to program one or more Write Buffer(s)
of 32 Words to a block. Once the device enters
Buffer Enhanced Factory Program mode, the
Write Buffer can be reloaded any number of times
as long as the address remains within the same
block. Only one block can be programmed at a
time.
The use of the Buffer Enhanced Factory Program
command requires certain operating conditions: VPP must be set to VPPH VDD must be within operating range Ambient temperature, TA must be 25°C ± 5°C The targeted block must be unlocked The start address must be aligned with the
start of a 32 Word buffer boundary
15/82
M58LR128FT, M58LR128FB The address must remain the Start Address
throughout programming.
Dual operations are not supported during the Buff-
er Enhanced Factory Program operation and the
command cannot be suspended.
The Buffer Enhanced Factory Program Command
consists of three phases: the Setup Phase, the
Program and Verify Phase, and the Exit Phase,
Please refer to Table 7. Factory Program Com-
mands for detail information.
Refer to Table 6., Factory Program Command,
and Figure 29., Buffer Enhanced Factory Program
Flowchart and Pseudo Code.
Setup Phase. The Buffer Enhanced Factory Pro-
gram command requires two Bus Write cycles to
initiate the command. The first Bus Write cycle sets up the Buffer
Enhanced Factory Program command. The second Bus Write cycle confirms the
command.
After the confirm command is issued, read opera-
tions output the contents of the Status Register.
The read Status Register command must not be
issued as it will be interpreted as data to program.
The Status Register P/E.C. Bit SR7 should be
read to check that the P/E.C. is ready to proceed
to the next phase.
If an error is detected, SR4 goes high (set to ‘1’)
and the Buffer Enhanced Factory Program opera-
tion is terminated. See Status Register section for
details on the error.
Program and Verify Phase. The Program and
Verify Phase requires 32 cycles to program the 32
Words to the Write Buffer. The data is stored se-
quentially, starting at the first address of the Write
Buffer, until the Write Buffer is full (32 Words). To
program less than 32 Words, the remaining Words
should be programmed with FFFFh.
Three successive steps are required to issue and
execute the Program and Verify Phase of the com-
mand. Use one Bus Write operation to latch the Start
Address and the first Word to be programmed.
The Status Register Bank Write Status bit SR0
should be read to check that the P/E.C. is
ready for the next Word. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address must remain the Start Address as the
P/E.C. increments the address location.If any
address that is not in the same block as the
Start Address is given, the Program and Verify
Phase terminates. Status Register bit SR0
should be read between each Bus Write cycle
to check that the P/E.C. is ready for the next
Word. Once the Write Buffer is full, the data is pro-
grammed sequentially to the memory array.
After the program operation the device auto-
matically verifies the data and reprograms if
necessary.
The Program and Verify phase can be repeated,
without re-issuing the command, to program addi-
tional 32 Word locations as long as the address re-
mains in the same block. Finally, after all Words, or the entire block
have been programmed, write one Bus Write
operation to any address outside the block
containing the Start Address, to terminate
Program and Verify Phase.
Status Register bit SR0 must be checked to deter-
mine whether the program operation is finished.
The Status Register may be checked for errors at
any time but it must be checked after the entire
block has been programmed.
Exit Phase. Status Register P/E.C. bit SR7 set to
‘1’ indicates that the device has exited the Buffer
Enhanced Factory Program operation and re-
turned to Read Status Register mode. A full Status
Register check should be done to ensure that the
block has been successfully programmed. See the
section on the Status Register for more details.
For optimum performance the Buffer Enhanced
Factory Program command should be limited to a
maximum of 100 program/erase cycles per block.
If this limit is exceeded the internal algorithm will
continue to work properly but some degradation in
performance is possible. Typical program times
are given in Table 15..
See APPENDIX C., Figure 29., Buffer Enhanced
Factory Program Flowchart and Pseudo Code, for
a suggested flowchart on using the Buffer En-
hanced Factory Program command.
Program/Erase Suspend Command The Program/Erase Suspend command is used to
pause a Program or Block Erase operation. The
command can be addressed to any bank.
The Program/Erase Resume command is re-
quired to restart the suspended operation.
One bus write cycle is required to issue the Pro-
gram/Erase Suspend command. Once the Pro-
gram/Erase Controller has paused bits SR7, SR6
and/ or SR2 of the Status Register will be set to ‘1’.
The following commands are accepted during Pro-
gram/Erase Suspend: Program/Erase Resume Read Array (data from erase-suspended
block or program-suspended Word is not
valid) Read Status Register Read Electronic Signature
M58LR128FT, M58LR128FB Read CFI Query.
Additionally, if the suspended operation was erase
then the following commands are also accepted: Clear Status Register Program (except in erase-suspended
block) Block Lock Block Lock-Down Block Unlock.
During an erase suspend the block being erased
can be protected by issuing the Block Lock or
Block Lock-Down commands. When the Program/
Erase Resume command is issued the operation
will complete.
It is possible to accumulate multiple suspend oper-
ations. For example: suspend an erase operation,
start a program operation, suspend the program
operation, then read the array.
If a Program command is issued during a Block
Erase Suspend, the erase operation cannot be re-
sumed until the program operation has completed.
The Program/Erase Suspend command does not
change the read mode of the banks. If the sus-
pended bank was in Read Status Register, Read
Electronic signature or Read CFI Query mode the
bank remains in that mode and outputs the corre-
sponding data.
Refer to Dual Operations section for detailed infor-
mation about simultaneous operations allowed
during Program/Erase Suspend.
During a Program/Erase Suspend, the device can
be placed in standby mode by taking Chip Enable
to VIH. Program/erase is aborted if Reset, RP,
goes to VIL.
See APPENDIX C., Figure 24., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 26., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Suspend command.
Program/Erase Resume Command The Program/Erase Resume command is used to
restart the program or erase operation suspended
by the Program/Erase Suspend command. One
Bus Write cycle is required to issue the command.
The command can be issued to any address.
The Program/Erase Resume command does not
change the read mode of the banks. If the sus-
pended bank was in Read Status Register, Read
Electronic signature or Read CFI Query mode the
bank remains in that mode and outputs the corre-
sponding data.
If a Program command is issued during a Block
Erase Suspend, then the erase cannot be re-
sumed until the program operation has completed.
See APPENDIX C., Figure 24., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 26., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Resume command.
Protection Register Program CommandThe Protection Register Program command is
used to program the user One-Time-Programma-
ble (OTP) segments of the Protection Register and
the two Protection Register Locks.
The device features 16 OTP segments of 128 bits
and one OTP segment of 64 bits, as shown in Fig-
ure 5., Protection Register Memory Map.
The segments are programmed one Word at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two Bus Write cycles are required to issue the
Protection Register Program command. The first bus cycle sets up the Protection
Register Program command. The second latches the address and data to
be programmed to the Protection Register and
starts the Program/Erase Controller.
Read operations to the bank being programmed
output the Status Register content after the pro-
gram operation has started.
Attempting to program a previously protected Pro-
tection Register will result in a Status Register er-
ror.
The Protection Register Program cannot be sus-
pended.
The two Protection Register Locks are used to
protect the OTP segments from further modifica-
tion. The protection of the OTP segments is not re-
versible. Refer to Figure 5., Protection Register
Memory Map, and Table 8., Protection Register
Locks, for details on the Lock bits.
See APPENDIX C., Figure 28., Protection Regis-
ter Program Flowchart and Pseudo Code, for a
flowchart for using the Protection Register Pro-
gram command.
Set Configuration Register CommandThe Set Configuration Register command is used
to write a new value to the Configuration Register.
Two Bus Write cycles are required to issue the Set
Configuration Register command. The first cycle sets up the Set Configuration
Register command and the address
corresponding to the Configuration Register
content. The second cycle writes the Configuration
Register data and the confirm command.
The Configuration Register data must be written
as an address during the bus write cycles, that is
17/82
M58LR128FT, M58LR128FBA0 = CR0, A1 = CR1, …, A15 = CR15. Addresses
A16- A22 are ignored.
Once the Set Configuration Register command
has been issued, read operations will output the
array contents.
The Read Electronic Signature command is re-
quired to read the updated contents of the Config-
uration Register.
Block Lock CommandThe Block Lock command is used to lock a block
and prevent program or erase operations from
changing the data in it. All blocks are locked after
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command. The first bus cycle sets up the Block Lock
command. The second Bus Write cycle latches the block
address and locks the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 14. shows the Lock Status after issuing a
Block Lock command.
Once set, the Block Lock bits remain set until a
hardware reset or power-down/power-up. They
are cleared by a Block Unlock command.
Refer to the section, Block Locking, for a detailed
explanation. See APPENDIX C., Figure
27., Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Lock command.
Block Unlock CommandThe Block Unlock command is used to unlock a
block, allowing the block to be programmed or
erased.
Two Bus Write cycles are required to issue the
Block Unlock command. The first bus cycle sets up the Block Unlock
command. The second Bus Write cycle latches the block
address and unlocks the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 14. shows the protection status after issuing
a Block Unlock command.
Refer to the section, Block Locking, for a detailed
explanation and APPENDIX C., Figure
27., Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Block Unlock
command.
Block Lock-Down CommandThe Block Lock-Down command is used to lock-
down a locked or unlocked block.
A locked-down block cannot be programmed or
erased. The lock status of a locked-down block
cannot be changed when WP is low, VIL. When
WP is high, VIH, the lock-down function is disabled
and the locked blocks can be individually unlocked
by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock-Down command. The first bus cycle sets up the Block Lock-
Down command. The second Bus Write cycle latches the block
address and locks-down the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table 14. shows the Lock Status af-
ter issuing a Block Lock-Down command.
Refer to the section, Block Locking, for a detailed
explanation and APPENDIX C., Figure
27., Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Lock-Down
command.
M58LR128FT, M58LR128FB
Table 5. Standard CommandsNote:1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data,
QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection
Register Data, CRD=Configuration Register Data. Must be same bank as in the first cycle. The signature addresses are listed in Table 7. Any address within the bank can be used. n+1 is the number of Words to be programmed.
19/82
M58LR128FT, M58LR128FB
Table 6. Factory Program CommandNote:1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address, X = Don’t Care. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block. Any address within the bank can be used.
Table 7. Electronic Signature CodesNote: CR = Configuration Register, PRLD = Protection Register Lock Data.
M58LR128FT, M58LR128FB
21/82
M58LR128FT, M58LR128FB
Table 8. Protection Register Locks
M58LR128FT, M58LR128FB
STATUS REGISTERThe Status Register provides information on the
current or previous program or erase operations.
Issue a Read Status Register command to read
the contents of the Status Register, refer to Read
Status Register Command section for more de-
tails. To output the contents, the Status Register is
latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be
read until Chip Enable or Output Enable returns to
VIH. The Status Register can only be read using
single Asynchronous or Single Synchronous
reads. Bus Read operations from any address
within the bank, always read the Status Register
during program and erase operations.
The various bits convey information about the sta-
tus and any errors of the operation. Bits SR7, SR6,
SR2 and SR0 give information on the status of the
device and are set and reset by the device. Bits
SR5, SR4, SR3 and SR1 give information on er-
rors, they are set by the device but must be reset
by issuing a Clear Status Register command or a
hardware reset. If an error bit is set to ‘1’ the Status
Register should be reset before issuing another
command.
The bits in the Status Register are summarized in
Table 9., Status Register Bits. Refer to Table 9. in
conjunction with the following text descriptions.
Program/Erase Controller Status Bit (SR7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive in any bank.
When the Program/Erase Controller Status bit is
Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Pro-
gram/Erase Controller is inactive, and the device
is ready to process a new command.
The Program/Erase Controller Status bit is Low
immediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
Erase Suspend Status Bit (SR6). The Erase
Suspend Status bit indicates that an erase opera-
tion has been suspended in the addressed block.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro-
gram/Erase Resume command.
The Erase Suspend Status bit should only be con-
sidered valid when the Program/Erase Controller
Status bit is High (Program/Erase Controller inac-
tive). SR6 is set within the Erase Suspend Latency
time of the Program/Erase Suspend command be-
ing issued therefore the memory may still com-
plete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status Bit (SR5). The Erase Status bit is
used to identify if there was an error during a block
or bank erase operation. When the Erase Status
bit is High (set to ‘1’), the Program/Erase Control-
ler has applied the maximum number of pulses to
the block or bank and still failed to verify that it has
erased correctly.
The Erase Status bit should be read once the Pro-
gram/Erase Controller Status bit is High (Program/
Erase Controller inactive).
Once set High, the Erase Status bit must be set
Low by a Clear Status Register command or a
hardware reset before a new erase command is is-
sued, otherwise the new command will appear to
fail.
Program Status Bit (SR4). The Program Status
bit is used to identify if there was an error during a
program operation.
The Program Status bit should be read once the
Program/Erase Controller Status bit is High (Pro-
gram/Erase Controller inactive).
When the Program Status bit is High (set to ‘1’),
the Program/Erase Controller has applied the
maximum number of pulses to the Word and still
failed to verify that it has programmed correctly.
Attempting to program a '1' to an already pro-
grammed bit while VPP = VPPH will also set the
Program Status bit High. If VPP is different from
VPPH, SR4 remains Low (set to '0') and the attempt
is not shown.
Once set High, the Program Status bit must be set
Low by a Clear Status Register command or a
hardware reset before a new program command is
issued, otherwise the new command will appear to
fail.
VPP Status Bit (SR3). The VPP Status bit is used
to identify an invalid voltage on the VPP pin during
program and erase operations. The VPP pin is only
sampled at the beginning of a program or erase
operation. Program and erase operations are not
guaranteed if VPP becomes invalid during an oper-
ation.
When the VPP Status bit is Low (set to ‘0’), the volt-
age on the VPP pin was sampled at a valid voltage.
when the VPP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the VPP Lockout
Voltage, VPPLK, the memory is protected and pro-
gram and erase operations cannot be performed.
Once set High, the VPP Status bit must be set Low
by a Clear Status Register command or a hard-
ware reset before a new program or erase com-
mand is issued, otherwise the new command will
appear to fail.
23/82
M58LR128FT, M58LR128FB
Program Suspend Status Bit (SR2). The Pro-
gram Suspend Status bit indicates that a program
operation has been suspended in the addressed
block. The Program Suspend Status bit should
only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
When the Program Suspend Status bit is High (set
to ‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro-
gram/Erase Resume command.
SR2 is set within the Program Suspend Latency
time of the Program/Erase Suspend command be-
ing issued therefore the memory may still com-
plete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status Bit (SR1). The Block
Protection Status bit is used to identify if a Pro-
gram or Block Erase operation has tried to modify
the contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a program or erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit
must be set Low by a Clear Status Register com-
mand or a hardware reset before a new program
or erase command is issued, otherwise the new
command will appear to fail.
Bank Write/Multiple Word Program Status Bit
(SR0). The Bank Write Status bit indicates wheth-
er the addressed bank is programming or erasing.
In Buffer Enhanced Factory Program mode the
Multiple Word Program bit shows if the device is
ready to accept a new Word to be programmed to
the memory array.
The Bank Write Status bit should only be consid-
ered valid when the Program/Erase Controller Sta-
tus SR7 is Low (set to ‘0’).
When both the Program/Erase Controller Status bit
and the Bank Write Status bit are Low (set to ‘0’),
the addressed bank is executing a program or
erase operation. When the Program/Erase Con-
troller Status bit is Low (set to ‘0’) and the Bank
Write Status bit is High (set to ‘1’), a program or
erase operation is being executed in a bank other
than the one being addressed.
In Buffer Enhanced Factory Program mode if Mul-
tiple Word Program Status bit is Low (set to ‘0’),
the device is ready for the next Word, if the Multi-
ple Word Program Status bit is High (set to ‘1’) the
device is not ready for the next Word.
For further details on how to use the Status Regis-
ter, see the Flowcharts and Pseudocodes provid-
ed in APPENDIX C.
M58LR128FT, M58LR128FB
Table 9. Status Register BitsNote: Logic level '1' is High, '0' is Low.
25/82
M58LR128FT, M58LR128FB
CONFIGURATION REGISTERThe Configuration Register is used to configure
the type of bus access that the memory will per-
form. Refer to Read Modes section for details on
read operations.
The Configuration Register is set through the
Command Interface using the Set Configuration
Register command. After a reset or power-up the
device is configured for asynchronous read (CR15
= 1). The Configuration Register bits are described
in Table 10. They specify the selection of the burst
length, burst type, burst X latency and the read op-
eration. Refer to Figures 6 and 7 for examples of
synchronous burst configurations.
Read Select Bit (CR15)The Read Select bit, CR15, is used to switch be-
tween Asynchronous and Synchronous Read op-
erations.
When the Read Select bit is set to ’1’, read opera-
tions are asynchronous; when the Read Select bit
is set to ’0’, read operations are synchronous.
Synchronous Burst Read is supported in both pa-
rameter and main blocks and can be performed
across banks.
On reset or power-up the Read Select bit is set to
’1’ for asynchronous access (default).
X-Latency Bits (CR13-CR11)The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available.
For correct operation the X-Latency bits can only
assume the values in Table 10., Configuration
Register.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters. Two conditions must be satisfied: Depending on whether tAVK_CPU or tDELAY is
supplied either one of the following two
equations must be satisfied:
(n + 1) tK ≥ tAVQV - tAVK_CPU + tQVK_CPU
(n + 2) tK ≥ tAVQV + tDELAY + tQVK_CPU and also
tK > tKQV + tQVK_CPU
where n is the chosen X-Latency configuration code tK is the clock period tAVK_CPU is clock to address valid, L Low, or E
Low, whichever occurs last tDELAY is address valid, L Low, or E Low to
clock, whichever occurs last tQVK_CPU is the data setup time required by
the system CPU, tKQV is the clock to data valid time tAVQV is the random access time of the device.
Refer to Figure 6., X-Latency and Data Output
Configuration Example.
Wait Polarity Bit (CR10)The Wait Polarity bit is used to set the polarity of
the Wait signal used in Synchronous Burst Read
mode. During Synchronous Burst Read mode the
Wait signal indicates whether the data output are
valid or a WAIT state must be inserted.
When the Wait Polarity bit is set to ‘0’ the Wait sig-
nal is active Low. When the Wait Polarity bit is set
to ‘1’ the Wait signal is active High (default).
Data Output Configuration Bit (CR9)The Data Output Configuration bit is used to con-
figure the output to remain valid for either one or
two clock cycles during synchronous mode.
When the Data Output Configuration Bit is ’0’ the
output data is valid for one clock cycle, when the
Data Output Configuration Bit is ’1’ the output data
is valid for two clock cycles.
The Data Output Configuration must be config-
ured using the following condition: tK > tKQV + tQVK_CPU
where tK is the clock period tQVK_CPU is the data setup time required by
the system CPU tKQV is the clock to data valid time.
If this condition is not satisfied, the Data Output
Configuration bit should be set to ‘1’ (two clock cy-
cles). Refer to Figure 6., X-Latency and Data Out-
put Configuration Example.
Wait Configuration Bit (CR8)The Wait Configuration bit is used to control the
timing of the Wait output pin, WAIT, in Synchro-
nous Burst Read mode.
When WAIT is asserted, Data is Not Valid and
when WAIT is deasserted, Data is Valid.
When the Wait Configuration bit is Low (set to ’0’)
the Wait output pin is asserted during the wait
state. When the Wait Configuration bit is High (set
to ’1’) (default) the Wait output pin is asserted one
clock cycle before the wait state.
Burst Type Bit (CR7)The Burst Type bit determines the sequence of ad-
dresses read during Synchronous Burst Reads.
The Burst Type bit is High (set to ’1’), as the mem-
ory outputs from sequential addresses only.
M58LR128FT, M58LR128FBSee Table 11., Burst Type Definition, for the se-
quence of addresses output from a given starting
address in sequential mode.
Valid Clock Edge Bit (CR6)The Valid Clock Edge bit, CR6, is used to config-
ure the active edge of the Clock, K, during syn-
chronous read operations. When the Valid Clock
Edge bit is Low (set to ’0’) the falling edge of the
Clock is the active edge. When the Valid Clock
Edge bit is High (set to ’1’) the rising edge of the
Clock is the active edge.
Wrap Burst Bit (CR3)The Wrap Burst bit, CR3, is used to select be-
tween wrap and no wrap. Synchronous burst
reads can be confined inside the 4, 8 or 16 Word
boundary (wrap) or overcome the boundary (no
wrap).
When the Wrap Burst bit is Low (set to ‘0’) the
burst read wraps. When it is High (set to ‘1’) the
burst read does not wrap.
Burst length Bits (CR2-CR0)The Burst Length bits are used to set the number
of Words to be output during a Synchronous Burst
Read operation as result of a single address latch
cycle.
They can be set for 4 Words, 8 Words, 16 Words
or continuous burst, where all the Words are read
sequentially. In continuous burst mode the burst
sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16 Words no-
wrap, depending on the starting address, the de-
vice asserts the WAIT signal to indicate that a de-
lay is necessary before the data is output.
If the starting address is aligned to a 4 Word
boundary no wait states are needed and the WAIT
output is not asserted.
If the starting address is shifted by 1, 2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 16 Word boundary, to
indicate that the device needs an internal delay to
read the successive Words in the array. WAIT will
be asserted only once during a continuous burst
access. See also Table 11., Burst Type Definition.
CR14, CR5 and CR4 are reserved for future use.
27/82
M58LR128FT, M58LR128FB
Table 10. Configuration Register
M58LR128FT, M58LR128FB
Table 11. Burst Type Definition
29/82
M58LR128FT, M58LR128FB
M58LR128FT, M58LR128FB
READ MODESRead operations can be performed in two different
ways depending on the settings in the Configura-
tion Register. If the clock signal is ‘don’t care’ for
the data output, the read operation is asynchro-
nous; if the data output is synchronized with clock,
the read operation is synchronous.
The read mode and format of the data output are
determined by the Configuration Register. (See
Configuration Register section for details). All
banks support both asynchronous and synchro-
nous read operations.
Asynchronous Read ModeIn Asynchronous Read operations the clock signal
is ‘don’t care’. The device outputs the data corre-
sponding to the address latched, that is the mem-
ory array, Status Register, Common Flash
Interface or Electronic Signature depending on the
command issued. CR15 in the Configuration Reg-
ister must be set to ‘1’ for asynchronous opera-
tions.
Asynchronous Read operations can be performed
in two different ways, Asynchronous Random Ac-
cess Read and Asynchronous Page Read. Only
Asynchronous Page Read takes full advantage of
the internal page storage so different timings are
applied.
In Asynchronous Read mode a Page of data is in-
ternally read and stored in a Page Buffer. The
Page has a size of 4 Words and is addressed by
address inputs A0 and A1.
The first read operation within the Page has a
longer access time (tAVQV, Random access time),
subsequent reads within the same Page have
much shorter access times (tAVQV1, Page access
time). If the Page changes then the normal, longer
timings apply again.
The device features an Automatic Standby mode.
During Asynchronous Read operations, after a
bus inactivity of 150ns, the device automatically
switches to the Automatic Standby mode. In this
condition the power consumption is reduced to the
standby value and the outputs are still driven.
In Asynchronous Read mode, the WAIT signal is
always deasserted.
See Table 21., Asynchronous Read AC Charac-
teristics, Figure 10., Asynchronous Random Ac-
cess Read AC Waveforms, and Figure
11., Asynchronous Page Read AC Waveforms, for
details.
Synchronous Burst Read ModeIn Synchronous Burst Read mode the data is out-
put in bursts synchronized with the clock. It is pos-
sible to perform burst reads across bank
boundaries.
Synchronous Burst Read mode can only be used
to read the memory array. For other read opera-
tions, such as Read Status Register, Read CFI
and Read Electronic Signature, Single Synchro-
nous Read or Asynchronous Random Access
Read must be used.
In Synchronous Burst Read mode the flow of the
data output depends on parameters that are con-
figured in the Configuration Register.
A burst sequence starts at the first clock edge (ris-
ing or falling depending on Valid Clock Edge bit
CR6 in the Configuration Register) after the falling
edge of Latch Enable or Chip Enable, whichever
occurs last. Addresses are internally incremented
and data is output on each data cycle after a delay
which depends on the X latency bits CR13-CR11
of the Configuration Register.
The number of Words to be output during a Syn-
chronous Burst Read operation can be configured
as 4 Words, 8 Words, 16 Words or Continuous
(Burst Length bits CR2-CR0). The data can be
configured to remain valid for one or two clock cy-
cles (Data Output Configuration bit CR9).
The order of the data output can be modified
through the Wrap Burst bit in the Configuration
Register. The burst sequence is sequential and
can be confined inside the 4, 8 or 16 Word bound-
ary (Wrap) or overcome the boundary (No Wrap).
The WAIT signal may be asserted to indicate to
the system that an output delay will occur. This de-
lay will depend on the starting address of the burst
sequence and on the burst configuration.
WAIT is asserted during the X latency, the Wait
state and at the end of a 4, 8 and 16 Word burst. It
is only deasserted when output data are valid. In
Continuous Burst Read mode a Wait state will oc-
cur when crossing the first 16 Word boundary. If
the burst starting address is aligned to a 4 Word
Page, the Wait state will not occur.
The WAIT signal can be configured to be active
Low or active High by setting CR10 in the Config-
uration Register.
See Table 22., Synchronous Read AC Character-
istics, and Figure 12., Synchronous Burst Read
AC Waveforms, for details.
Synchronous Burst Read Suspend. A Syn-
chronous Burst Read operation can be suspend-
ed, freeing the data bus for other higher priority
devices. It can be suspended during the initial ac-
cess latency time (before data is output) in which
case the initial latency time can be reduced to ze-
ro, or after the device has output data. When the
Synchronous Burst Read operation is suspended,
internal array sensing continues and any previous-
ly latched internal data is retained. A burst se-
31/82
M58LR128FT, M58LR128FBquence can be suspended and resumed as often
as required as long as the operating conditions of
the device are met.
A Synchronous Burst Read operation is suspend-
ed when Chip Enable, E, is Low and the current
address has been latched (on a Latch Enable ris-
ing edge or on a valid clock edge). The Clock sig-
nal is then halted at VIH or at VIL, and Output
Enable, G, goes High.
When Output Enable, G, becomes Low again and
the Clock signal restarts, the Synchronous Burst
Read operation is resumed exactly where it
stopped.
WAIT will revert to high-impedance when Output
Enable, G, or Chip Enable, E, goes High.
See Table 22., Synchronous Read AC Character-
istics, and Figure 14., Synchronous Burst Read
Suspend AC Waveforms, for details.
Single Synchronous Read ModeSingle Synchronous Read operations are similar
to Synchronous Burst Read operations except that
the memory outputs the same data to the end of
the operation.
Synchronous Single Reads are used to read the
Electronic Signature, Status Register, CFI, Block
Protection Status, Configuration Register Status
or Protection Register. When the addressed bank
is in Read CFI, Read Status Register or Read
Electronic Signature mode, the WAIT signal is as-
serted during the X latency, the Wait state and at
the end of a 4, 8 and 16 Word burst. It is only deas-
serted when output data are valid.
See Table 22., Synchronous Read AC Character-
istics, and Figure 12., Synchronous Burst Read
AC Waveforms, for details.
M58LR128FT, M58LR128FB
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTUREThe Multiple Bank Architecture of the
M58LR128FT/B gives greater flexibility for soft-
ware developers to split the code and data spaces
within the memory array. The Dual Operations fea-
ture simplifies the software management of the de-
vice by allowing code to be executed from one
bank while another bank is being programmed or
erased.
The Dual Operations feature means that while pro-
gramming or erasing in one bank, read operations
are possible in another bank with zero latency
(only one bank at a time is allowed to be in pro-
gram or erase mode).
If a read operation is required in a bank, which is
programming or erasing, the program or erase op-
eration can be suspended.
Also if the suspended operation was erase then a
program command can be issued to another
block, so the device can have one block in Erase
Suspend mode, one programming and other
banks in read mode.
Bus Read operations are allowed in another bank
between setup and confirm cycles of program or
erase operations.
By using a combination of these features, read op-
erations are possible at any moment in the
M58LR128FT/B device.
Tables 12 and 13 show the dual operations possi-
ble in other banks and in the same bank.
Table 12. Dual Operations Allowed In Other Banks
Table 13. Dual Operations Allowed In Same BankNote:1. Not allowed in the Block or Word that is being erased or programmed. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
33/82
M58LR128FT, M58LR128FB
BLOCK LOCKINGThe M58LR128FT/B features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection. Lock/Unlock - this first level allows software
only control of block locking. Lock-Down - this second level requires
hardware interaction before locking can be
changed. VPP ≤ VPPLK - the third level offers a complete
hardware protection against program and
erase on all blocks.
The protection status of each block can be set to
Locked, Unlocked, and Locked-Down. Table 14.,
defines all of the possible protection states (WP,
DQ1, DQ0), and APPENDIX C., Figure 27., shows
a flowchart for the locking operations.
Reading a Block’s Lock StatusThe lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode issue the Read Electronic Signa-
ture command. Subsequent reads at the address
specified in Table 7., will output the protection sta-
tus of that block.
The lock status is represented by DQ0 and DQ1.
DQ0 indicates the Block Lock/Unlock status and is
set by the Lock command and cleared by the Un-
lock command. DQ0 is automatically set when en-
tering Lock-Down. DQ1 indicates the Lock-Down
status and is set by the Lock-Down command.
DQ1 cannot be cleared by software, only by a
hardware reset or power-down.
The following sections explain the operation of the
locking system.
Locked StateThe default status of all blocks on power-up or af-
ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
program or erase operations. Any program or
erase operations attempted on a locked block will
return an error in the Status Register. The Status
of a Locked block can be changed to Unlocked or
Locked-Down using the appropriate software
commands. An Unlocked block can be Locked by
issuing the Lock command.
Unlocked StateUnlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be un-
locked by issuing the Unlock command.
Lock-Down StateBlocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can-
not be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked-
Down blocks revert to the Locked state when the
device is reset or powered-down.
The Lock-Down function is dependent on the Write
Protect, WP, input pin.
When WP=0 (VIL), the blocks in the Lock-Down
state (0,1,x) are protected from program, erase
and protection status changes.
When WP=1 (VIH) the Lock-Down function is dis-
abled (1,1,x) and Locked-Down blocks can be in-
dividually unlocked to the (1,1,0) state by issuing
the software command, where they can be erased
and programmed.
When the Lock-Down function is disabled (WP=1)
blocks can be locked (1,1,1) and unlocked (1,1,0)
as desired. When WP=0 blocks that were previ-
ously Locked-Down return to the Lock-Down state
(0,1,x) regardless of any changes that were made
while WP=1.
Device reset or power-down resets all blocks, in-
cluding those in Lock-Down, to the Locked state.
Locking Operations During Erase SuspendChanges to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the Status Register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operations cannot be performed during a
program suspend.
M58LR128FT, M58LR128FB
Table 14. Lock Status Note:1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = VIH and A0 = VIL. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
35/82
M58LR128FT, M58LR128FB
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLESThe Program and Erase times and the number of
Program/ Erase cycles per block are shown in Ta-
ble 15. In the M58LR128FT/B the maximum num-
ber of Program/ Erase cycles depends on the
voltage supply used.
Table 15. Program, Erase Times and Endurance CyclesNote:1. TA = –40 to 85°C; VDD = 1.7V to 2.0V; VDDQ = 1.7V to 2.0V. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). Excludes the time needed to execute the command sequence. Average on entire device.
M58LR128FT, M58LR128FB
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 16. Absolute Maximum Ratings
37/82
M58LR128FT, M58LR128FB
DC AND AC PARAMETERSThis section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 17., Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 17. Operating and AC Measurement Conditions
Table 18. CapacitanceNote: Sampled only, not 100% tested.
M58LR128FT, M58LR128FB
Table 19. DC Characteristics - CurrentsNote:1. Sampled only, not 100% tested. VDD Dual Operation current is the sum of read and program or erase currents.
39/82
M58LR128FT, M58LR128FB
Table 20. DC Characteristics - Voltages
M58LR128FT, M58LR128FB
41/82
M58LR128FT, M58LR128FB
