M58CR032C100ZB6T ,32 Mbit 2Mb x 16, Dual Bank, Burst 1.8V Supply Flash MemoryLogic Diagram . . 7Table 1. Signal Names . . . 7Figure 3. TFBGA Connections (Top view ..
M58LR128FB85ZB6 ,128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash MemoryLogic Diagram . . 7Table 1. Signal Names . . 7Figure 3. VFBGA Connections (Top view t ..
M58LR128GB85ZB5 , 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M58LT128GSB1ZA5E , 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5 , 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128HSB8ZA6 , 128 Mbit (8 Mb ×16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories
M95160-RMN6TP ,16 Kbit SPI bus EEPROM with high-speed clockfeatures . 135.1 Supply voltage (V ) 13CC5.1.1 Operating supply voltage (V ) . . . . ..
M95160-WBN6 ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKBlock Diagram . 11INSTRUCTIONS . . 12Table 5. Instruction Set . 12Write Enabl ..
M95160-WDW6TP ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95160-WMN3 ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95160-WMN3T/W ,16KBIT AND 8KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95160WMN3TP/S ,Automotive 16 Kbit serial SPI bus EEPROMFeatures■ Compatible with the Serial Peripheral Interface (SPI) bus■ Memory array– 16 Kb (2 Kbytes) ..
M58CR032C100ZB6T
32 MBIT (2MB X16, DUAL BANK, BURST) 1.8V SUPPLY FLASH MEMORY
1/63
PRELIMINARY DATASeptember 2002
M58CR032C
M58CR032D32 Mbit (2Mb x 16, Dual Bank, Burst )
1.8V Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VDD = 1.65V to 2V for Program, Erase and
Read
–VDDQ = 1.65V to 3.3V for I/O Buffers
–VPP = 12V for fast Program (optional) SYNCHRONOUS / ASYNCHRONOUS READ Burst mode Read: 54MHz Page mode Read (4 Words Page) Random Access: 85, 100, 120 ns PROGRAMMING TIME 10μs by Word typical Double/Quadruple Word programming option MEMORY BLOCKS Dual Bank Memory Array: 8/24 Mbit Parameter Blocks (Top or Bottom location) DUAL OPERATIONS Read in one Bank while Program or Erase in
other No delay between Read and Write operations BLOCK LOCKING All blocks locked at Power up Any combination of blocks can be locked
–WP for Block Lock-Down SECURITY 64 bit user programmable OTP cells 64 bit unique device identifier One parameter block permanently lockable COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per
BLOCK
Figure 1. Packages ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M58CR032C: 88C8h Bottom Device Code, M58CR032D: 88C9h
M58CR032C, M58CR032D
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VDD Supply Voltage (1.65V to 2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VDDQ Supply Voltage (1.65V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VPP Program Supply Voltage (12V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VSS and VSSQ Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Asynchronous Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset/Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Synchronous Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6. Synchronous Single Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Power-Down Bit (M10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Wait Bit (M8).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/63
M58CR032C, M58CR032DWrap Burst Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst length Bits (M2-M0).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 4. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 5. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. X-Latency Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 8. Wait Configuration Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Read Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 6. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 7. Dual Bank Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 8. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 9. Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 10. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 11. Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 12. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . .26
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
M58CR032C, M58CR032DProgram Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 15. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Table 16. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 17. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 18. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 19. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 20. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 11. Asynchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 12. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 21. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 13. Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 22. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 14. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 23. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 15. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 24. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 16. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 25. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline. .45
Table 26. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data . . . . .45
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
APPENDIX A. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 30. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 31. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 32. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 33. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5/63
M58CR032C, M58CR032DTable 34. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 35. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
APPENDIX B. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Figure 18. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 19. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 20. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 21. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . .56
Figure 22. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . .58
Figure 24. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 25. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .60
APPENDIX C. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61Table 36. Command Interface States - Lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 37. Command Interface States - Modify Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
M58CR032C, M58CR032D
SUMMARY DESCRIPTIONThe M58CR032 is a 32 Mbit (2Mbit x16) non-vola-
tile Flash memory that may be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 1.65V to 2.0V VDD
supply for the circuitry and a 1.65V to 3.3V VDDQ
supply for the Input/Output pins. An optional 12V
VPP power supply is provided to speed up custom-
er programming. The VPP pin can also be used as
a control pin to provide absolute protection against
program or erase.
The device features an asymmetrical block archi-
tecture. M58CR032 has an array of 71 blocks and
is divided into two banks, Banks A and B, provid-
ing Dual Bank operations. While programming or
erasing in Bank A, read operations are possible in
Bank B or vice versa. Only one bank at a time is
allowed to be in program or erase mode. It is pos-
sible to perform burst reads that cross bank
boundaries. The bank architecture is summarized
in Table 2, and the memory maps are shown in
Figure 4. The Parameter Blocks are located at the
top of the memory address space for the
M58CR032C and at the bottom for the
M58CR032D.
Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
page mode read. In synchronous burst mode, data
is output on each clock cycle at frequencies of up
to 54MHz.
The M58CR032 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at Power
Up.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system’s design. The Protection Register is di-
vided into two 64 bit segments. The first segment
contains a unique device number written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user. Figure 5, shows the Security Block and
Protection Register Memory Map.
The memory is offered in a TFBGA56, 0.75 mm
ball pitch package and is supplied with all the bits
erased (set to ’1’).
7/63
M58CR032C, M58CR032D
Figure 2. Logic Diagram Table 1. Signal Names
M58CR032C, M58CR032D
Figure 3. TFBGA Connections (Top view through package)
Table 2. Bank Architecture
9/63
M58CR032C, M58CR032D
M58CR032C, M58CR032D
SIGNAL DESCRIPTIONSSee Figure 2 Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
The address inputs for the memory array are
latched on the rising edge of Latch Enable L. The
address latch is transparent when L is at VIL. In
synchronous operations the address is also
latched on the first rising/falling edge of K (de-
pending on clock configuration) when L is low.
During a Write operation the address is latched on
the rising edge of L or W, whichever occurs first.
Data Inputs/Outputs (DQ0-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Both input data and commands are latched on the
rising edge of Write Enable, W. When Chip En-
able, E, and Output Enable, G, are at VIL the data
bus outputs data from the Memory Array, the Elec-
tronic Signature, Manufacturer or Device codes,
the Block Protection Status, the Burst Configura-
tion Register, the Protection Register or the Status
Register. The data bus is high impedance when
the chip is deselected, Output Enable, G, is at VIH,
or Reset/Power-Down, RP , is at VIL.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable,
E, is at VIH, the memory is deselected and the
power consumption is reduced to the standby lev-
el. Chip Enable can also be used to control writing
to the Command Interface and to the memory ar-
ray, while Write Enable, W, remains at VIL.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When Output Enable, G, is at VIH the out-
puts are high impedance.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. Data are latched on the rising edge of
Write Enable.
Write Protect (WP). Write Protect is an input that
gives an additional hardware protection for each
block. When Write Protect is at VIL, the Lock-Down
is enabled and the protection status of the block
cannot be changed. When Write Protect is at VIH,
the Lock-Down is disabled and the block can be
locked or unlocked. (refer to Table 10, Read Pro-
tection Register).
Reset/Power-Down (RP). The Reset/Power-
Down input provides hardware reset of the memo-
ry, and/or Power-Down functions, depending on
the Burst Configuration Register status. A Reset or
Power-Down of the memory is achieved by pulling
RP to VIL for at least tPLPH. When the reset pulse
is given, the memory will recover from Power-
Down (when enabled) in a minimum of tPHEL,
tPHLL or tPHWL (see Table 25 and Figure 16) after
the rising edge of RP. After a Reset or Power-Up
the device is configured for asynchronous page
read (M15=1) and the power save function is dis-
abled (M10=0). All blocks are locked after a Reset
or Power-Down. Either Chip Enable or Write En-
able must be tied to VIH during Power-Up to allow
maximum security and the possibility to write a
command on the first rising edge of Write Enable.
Latch Enable (L). Latch Enable latches the ad-
dress bits A0-A20 on its rising edge. The ad-
dress latch is transparent when L is at VIL and
it is inhibited when L is at VIH.
Clock (K). The clock input synchronizes the
memory to the microcontroller during burst mode
read operation; the address is latched on a K edge
(rising or falling, according to the configuration set-
tings) when L is at VIL. K is don't care during asyn-
chronous page mode read and in write operations.
Wait (WAIT). Wait is an output signal used during
burst mode read, indicating whether the data on
the output bus are valid or a wait state must be in-
serted. This output is high impedance when Chip
Enable or Output Enable are at VIH or Reset/Pow-
er-Down is at VIL. It can be configured to be active
during the wait cycle or one clock cycle in ad-
vance.
VDD Supply Voltage (1.65V to 2V). VDD pro-
vides the power supply to the internal core of the
memory device. It is the main power supply for all
operations (Read, Program and Erase). It ranges
from 1.65V to 2.0V.
VDDQ Supply Voltage (1.65V to 3.3V). VDDQ
provides the power supply to the I/O pins and en-
ables all Outputs to be powered independently
from VDD. VDDQ can be tied to VDD or it can use a
separate supply. It can be powered either from
1.65V to 2.0V or from 1.65V to 3.3V.
VPP Program Supply Voltage (12V).VPP is a power supply pin. The Supply Voltage
VDD and the Program Supply Voltage VPP can be
applied in any order. The pin can also be used as
a control input.
The two functions are selected by the voltage
range applied to the pin. If VPP is kept in a low volt-
age range (0V to 2V) VPP is seen as a control in-
put. In this case a voltage lower than VPPLK gives
an absolute protection against program or erase,
11/63
M58CR032C, M58CR032Dwhile VPP > VPP1 enables these functions (see Ta-
ble 19, DC Characteristics for the relevant values).
VPP is only sampled at the beginning of a program
or erase; a change in its value after the operation
has started does not have any effect on Program
or Erase, however for Double or Quadruple Word
Program the results are uncertain.
If VPP is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition VPP must be
stable until the Program/Erase algorithm is com-
pleted (see Table 16 and 17). In read mode the
current sunk is less then 0.5mA, while during pro-
gram and erase operations the current may in-
crease up to 10mA.
VSS and VSSQ Grounds. VSS and VSSQ grounds
are the reference for the core supply and the input/
output voltage measurements respectively.
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1μF ca-
pacitor close to the pin. See Figure 10, AC Mea-
surement Load Circuit. The PCB trace widths
should be sufficient to carry the required VPP
program and erase currents.
M58CR032C, M58CR032D
BUS OPERATIONSThere are two types of bus operations that control
the device: Asynchronous (Read, Page Read,
Write, Output Disable, Standby, Automatic Stand-
by and Reset/Power-Down) and Synchronous
(Synchronous Read and Synchronous Burst
Read).
The Dual Bank architecture of the M58CR032 al-
lows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time (see Table 7).
See Table 3, Bus Operations, for a summary. Typ-
ically glitches of less than 5ns on Chip Enable or
Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Read. Asynchronous Read oper-
ations read from the Memory Array, or specific
registers (Electronic Signature, Status Register,
CFI, Block Protection Status, Read Configuration
Register status and Protection Register) in the
Command Interface.
A valid Asynchronous Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The address is latched on the rising
edge of the Latch, L, input. The Data Inputs/Out-
puts will output the value, see Figure 11, Asyn-
chronous Read AC Waveforms, and Table 21,
Asynchronous Read AC Characteristics, for de-
tails of when the output becomes valid.
According to the device configuration the following
Read operations: Electronic Signature, Status
Register, CFI, Block Protection Status, Burst Con-
figuration Register Status and Protection Register
must be accessed as asynchronous read or as
single synchronous read.
Asynchronous Page Read. Asynchronous
Page Read operations can be used to read the
content of the memory array, where data is inter-
nally read and stored in a page buffer. The page
has a size of 4 words and is addressed by A0 and
A1 address inputs.
Valid bus operations are the same as Asynchro-
nous Bus Read operations but with different tim-
ings. The first read operation within the page has
identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. See Figure 12, Asynchronous Page
Read AC Waveforms and Table 21, Asynchro-
nous Read AC Characteristics for details on when
the outputs become valid.
Asynchronous Page Read is the default state of
the device when exiting power-down or after pow-
er-up.
Asynchronous Write. Bus Write operations are
used to write to the Command Interface of the
memory or latch Input Data to be programmed. A
valid Bus Write operation begins by setting the de-
sired address on the Address Inputs and setting
Chip Enable, E, and Write Enable, W, to VIL and
Output Enable to VIH. Addresses are latched on
the rising edge of L, W or E whichever occur first.
Commands and Input Data are latched on the ris-
ing edge of W or E whichever occurs first. Output
Enable must remain High, VIH, during the whole
Bus Write operation. See Figures 14 and 15, Write
AC Waveforms, and Tables 23 and 24, Write AC
Characteristics, for details of the timing require-
ments.
Write operations are asynchronous and the clock
is ignored during write.
Output Disable. The data outputs are high im-
pedance when the Output Enable, G, and Write
Enable, W, are High, VIH.
Standby. When Chip Enable is High, VIH, and the
Program/Erase Controller is idle, the memory en-
ters Standby mode and the Data Inputs/Outputs
pins are placed in the high impedance state, inde-
pendent of Output Enable, G, or Write Enable, W.
For the Standby current level see Table 19, DC
Characteristics.
Reset/Power-Down. The memory is in Power-
Down when the Burst Configuration Register is set
for Power-Down and RP is at VIL. The power con-
sumption is reduced to the Power-Down level, and
Outputs are in high impedance, independent of
Chip Enable E, Output Enable G or Write Enable
W. The memory is in reset mode when the Burst
Configuration Register is set for Reset and RP is
at VIL. The power consumption is the same of the
standby and the outputs are in high impedance.
After a Reset/Power-Down the device defaults to
Asynchronous Page Read, the Status Register is
cleared and the Burst configuration register de-
faults to Asynchronous Page read.
Automatic Standby. If CMOS levels (VDD ±
0.2V) are used to drive the bus and the bus is in-
active for 150ns or more in Read mode, the mem-
ory enters Automatic Standby where the internal
Supply Current is reduced to the Standby Supply
Current, IDD2. The Data Inputs/Outputs will still
output data if a Bus Read operation is in progress.
The automatic standby feature is not available
when the device is configured for synchronous
burst mode.
Synchronous Single Read. Synchronous sin-
gle Reads can be used to read the Electronic Sig-
nature, Status Register, CFI, Block Protection
Status, Burst Configuration Register Status or
13/63
M58CR032C, M58CR032DProtection Register, see Figure 6, for an example
of a single synchronous read operation.
Synchronous Burst Read. The device also sup-
ports a synchronous burst read. In this mode a
burst sequence is started at the first clock edge
(rising or falling according to configuration set-
tings) after the falling edge of Latch Enable. After
a configurable delay of 2 to 5 clock cycles a new
data is output at each clock cycle. The burst se-
quence may be configured to be sequential or in-
terleaved and for a length of 4 or 8 words or for
continuous burst mode (see Table 5, Burst Type
Definition). Wrap and no-wrap modes are also
supported.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur. This delay
will depend on the starting address of the burst se-
quence; the worst case delay will occur when the
sequence is crossing a 64 word boundary and the
starting address was at the end of a four word
boundary. See the Burst Configuration Register
command for more details on all the possible set-
tings for the synchronous burst read (see Table 4).
It is possible to perform burst read across bank
boundaries (all banks in read array mode).
Table 3. Bus Operations Note:1. X = Don’t care. T = transition, falling edge for L, rising or falling edge for K depending on M6 in the Burst Configuration Register. The burst sequence
is started on the first active clock edge after the falling edge of Latch Enable. L can be tied to VIH if the valid address has been previously latched
M58CR032C, M58CR032D
15/63
M58CR032C, M58CR032D
Burst Configuration RegisterThe Burst Configuration Register is used to config-
ure the type of bus access that the memory will
perform.
The Burst Configuration Register is set through
the Command Interface. After a Reset or Power-
Up the device is configured for asynchronous
page read (M15 = 1) and the power save function
is disabled (M10 = 0). The Burst Configuration
Register bits are described in Table 4. They spec-
ify the selection of the burst length, burst type,
burst X latency and the Read operation. Refer to
Figures 7 and 8 for examples of synchronous burst
configurations.
Read Select Bit (M15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.
Synchronous Burst Read is supported in both pa-
rameter and main blocks and can be performed
across banks.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous access.
X-Latency Bits (M13-M11). The X-Latency bits
are used during Synchronous Bus Read opera-
tions to set the number of clock cycles between
the address being latched and the first data be-
coming available. For correct operation the X-La-
tency bits can only assume the values in Table 4,
Burst Configuration Register.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters.
Two conditions must be satisfied:
–(n + 1) tK ≥ tACC - tAVK_CPU + tQVK_CPU
–tK > tKQV + tQVK_CPU
where "n" is the chosen X-Latency configuration
code, tK is the clock period, tAVK_CPU is Clock to
Address Valid, L Low or E Low, whichever occurs
last, and tQVK_CPU is the data setup time required
by the system CPU.
Power-Down Bit (M10). The Power-Down bit is
used to enable or disable the power-down func-
tion. When the Power-Down bit is set to ‘0’ (de-
fault) the power-down function is disabled. When
the Power-Down bit is set to ‘1’ power-down is en-
abled and the device goes into the power-down
state where the IDD supply current is reduced to a
typical figure of IDD2.
if this function is disabled the Reset/Power-Down,
RP, pin causes only a reset of the device and the
supply current is the standby value. The recovery
time after a Reset/Power-Down, RP, pulse is sig-
nificantly longer when power-down is enabled
(see Table 25).
Wait Bit (M8). In burst mode the Wait bit controls
the timing of the Wait output pin, WAIT. When the
Wait bit is ’0’ the Wait output pin is asserted during
the wait state. When the Wait bit is ’1’ (default) the
Wait output pin is asserted one clock cycle before
the wait state.
WAIT is asserted during a continuous burst and
also during a 4 or 8 burst length if no-wrap config-
uration is selected. WAIT is not asserted during
asynchronous reads, single synchronous reads or
during latency in synchronous reads.
Burst Type Bit (M7). The Burst Type bit is used
to configure the sequence of addresses read as
sequential or interleaved. When the Burst Type bit
is ’0’ the memory outputs from interleaved ad-
dresses; when the Burst Type bit is ’1’ (default) the
memory outputs from sequential addresses. See
Tables 5, Burst Type Definition, for the sequence
of addresses output from a given starting address
in each mode.
Valid Clock Edge Bit (M6). The Valid Clock
Edge bit, M6, is used to configure the active edge
of the Clock, K, during Synchronous Burst Read
operations. When the Valid Clock Edge bit is ’0’
the falling edge of the Clock is the active edge;
when the Valid Clock Edge bit is ’1’ the rising edge
of the Clock is active.
Wrap Burst Bit (M3). The burst reads can be
confined inside the 4 or 8 Double-Word boundary
(wrap) or overcome the boundary (no wrap). The
Wrap Burst bit is used to select between wrap and
no wrap. When the Wrap Burst bit is set to ‘0’ the
burst read wraps; when it is set to ‘1’ the burst read
does not wrap.
Burst length Bits (M2-M0). The Burst Length
bits set the number of Words to be output during a
Synchronous Burst Read operation; 4 words, 8
words or continuous burst, where all the words are
read sequentially.
In continuous burst mode the burst sequence can
cross bank boundaries.
In continuous burst mode or in 4, 8 words no-wrap,
depending on the starting address, the device ac-
tivates the WAIT output to indicate that a delay is
necessary before the data is output.
If the starting address is aligned to a 4 word
boundary no wait states are needed and the WAIT
output is not activated.
If the starting address is shifted by 1,2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 64 word boundary, to
indicate that the device needs an internal delay to
read the successive words in the array. WAIT will
M58CR032C, M58CR032Dbe asserted only once during a continuous burst
access. See also Table 5, Burst Type Definition.
M14, M9, M5 and M4 are reserved for future use.
Table 4. Burst Configuration Register
17/63
M58CR032C, M58CR032D
Table 5. Burst Type Definition
M58CR032C, M58CR032D
19/63
M58CR032C, M58CR032D
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Pro-
gram/Erase states. See Appendix C, Tables 36
and 37, Command Interface States - Lock and
Modify Tables, for a summary of the Command In-
terface.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
set or whenever VDD is lower than VLKO. Com-
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 6, Commands,
in conjunction with the text descriptions below.
Read Command.The Read command returns the addressed bank
to Read mode. One Bus Write cycle is required to
issue the Read command and return the ad-
dressed Bank to Read mode. Subsequent read
operations will read the addressed location and
output the data. A Read command can be issued
in one bank while programming or erasing in the
other bank. However if a Read command is issued
to a bank currently executing a program or erase
operation the command will be ignored.
When a device Reset occurs, the memory defaults
to Read mode.
Read Status Register Command bank’s Status Register indicates when a pro-
gram or erase operation is complete and the suc-
cess or failure of operation itself. Issue a Read
Status Register command to read the Status Reg-
ister content of the addressed bank. The status of
the other bank is not affected by the command.
The Read Status Register command can be is-
sued at any time, even during program or erase
operations.
The following Read operations output the content
of the Status Register of the addressed bank. The
Status Register is latched on the falling edge of E
or G signals, and can be read until E or G returns
to VIH. Either E or G must be toggled to update the
latched data. See Table 15 for the description of
the Status Register Bits. This mode supports
asynchronous or single synchronous reads only.
Read Electronic Signature Command The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle to an address within the bottom
bank. A subsequent read operation in the address
of the bottom bank will output the Manufacturer
Code, the Device Code, the protection Status of
Blocks of the bottom bank, the Die Revision Code,
the Protection Register, or the Read Configuration
Register (see Table 11).
If the first write cycle of Read Electronic Signature
command is issued to an address within the top
bank, a subsequent read operation in an address
of the top bank will output the protection Status of
blocks of the top bank. The status of the other
bank is not affected by the command (see Table
7). This mode supports asynchronous or single
synchronous reads only.
See Tables 8, 9, 10 and 11 for the valid addresses.
Read CFI Query Command The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area, located in the bottom bank. One
Bus Write cycle, addressed to the bottom bank, is
required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations in the bottom bank read from the
Common Flash Interface Memory Area. The sta-
tus of the top bank is not affected by the command
(see Table 7). After issuing a Read CFI Query
command, a Read command should be issued to
return the bank to read mode.
See Appendix B, Common Flash Interface, Tables
29, 30, 31, 32, 33, 34 and 35 for details on the in-
formation contained in the Common Flash Inter-
face memory area.
Clear Status Register CommandThe Clear Status Register command can be used
to reset (set to ‘0’) bits 1, 3, 4 and 5 in the Status
Register of the addressed bank’. One bus write cy-
cle is required to issue the Clear Status Register
command. After the Clear Status Register com-
mand the bank returns to read mode.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Block Erase CommandThe Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error. It is not
necessary to pre-program the block as the Pro-
M58CR032C, M58CR032Dgram/Erase Controller does it automatically before
erasing.
Two Bus Write cycles are required to issue the
command. The first bus cycle sets up the Erase command. The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts. Erase aborts if Reset turns
to VIL. As data integrity cannot be guaranteed
when the Erase operation is aborted, the block
must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register until a
Read command is issued.
During Erase operations the bank containing the
block being erased will only accept the Read Sta-
tus Register command and the Program/Erase
Suspend command, all other commands will be ig-
nored. Typical Erase times are given in Table 12,
Program, Erase Times and Program/Erase Endur-
ance Cycles.
See Appendix B, Figure 22, Block Erase Flowchart
and Pseudo Code, for a suggested flowchart for
using the Block Erase command.
Bank Erase CommandThe Bank Erase command can be used to erase a
bank. It sets all the bits within the selected bank to
’1’. All previous data in the bank is lost. The Bank
Erase command will ignore any protected blocks
within the bank. If the bank is protected then the
Erase operation will abort, the data in the bank will
not be changed and the Status Register will output
the error.
Two Bus Write cycles are required to issue the
command. The first bus cycle sets up the Bank Erase
command. The second latches the bank address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Bank Erase
Confirm (D0h), Status Register bits b4 and b5 are
set and the command aborts. Erase aborts if Re-
set turns to VIL. As data integrity cannot be guar-
anteed when the Erase operation is aborted, the
bank must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register until a
Read command is issued.
During Erase operations the bank being erased
will only accept the Read Status Register com-
mand and the Program/Erase Suspend command,
all other commands will be ignored. Typical Erase
times are given in Table 12, Program, Erase
Times and Program/Erase Endurance Cycles.
Program CommandThe memory array can be programmed word-by-
word. Only one bank can be programmed at any
one time. The other bank must be in Read mode
or Erase Suspend. Two bus write cycles are re-
quired to issue the Program Command. The first bus cycle sets up the Program
command. The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
After programming has started, Read operations
in the bank being programmed output the Status
Register content.
During Program operations the bank being pro-
grammed will only accept the Read Status Regis-
ter command and the Program/Erase Suspend
command. Typical Program times are given in Ta-
ble 12, Program, Erase Times and Program/Erase
Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix B, Figure 18, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program CommandThis feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. The two words must differ only for the
address A0. Only one bank can be programmed at
any one time. The other bank must be in Read
mode or Erase Suspend.
Programming should not be attempted when VPP
is not at VPPH. The command can be executed if
VPP is below VPPH but the result is not guaranteed.
Three bus write cycles are necessary to issue the
Double Word Program command. The first bus cycle sets up the Double Word
Program Command. The second bus cycle latches the Address and
the Data of the first word to be written. The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
21/63
M58CR032C, M58CR032DRead operations in the bank being programmed
output the Status Register content after the pro-
gramming has started.
During Double Word Program operations the bank
being programmed will only accept the Read Sta-
tus Register command and the Program/Erase
Suspend command. Typical Program times are
given in Table 12, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix B, Figure 19, Double Word Program
Flowchart and Pseudo Code, for the flowchart for
using the Double Word Program command.
Quadruple Word Program Command This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel. The four words must differ only for the
addresses A0 and A1. The first write cycle must be
addressed to the bank to be programmed.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Programming should not be attempted when VPP
is not at VPPH. The command can be executed if
VPP is below VPPH but the result is not guaranteed.
Five bus write cycles are necessary to issue the
Quadruple Word Program command. The first bus cycle sets up the Double Word
Program Command. The second bus cycle latches the Address and
the Data of the first word to be written. The third bus cycle latches the Address and the
Data of the second word to be written. The fourth bus cycle latches the Address and
the Data of the third word to be written. The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations to the bank being programmed
output the Status Register content after the pro-
gramming has started.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
During Quadruple Word Program operations the
bank being programmed will only accept the Read
Status Register command and the Program/Erase
Suspend command. Typical Program times are
given in Table 12, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See Appendix B, Figure 20, Quadruple Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Quadruple Word Program
command.
Program/Erase Suspend Command The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pause the Program/Erase control-
ler. The command must be addressed to the bank
containing the program or erase operation.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read, Read Status Register, Read Electronic Sig-
nature and Read CFI Query commands. Addition-
ally, if the suspend operation was Erase then the
Program, Block Lock, Block Lock-Down or Protec-
tion Program commands will also be accepted.
The block being erased may be protected by issu-
ing the Block Lock, Block Lock-Down or Protection
Program commands. Only the blocks not being
erased may be read or programmed correctly.
When the Program/Erase Resume command is is-
sued the operation will complete.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Enable to VIH. Program/Erase is aborted if
Reset turns to VIL.
See Appendix B, Figure 21, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
23, Erase Suspend & Resume Flowchart and
Pseudo Code for flowcharts for using the Program/
Erase Suspend command.
Program/Erase Resume Command The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend command has paused
it. One Bus Write cycle is required to issue the
command. The command must be addressed to
the bank containing the program or erase opera-
tion. Once the command is issued subsequent
Bus Read operations read the Status Register.
If a Program command is issued during a Block
Erase Suspend, then the erase cannot be re-
sumed until the programming operation has com-
pleted. It is possible to accumulate suspend
operations. For example: suspend an erase oper-
ation, start a programming operation, suspend the
programming operation then read the array. See
Appendix B, Figure 21, Program Suspend & Re-
sume Flowchart and Pseudo Code, and Figure 23,
Erase Suspend & Resume Flowchart and Pseudo
Code for flowcharts for using the Program/Erase
Resume command.
M58CR032C, M58CR032D
Protection Register Program CommandThe Protection Register Program command is
used to Program the 64 bit user One-Time-Pro-
grammable (OTP) segment of the Protection Reg-
ister. The segment is programmed 16 bits at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are required to issue the Protec-
tion Register Program command. The first bus cycle sets up the Protection
Register Program command. The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register. Bit 1 of the Pro-
tection Lock Register protects bit 2 of the Protec-
tion Lock Register. Programming bit 2 of the
Protection Lock Register will result in a permanent
protection of the Security Block (see Figure 5, Se-
curity Block and Protection Register Memory
Map). Attempting to program a previously protect-
ed Protection Register will result in a Status Reg-
ister error. The protection of the Protection
Register and/or the Security Block is not revers-
ible.
The Protection Register Program cannot be sus-
pended. See Appendix B, Figure 25, Protection
Register Program Flowchart and Pseudo Code,
for a flowchart for using the Protection Register
Program command.
Block Lock CommandThe Block Lock command is used to lock a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command. The first bus cycle sets up the Block Lock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 14 shows the Lock Status after issuing a
Block Lock command.
The Block Lock bits are volatile, once set they re-
main set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation. See Appendix B, Figure
24, Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Lock command.
Block Unlock CommandThe Blocks Unlock command is used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Write cycles are required to is-
sue the Blocks Unlock command. The first bus cycle sets up the Block Unlock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 13 shows the protection status after issuing Block Unlock command. Refer to the section,
Block Locking, for a detailed explanation and Ap-
pendix B, Figure 24, Locking Operations Flow-
chart and Pseudo Code, for a flowchart for using
the Unlock command.
Block Lock-Down CommandA locked block cannot be Programmed or Erased,
or have its protection status changed when WP is
low, VIL. When WP is high, VIH, the Lock-Down
function is disabled and the locked blocks can be
individually unlocked by the Block Unlock com-
mand.
Two Bus Write cycles are required to issue the
Block Lock-Down command. The first bus cycle sets up the Block Lock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table. 14 shows the Lock Status af-
ter issuing a Block Lock-Down command. Refer to
the section, Block Locking, for a detailed explana-
tion and Appendix B, Figure 24, Locking Opera-
tions Flowchart and Pseudo Code, for a flowchart
for using the Lock-Down command.
Set Burst Configuration Register Command.The Set Burst Configuration Register command is
used to write a new value to the Burst Configura-
tion Control Register which defines the burst
length, type, X latency, Synchronous/Asynchro-
nous Read mode and the valid Clock edge config-
uration.
Two Bus Write cycles are required to issue the Set
Burst Configuration Register command. The first
cycle writes the setup command and the address
corresponding to the Set Burst Configuration Reg-
ister content. The second cycle writes the Burst
Configuration Register data and the confirm com-
mand. Once the command is issued the memory
returns to Read mode as if a Read Memory Array
command had been issued.
23/63
M58CR032C, M58CR032DThe value for the Burst Configuration Register is
always presented on A0-A15. M0 is on A0, M1 on
A1, etc.; the other address bits are ignored.
Table 6. CommandsNote:1. X = Don’t Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ESA= Electronic Signature Address, ID=Identifier
(Manufacture and Device Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program
Data, PRA=Protection Register Address, PRD=Protection Register Data, BCRA=Burst Configuration Register Address,
BCRD=Burst Configuration Register Data. The signature addresses are listed in Tables 8, 9 and 10. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
M58CR032C, M58CR032D
Table 7. Dual Bank Operations Note:1. For detailed description of command see Table 6, 36 and 37. There is a Status Register for each bank; Status Register indicates bank state, not P/E.C. status. Command must be written to an address within the block targeted by that command.
Table 8. Read Electronic Signature Note:1. Addresses are latched on the rising edge of L input. ESA means Electronic Signature Address (see Read Electronic Signature)
Table 9. Read Block Protection Note:1. Addresses are latched on the rising edge of L input. A locked block can only be unlocked with WP at VIH. BA means Block Address. First cycle command address should indicate the bank of the block address.
25/63
M58CR032C, M58CR032D
Table 10. Read Protection RegisterNote:1. Addresses are latched on the rising edge of L input. X = Don’t care.
Table 11. Identifier CodesNote: DRC=Die Revision Code, BCR=Burst Configuration Register, LPR= Lock Protection Register, PR=Protection Register (Unique Device
Number and User Programmable OTP).
M58CR032C, M58CR032D
Table 12. Program, Erase Times and Program, Erase Endurance CyclesNote:1. TA = –40 to 85°C; VDD = 1.65V to 2V; VDDQ = 1.65V to 3.3V. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms). Excludes the time needed to execute the command sequence.
27/63
M58CR032C, M58CR032D
BLOCK LOCKINGThe M58CR032 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection. Lock/Unlock - this first level allows software-
only control of block locking. Lock-Down - this second level requires
hardware interaction before locking can be
changed. VPP ≤ VPPLK - the third level offers a complete
hardware protection against program and erase
on all blocks.
For all devices the protection status of each block
can be set to Locked, Unlocked, and Lock-Down.
Table 14, defines all of the possible protection
states (WP, DQ1, DQ0), and Appendix B, Figure
24, shows a flowchart for the locking operations.
Reading a Block’s Lock StatusThe lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode write 90h to the device. Subse-
quent reads at the address specified in Table 9,
will output the protection status of that block. The
lock status is represented by DQ0 and DQ1. DQ0
indicates the Block Lock/Unlock status and is set
by the Lock command and cleared by the Unlock
command. It is also automatically set when enter-
ing Lock-Down. DQ1 indicates the Lock-Down sta-
tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked StateThe default status of all blocks on power-up or af-
ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper-
ations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com-
mands. An Unlocked block can be Locked by issu-
ing the Lock command.
Unlocked StateUnlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be un-
locked by issuing the Unlock command.
Lock-Down StateBlocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can-
not be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked-
Down blocks revert to the Locked state when the
device is reset or powered-down.
The Lock-Down function is dependent on the WP
input pin. When WP=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
WP=1 (VIH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be individu-
ally unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WP
remains high. When WP is low , blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP was high. Device reset or power-down
resets all blocks , including those in Lock-Down, to
the Locked state.
Locking Operations During Erase SuspendChanges to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operations cannot be performed during a
program suspend. Refer to Appendix C, Com-
mand Interface State Table, for detailed informa-
tion on which commands are valid during erase
suspend.
M58CR032C, M58CR032D
Table 13. Block Lock Status
Table 14. Lock Status Note:1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = VIH and A0 = VIL. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
29/63
M58CR032C, M58CR032D
STATUS REGISTERThe M58CR032 has two Status Registers, one for
each bank. The Status Registers provide informa-
tion on the current or previous Program or Erase
operations executed in each bank. The various
bits convey information and errors on the opera-
tion. Issue a Read Status Register command to
read the Status Register content of the addressed
bank, refer to Read Status Register Command
section for more details. To output the contents,
the Status Register is latched on the falling edge
of the Chip Enable or Output Enable signals, and
can be read until Chip Enable or Output Enable re-
turns to VIH. Either Chip Enable or Output Enable
must be toggled to update the latched data.
Bus Read operations from any address within the
bank, always read the Status Register during Pro-
gram and Erase operations.
The bits in the Status Register are summarized in
Table 15, Status Register Bits. Refer to Table 15
in conjunction with the following text descriptions.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive
in the addressed bank. When the Program/Erase
Controller Status bit is Low (set to ‘0’), the Pro-
gram/Erase Controller is active; when the bit is
High (set to ‘1’), the Program/Erase Controller is
inactive, and the device is ready to process a new
command.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High .
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg-
ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Lock Status bits should be tested
for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended or is going to be suspended
in the addressed block. When the Erase Suspend
Status bit is High (set to ‘1’), a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
The Erase Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30μs of the Program/Erase Sus-
pend command being issued therefore the memo-
ry may still complete the operation rather than
entering the Suspend mode.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set to ‘1’), the Program/
Erase Controller has applied the maximum num-
ber of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Sta-
tus bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the Byte and still failed to ver-
ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new command is issued, otherwise the new
command will appear to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the volt-
age on the VPP pin was sampled at a valid voltage;
when the VPP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the VPP Lockout
Voltage, VPPLK, the memory is protected and Pro-
gram and Erase operations cannot be performed.
Once set High, the VPP Status bit can only be reset
Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended in the addressed block.
When the Program Suspend Status bit is High (set
to ‘1’), a Program/Erase Suspend command has
M58CR032C, M58CR032Dbeen issued and the memory is waiting for a Pro-
gram/Erase Resume command. The Program
Suspend Status should only be considered valid
when the Program/Erase Controller Status bit is
High (Program/Erase Controller inactive). Bit 2 is
set within 5μs of the Program/Erase Suspend
command being issued therefore the memory may
still complete the operation rather than entering
the Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to Appendix B, Flowcharts and
Pseudo Codes, for using the Status Register.
Table 15. Status Register BitsNote: Logic level ’1’ is High, ’0’ is Low.
31/63
M58CR032C, M58CR032D
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 16. Absolute Maximum RatingsNote:1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
M58CR032C, M58CR032D
DC AND AC PARAMETERSThis section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 17, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 17. Operating and AC Measurement Conditions
Figure 9. AC Measurement I/O Waveform
Table 18. CapacitanceNote: Sampled only, not 100% tested.
