M48Z512AY-85PM9 ,4 MBIT (512KB X 8) ZEROPOWER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. 32-pin PMDIP ModulePOWER-FAIL CONTROL ..
M48Z58-70PC1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. CAPHAT™ DIP SolutionPOWER-FAIL CONTRO ..
M48Z58-70PC1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 6. Operating and ..
M48Z58-70PC1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMBlock Diagram . . 5OPERATING MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M48Z58Y-70MH1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMM48Z58M48Z58Y®5V, 64 Kbit (8 Kbit x8) ZEROPOWER SRAM
M48Z58Y-70MH1E ,64 Kbit (8Kb X 8) ZEROPOWER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 4. DIP Connections 5Figur ..
M62003FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62005L , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M48Z512A-70PM1-M48Z512AY-70PM1-M48Z512AY-85PM9
4 Mbit (512Kb x8) ZEROPOWER SRAM
1/22February 2005
M48Z512A
M48Z512AY, M48Z512AV4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
FEATURES SUMMARY INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PROTECTION TWO WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage) M48Z512A: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V M48Z512AY: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V M48Z512AV: VCC = 3.0 to 3.6V
2.8V ≤ VPFD ≤ 3.0V BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 512K x 8 SRAMs SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 28-PIN M40Z300/
W AND A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT® Top to be ordered separately)
M48Z512A, M48Z512AY, M48Z512AV
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution. . . . . . . . . . . . . . . . . . .6
Table 2. Equivalent Surface-Mount (SMT) Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . .8
Figure 7. Address Controlled, READ Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 8. WRITE Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 13.PMDIP32 – 32-pin Plastic DIP Module, Package Outline . . . . . . . . . . . . . . . . . . . . . . . .16
Table 12. PMDIP32 – 32-pin Plastic DIP Module, Package Mechanical Data . . . . . . . . . . . . . . . .16
Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . .17
Table 13. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 17
Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . .18
3/22
M48Z512A, M48Z512AY, M48Z512AVTable 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data . . . . . . .18
Figure 16.SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline . . . . . . . . . . . . . .19
Table 15. SH - 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data. . . . . . .19
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 18. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
M48Z512A, M48Z512AY, M48Z512AV
DESCRIPTIONThe M48Z512A/Y/V ZEROPOWER® RAM is a
non-volatile, 4,194,304-bit Static RAM organized
as 524,288 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP Module.
For surface-mount environments ST provides an
equivalent SMT solution consisting of a 28-pin,
330mil SOIC NVRAM SUPERVISOR (M40Z300/
W) and a 32-pin, (Type II TSOP, 10 x 20mm) 4Mb
LPSRAM. Both 5V and 3V versions are available
(see Table 2., page 6).
The unique design allows the SNAPHAT® battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface-mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is “M4Z32-BR00SH1.”
Table 1. Signal Names
5/22
M48Z512A, M48Z512AY, M48Z512AV
Figure 3. DIP Connections
Figure 4. Block Diagram
M48Z512A, M48Z512AY, M48Z512AV
Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution
Note: For pin connections, see individual datasheet for M48Z300/300W at . Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z512AY) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z512A). Connect THS pin to VSS if 2.8V ≤ VPFD ≤ 3.0V (M48Z512AV). SNAPHAT® Top ordered separately.
Table 2. Equivalent Surface-Mount (SMT) Solution
Note:1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/300W).
7/22
M48Z512A, M48Z512AY, M48Z512AV
OPERATING MODES
The M48Z512A/Y/V also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single VCC supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low VCC. As VCC falls
below the switchover voltage (VSO), the control cir-
cuitry connects the battery which maintains data
until valid power returns.
The ZEROPOWER® RAM replaces industry stan-
dard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
Table 3. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 11., page 15 for details.
M48Z512A, M48Z512AY, M48Z512AV
READ Mode
The M48Z512A/Y/V is in the READ Mode whenev-
er W (WRITE Enable) is high and E (Chip Enable)
is low. The device architecture allows ripple-
through access of data from eight of 4,194,304 lo-
cations in the static storage array. Thus, the
unique address specified by the 19 Address Inputs
defines which one of the 524,288 bytes of data is
to be accessed. Valid data will be available at the
Data I/O pins within Address Access time (tAVQV)
after the last address input signal is stable, provid-
ing that the E (Chip Enable) and G (Output En-
able) access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the later of Chip Enable Access
time (tELQV) or Output Enable Access Time
(tGLQV). The state of the eight three-state Data I/O
signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Ad-
dress Inputs are changed while E and G remain
low, output data will remain valid for Output Data
Hold time (tAXQX) but will go indeterminate until the
next Address Access.
9/22
M48Z512A, M48Z512AY, M48Z512AV
Table 4. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). CL = 5pF.
WRITE Mode
The M48Z512A/Y/V is in the WRITE Mode when-
ever W and E are active. The start of a WRITE is
referenced from the latter occurring falling edge of
W or E. A WRITE is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for a minimum of tE-
HAX from E or tWHAX from W prior to the initiation
of another READ or WRITE cycle. Data-in must be
valid tDVEH or tDVWH prior to the end of WRITE and
remain valid for tEHDX or tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
M48Z512A, M48Z512AY, M48Z512AV
11/22
M48Z512A, M48Z512AY, M48Z512AV
Data Retention Mode
With valid VCC applied, the M48Z512A/Y/V oper-
ates as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as “don't care.”
If power fail detection occurs during a valid ac-
cess, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
tWP, write protection takes place. When VCC drops
below VSO, the control circuit switches power to
the internal energy source which preserves data.
The internal coin cell will maintain data in the
M48Z512A/Y/V after the initial application of VCC
for an accumulated period of at least 10 years
when VCC is less than VSO. As system power re-
turns and VCC rises above VSO, the battery is dis-
connected, and the power supply is switched to
external VCC. Write protection continues for tER af-
ter VCC reaches VPFD to allow for processor stabi-
lization. After tER, normal RAM operation can
resume.
For more information on Battery Storage Life refer
to the Application Note AN1012.
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (see Figure 10.) is
recommended in order to provide the needed fil-
tering.
