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Partno Mfg Dc Qty AvailableDescript
M48Z35-70PC1 |M48Z3570PC1STN/a1000avai256 KBIT (32KB X 8) ZEROPOWER SRAM
M48Z35Y-70MH1 |M48Z35Y70MH1N/a49avai256 Kbit (32Kbit X 8) ZEROPOWER SRAM
M48Z35Y-70MH1F |M48Z35Y70MH1FSTN/a2500avai256 Kbit (32Kbit X 8) ZEROPOWER SRAM
M48Z35Y-70MH1TR |M48Z35Y70MH1TRSTMN/a113avai256 Kbit (32Kbit X 8) ZEROPOWER SRAM
M48Z35Y-70PC1 |M48Z35Y70PC1STN/a400avai256 KBIT (32KB X 8) ZEROPOWER SRAM


M48Z35Y-70MH1F ,256 Kbit (32Kbit X 8) ZEROPOWER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 28-pin CAPHAT™ DIP Package . . . . 1Figure 2. 28- ..
M48Z35Y-70MH1TR ,256 Kbit (32Kbit X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . . . . . . . 11DC AND AC PARAMETERS . 12Table 8. Operating and ..
M48Z35Y-70PC1 ,256 KBIT (32KB X 8) ZEROPOWER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 4. DIP Connections 5Figur ..
M48Z512A-70PM1 ,4 Mbit (512Kb x8) ZEROPOWER SRAMAbsolute Maximum Ratings . . . . . . . 12DC AND AC PARAMETERS . 13Table 7. Operating and ..
M48Z512AV-85PM1 ,4 Mbit (512 Kbit x 8) ZEROPOWER® SRAMFeatures■ Integrated, ultra low power SRAM, power-fail control circuit, and battery■ Conventional S ..
M48Z512AY-70PM1 ,4 Mbit (512Kb x8) ZEROPOWER SRAMBlock Diagram . . 5Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution . ..
M62003FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62005L , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES


M48Z35-70PC1-M48Z35Y-70MH1-M48Z35Y-70MH1F-M48Z35Y-70MH1TR-M48Z35Y-70PC1
256 KBIT (32KB X 8) ZEROPOWER SRAM
1/20August 2004
M48Z35
M48Z35Y

256 Kbit (32 Kbit x8) ZEROPOWER® SRAM
FEATURES SUMMARY
INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY READ CYCLE TIME EQUALS WRITE CYCLE
TIME AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage) M48Z35: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V M48Z35Y: 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 32K x 8 SRAMs SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY
M48Z35, M48Z35Y
2/20
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1. 28-pin CAPHAT™ DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 8. WRITE Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 10.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 5. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 6. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 11.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 12.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 13.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . .14
Table 11. PMDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data. . . . . . .14
Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . .15
Table 12. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 15
Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . .16
Table 13. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data . . . . . . .16
3/20
M48Z35, M48Z35Y

Figure 16.SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline. . . . . . . . . . . . . .17
Table 14. SH – 4-pin SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data. . . . . .17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 16. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 17. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
M48Z35, M48Z35Y
4/20
DESCRIPTION

The M48Z35/Y ZEROPOWER® RAM is a 32 Kbit
x 8, non-volatile static RAM that integrates power-
fail deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
The M48Z35/Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. The 28 pin 600mil
DIP CAPHAT™ houses the M48Z35/Y silicon with
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHAT housing
is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is “M4Z28-BR00SH1.” Table 1. Signal Names
5/20
M48Z35, M48Z35Y
M48Z35, M48Z35Y
6/20
OPERATING MODES

The M48Z35/Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low VCC. As VCC falls be-
low approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
Table 2. Operating Modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Note:1. See Table 6., page 10 for details.
READ Mode

The M48Z35/Y is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
7/20
M48Z35, M48Z35Y
Table 3. READ Mode AC Characteristics

Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). CL = 100pF. CL = 5pF.
WRITE Mode

The M48Z35/Y is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of
W or E. The addresses must be held valid through-
out the cycle. E or W must return high for a mini-
mum of tEHAX from Chip Enable or tWHAX from
WRITE Enable prior to the initiation of another
READ or WRITE cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid fortWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
M48Z35, M48Z35Y
8/20
9/20
M48Z35, M48Z35Y
Data Retention Mode

With valid VCC applied, the M48Z35/Y operates as
a conventional BYTEWIDE™ static RAM. Should
the supply voltage decay, the RAM will automati-
cally power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may

corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD(min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z35/Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data. The internal button cell will maintain
data in the M48Z35/Y for an accumulated period of
at least 10 years (at 25°C) when VCC is less than
VSO.
As system power returns and VCC rises above
VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protec-
tion continues until VCC reaches VPFD(min) plus
tREC(min). Normal RAM operation can resume
tREC after VCC exceeds VPFD(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
M48Z35, M48Z35Y
10/20
Table 6. Power Down/Up Trip Points DC Characteristics

Note: All voltages referenced to VSS.
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). At 25°C, VCC = 0V.
VCC Noise And Negative Going Transients

ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (see Figure 11) is
recommended in order to provide the needed fil-
tering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from VCC to VSS (cathode con-
nected to VCC, anode to VSS). (Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).
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