M48Z19-100PC1 ,CMOS 8K x 8 ZEROPOWER SRAMabsolute maximum ratings conditions for extended periods of time may affect reliability.CAUTION: Ne ..
M48Z19-100PC1 ,CMOS 8K x 8 ZEROPOWER SRAMLogic DiagramPIN and FUNCTION COMPATIBLE with theMK48Z09, 19 and JEDEC STANDARD 8K x 8SRAMsDESCRIPT ..
M48Z30Y-100PM1 ,CMOS 32K x 8 ZEROPOWER SRAMabsolute maximum ratings conditions for extended periods of time may affect reliability.CAUTION: Ne ..
M48Z32V-35MT1 ,3.3V, 256 Kbit (32Kbit X8) ZEROPOWER SRAMAbsolute Maximum Ratings 9DC AND AC PARAMETERS . 10Table 6. Operating and AC Measurement ..
M48Z32V-35MT1TR ,3.3V, 256 Kbit (32Kbit X8) ZEROPOWER SRAMBlock Diagram . . 4OPERATING MODES . . . . . . . 4Table 2. Operating Modes 4RE ..
M48Z35-70MH6 ,256 Kbit (32 Kbit x 8) ZEROPOWER SRAMLogic Diagram■ SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY ..
M616Z08-20MH3 ,128 Kbit (8 Kbit X 16) SRAM with Output EnableLogic Diagram . . 1Table 1. Signal Names . . 1DESCRIPTION . . . . 4Figure 3. ..
M616Z08-20MH3TR ,128 Kbit (8 Kbit X 16) SRAM with Output EnableAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 7. DC and AC Meas ..
M62003FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62005L , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M48Z19-100PC1
CMOS 8K x 8 ZEROPOWER SRAM
Figure 1. Logic DiagramCMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMA TIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
POWER-FAIL INTERRUPT
CHOICE of TWO WRITE PROTECT
VOLTAGES: M48Z09: 4.5V ≤ VPFD ≤ 4.75V M48Z19: 4.2V ≤ VPFD ≤ 4.5V
SELF CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
11 YEARS of DATA RETENTION in the
ABSENCE of POWER
PIN and FUNCTION COMPATIBLE with the
MK48Z09, 19 and JEDEC STANDARD 8K x 8
SRAMs
DESCRIPTIONThe M48Z09,19 ZEROPOWER® RAM is an 8K x 8
non-volatile static RAM which is pin and function
compatible with the MK48Z09,19.
A special 28 pin 600mil DIP CAPHAT package
houses the M48Z09,19 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
Table 1. Signal NamesNovember 1994 1/13
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stressrating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
Note: X = VIH or VIL
Table 3. Operating Modes
Figure 2A. DIP Pin ConnectionsThe M48Z09,19 button cell has sufficient capacity
and storage life to maintain data for an accumu-
lated time period of at least 11 years in the absence
of power over the operating temperature range.
The M48Z09,19 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z09,19 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system opera-
tion brought on by low VCC. As VCC falls below
approximately 3V , the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
DESCRIPTION (cont’d)
M48Z09, M48Z19
Figure 4. AC Testing Load Circuit Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
AC MEASUREMENT CONDITIONSNote that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 3. Block Diagram
READ MODEThe M48Z09,19 is in the Read Mode whenever W
(Write Enable) is high, E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The device archi-
tecture allows ripple- through access of data from
eight of 65,536 locations in the static storage array.
Thus, the unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within tAVQV (Address
Access Time) after the last address input signal is
stable, providing that the E1, E2, and G access
times are also satisfied. If the E1, E2 and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tE1LQV
or tE2HQV) or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address
Inputs are changed while E1, E2 and G remain
active, output data will remain valid for tAXQX (Out-
put Data Hold Time) but will go indeterminate until
the next Address Access.
M48Z09, M48Z19
Note:1. The INT pin is Open Drain.
Table 5. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Notes: 1. Effective capacitance calculated from the equation C = IΔt/ΔV with ΔV = 3V and power supply at 5V. Outputs deselected
Table 4. Capacitance (1) (TA = 25 °C)
Note:1. All voltages referenced to VSS.
Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
M48Z09, M48Z19
Notes:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 μs after
VCC passes VPFD (min). VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data. INT may go high anytime after VCC exceeds VPFD (min) and is guaranteed to go high tPFH after VCC exceeds VPFD (max).
Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)
Figure 5. Power Down/Up Mode AC Waveforms
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD(min).Some systems may performs inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begins. Even
though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.
M48Z09, M48Z19
Notes:1. CL= 100pF (see Figure 4). CL= 30pF (see Figure 4)
Table 8. Read Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Figure 6. Read Mode AC Waveforms
M48Z09, M48Z19
Notes:1. CL= 30pF (see Figure 4). If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
Table 9. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z09, M48Z19
