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M48Z128Y-85PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMBlock Diagram . . 5Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution . ..
M48Z129V-85PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . 4DC AND AC PARAMETERS . . 5Table 3. Operating and AC Measurem ..
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M616Z08-20MH3 ,128 Kbit (8 Kbit X 16) SRAM with Output EnableLogic Diagram . . 1Table 1. Signal Names . . 1DESCRIPTION . . . . 4Figure 3. ..
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M62003FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62005L , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M48Z128-70PM1-M48Z128Y-70PM1-M48Z128Y-85PM1
1 MBIT (128KB X 8) ZEROPOWER SRAM
1/21February 2005
M48Z128
M48Z128Y, M48Z128V*5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM
* Contact local ST sales office for availability.
FEATURES SUMMARY INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER BATTERY INTERNALLY ISOLATED UNTIL
POWER IS FIRST APPLIED AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage) M48Z128: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V M48Z128Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V M48Z128V: VCC = 3.0 to 3.6V
2.8V ≤ VPFD ≤ 3.0V SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 28-PIN M40Z300/
W and A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT® Top to be ordered separately)
M48Z128, M48Z128Y, M48Z128V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution. . . . . . . . . . . . . . . . . . .6
Table 2. Equivalent Surface-Mount (SMT) Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . .7
Figure 7. Address Controlled, READ Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 8. WRITE Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 5. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 13.PMDIP32 – 32-pin Plastic DIP Module, Package Outline . . . . . . . . . . . . . . . . . . . . . . . .15
Table 12. PMDIP32 – 32-pin Plastic DIP Module, Package Mechanical Data . . . . . . . . . . . . . . . .15
Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . .16
Table 13. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 16
Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . .17
3/21
M48Z128, M48Z128Y, M48Z128V*Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data . . . . . . .17
Figure 16.SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline . . . . . . . . . . . . . .18
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data . . . . . .18
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 18. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
M48Z128, M48Z128Y, M48Z128V*
DESCRIPTIONThe M48Z128/Y/V ZEROPOWER® RAM is a
128 Kbit x 8 non-volatile static RAM organized
as131,072 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module. This
solution is available in two special packages to
provide a highly integrated battery backed-up
memory solution.
The M48Z128/Y/V is a non-volatile pin and func-
tion equivalent to any JEDEC standard 128K x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. The 32-pin,
600mil DIP Module houses the M48Z128/Y/V sili-
con with a long life lithium button cell in a single
package.
For surface-mount environments ST provides an
equivalent SMT solution consisting of a 28-pin,
330mil SOIC NVRAM SUPERVISOR (M40Z300/
W) and a 32-pin, (TSOP, 8 x 20mm) 1Mb
LPSRAM. Both 5V and 3V versions are available
(see Table 2., page 6).
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface-mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is “M4Zxx-BR00SH” (see
Table 17., page 19).
Table 1. Signal Names
5/21
M48Z128, M48Z128Y, M48Z128V*
M48Z128, M48Z128Y, M48Z128V*
Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution
Note: For pin connections, see individual data sheet for M48Z300/300W at . Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z128Y) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z128). Connect THS pin to VSS if 2.8V ≤ VPFD ≤ 3.0V (M48Z128V). SNAPHAT® Top ordered separately.
Table 2. Equivalent Surface-Mount (SMT) Solution
Note:1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/300W).
7/21
M48Z128, M48Z128Y, M48Z128V*
OPERATING MODES
The M48Z128/Y/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single VCC supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low VCC. As VCC falls
below the switchover voltage (VSO), the control cir-
cuitry connects the battery which maintains data
until valid power returns.
Table 3. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 11., page 14 for details.
READ Mode
The M48Z128/Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 1,048,576 locations in
the static storage array. Thus, the unique address
specified by the 17 address inputs defines which
one of the 131,072 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G (Output Enable) access times are also sat-
isfied. If the E and G access times are not met, val-
id data will be available after the later of Chip
Enable Access time (tELQV) or Output Enable Ac-
cess Time (tGLQV). The state of the eight three-
state Data I/O signals is controlled by E and G. If
the outputs are activated before tAVQV, the data
lines will be driven to an indeterminate state until
tAVQV. If the address inputs are changed while E
and G remain low, output data will remain valid for
Output Data Hold time (tAXQX) but will go indeter-
minate until the next Address Access.
M48Z128, M48Z128Y, M48Z128V*
9/21
M48Z128, M48Z128Y, M48Z128V*
WRITE Mode
The M48Z128/Y/V is in the WRITE Mode whenev-
er W and E are active. The start of a WRITE is ref-
erenced from the latter occurring falling edge of W
or E. A WRITE is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of
tEHAX from E or tWHAX from W prior to the initiation
of another READ or WRITE cycle. Data-in must be
valid tDVWH prior to the end of WRITE and remain
valid for tWHDX or tEHDX afterward. G should be
kept high during WRITE cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on E and G, a low on W will disable
the outputs tWLQZ after W falls.
M48Z128, M48Z128Y, M48Z128V*
Table 5. WRITE Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
11/21
M48Z128, M48Z128Y, M48Z128V*
Data Retention Mode
With valid VCC applied, the M48Z128/Y/V oper-
ates as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as “Don't care.”
If power fail detection occurs during a valid ac-
cess, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
tWP, write protection takes place. When VCC drops
below VSO, the control circuit switches power to
the internal energy source which preserves data.
The internal coin cell will maintain data in the
M48Z128/Y/V after the initial application of VCC for
an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to exter-
nal VCC. Write protection continues for tER after
VCC reaches VPFD to allow for processor stabiliza-
tion. After tER, normal RAM operation can resume.
For more information on Battery Storage Life refer
to the Application Note AN1012.
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (see Figure 10.) is
recommended in order to provide the needed fil-
tering.
