M48Z08-150PC1 ,16 Kbit 2Kb x 8 ZEROPOWER SRAMLogic DiagramDESCRIPTION®The M48Z02/12 ZEROPOWER RAM is a 2K x 8non-volatile static RAM which is pi ..
M48Z08-70PC1 ,16 Kbit 2Kb x 8 ZEROPOWER SRAMAbsolute Maximum Ratings" may cause permanent damage to the device. This is astress rating only and ..
M48Z12-150PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram Table 1. Signal NamesA0-A10 Address InputsVCCDQ0-DQ7 Data Inputs / Outputs11 8E Chip ..
M48Z12-200PC1 ,CMOS 2K x 8 zeropower SRAM, 200nsTABLE OF CONTENTSSUMMARY DESCRIPTION . . . 3Figure 2.
M48Z12-70PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . 4DC AND AC PARAMETERS . . 5Table 3. Operating and AC Measurem ..
M48Z12-70PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram . . 3Table 1. Signal Names . . . 3Figure 3. DIP Connections 3Fig ..
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M61538FP , 6-Channel Electronic Volume
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M61545AFP , Serial Data Control Dual Electronic Volume
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M48Z08-150PC1-M48Z08-70PC1
16 Kbit 2Kb x 8 ZEROPOWER SRAM
M48Z02
M48Z1216 Kbit (2Kb x 8) ZEROPOWER® SRAM
May 1999 1/12
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMA TIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48Z02: 4.50V ≤ VPFD ≤ 4.75V M48Z12: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2K x 8 SRAMs
DESCRIPTIONThe M48Z02/12 ZEROPOWER® RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220. special 24 pin 600mil DIP CAPHAT package
houses the M48Z02/12 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data and clock function-
ality for an accumulated time period of at least 10
years in the absence of power over the operating
temperature range.
Figure 1. Logic Diagram
Table 1. Signal Names
Notes:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings (1)
Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Table 3. Operating Modes
Figure 2. DIP Pin ConnectionsThe M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
DESCRIPTION (cont’d)2/12
M48Z02, M48Z12
Figure 4. AC Testing Load Circuit Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
Figure 3. Block Diagram
READ MODEThe M48Z02/12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
3/12
M48Z02, M48Z12
Notes:1. Outputs Deselected. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 6. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Notes:1. Effective capacitance measured with power supply at 5V. Outputs deselected
Table 5. Capacitance (1) (TA = 25 °C)
Note:1. All voltages referenced to VSS.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C or –40 to 85°C)
4/12
M48Z02, M48Z12
Notes:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 50 μs after
VCC passes VPFD (min). VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C or –40 to 85°C)
Figure 5. Power Down/Up Mode AC Waveforms
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systemsmay perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/12
M48Z02, M48Z12
Table 9. Read Mode AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Figure 6. Read Mode AC Waveforms
Note: Write Enable (W) = High.
6/12
M48Z02, M48Z12
