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M48T35-70PC1 |M48T3570PC1STN/a54avai256 KBIT (32KB X8) TIMEKEEPER SRAM
M48T35Y-70MH1 |M48T35Y70MH1STN/a516avai256 KBIT (32KB X8) TIMEKEEPER SRAM
M48T35Y-70MH6 |M48T35Y70MH6STN/a81avai256 KBIT (32KB X8) TIMEKEEPER SRAM
M48T35Y-70PC1 |M48T35Y70PC1STN/a894avai256 KBIT (32KB X8) TIMEKEEPER SRAM
M48T35Y-70PC1. |M48T35Y70PC1STN/a5avai256 KBIT (32KB X8) TIMEKEEPER SRAM


M48T35Y-70PC1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMM48T35M48T35Y® 5V, 256 Kbit (32 Kb x8) TIMEKEEPER SRAM
M48T35Y-70PC1. ,256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 28-pin PCDIP, CAPHAT™ Package . 1Figure 2. 28-pin ..
M48T37V-10MH1 ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMBlock Diagram . . 6OPERATION MODES . . . . . . . 7Table 2. Operating Modes 7RE ..
M48T37V-10MH1E ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMM48T37YM48T37V® 5.0 or 3.3V, 256 Kbit (32 Kbit x8) TIMEKEEPER SRAM
M48T37V-10MH1TR ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED ULTRA-LOW POWER SRAM, Figure 1. PackageREAL TIME CLOCK, POWER-FAIL CON ..
M48T37V-10MH6 ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMAbsolute Maximum Ratings . . . . . . . 202/29M48T37Y, M48T37VDC AND AC PARAMETERS . 21Tab ..
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61324SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61324SP , WIDE FREQUENCY BAND ANALOG SWITCH
M-614T , DC Line Fileters


M48T35-70PC1-M48T35Y-70MH1-M48T35Y-70MH6-M48T35Y-70PC1-M48T35Y-70PC1.
256 KBIT (32KB X8) TIMEKEEPER SRAM
1/26April 2004
M48T35
M48T35Y

5V, 256 Kbit (32 Kb x8) TIMEKEEPER® SRAM
FEATURES SUMMARY
INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT AND BATTERY BYTEWIDE™ RAM-LIKE CLOCK ACCESS BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48T35: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V M48T35Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT™ DIP
PACKAGE SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT®
HOUSING CONTAINING THE BATTERY
AND CRYSTAL SNAPHAT® HOUSING (BATTERY AND
CRYSTAL) IS REPLACEABLE PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 32 Kb x 8 SRAMs
M48T35, M48T35Y
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 8. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 12.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3/26
M48T35, M48T35Y

Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 15.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . .19
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . .19
Figure 16.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline.20
Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data . . . . .20
Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .21
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . .21
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .22
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .22
Figure 19.PMDIP28 – 28-pin Plastic DIP, Hybrid, Package Outline . . . . . . . . . . . . . . . . . . . . . . . .23
Table 16. PMDIP28 – 28-pin Plastic DIP, Hybrid, Package Mechanical Data. . . . . . . . . . . . . . . . .23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 18. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
M48T35, M48T35Y
SUMMARY DESCRIPTION

The M48T35/Y TIMEKEEPER® RAM is a 32Kb x
8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packag-
es to provide a highly integrated battery backed-up
memory and real time clock solution.
The M48T35/Y is a non-volatile pin and function
equivalent to any JEDEC standard 32Kb x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT houses the
M48T35/Y silicon with a quartz crystal and a long
life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery/crys-
tal packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package
(e.g., SNAPHAT) part number is “M4T28-
BR12SH” (see Table 18., page 24). Table 1. Signal Names
5/26
M48T35, M48T35Y
M48T35, M48T35Y
OPERATION MODES

As Figure 6., page 5 shows, the static memory ar-
ray and the quartz controlled clock oscillator of the
M48T35/Y are integrated on one silicon chip. The
two circuits are interconnected at the upper eight
memory locations to provide user accessible
BYTEWIDE clock information in the bytes with ad-
dresses 7FF8h-7FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automat-
ically. Byte 7FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T35/Y includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T35/Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low VCC. As VCC falls be-
low the Battery Back-up Switchover Voltage
(VSO), the control circuitry connects the battery
which maintains data and clock operation until val-
id power returns.
Table 2. Operating Modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 11., page 18 for details.
7/26
M48T35, M48T35Y
READ Mode

The M48T35/Y is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
Access time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV.
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (tAXQX) but will go indetermi-
nate until the next Address Access.
M48T35, M48T35Y
WRITE Mode

The M48T35/Y is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of
W or E. The addresses must be held valid through-
out the cycle. E or W must return high for a mini-
mum of tEHAX from Chip Enable or tWHAX from
WRITE Enable prior to the initiation of another
READ or WRITE Cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid fortWHDX afterward. G should be kept high during
WRITE Cycles to avoid bus contention; although,
if the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
9/26
M48T35, M48T35Y
Table 4. WRITE Mode AC Characteristics

Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). CL = 5pF. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
M48T35, M48T35Y
Data Retention Mode

With valid VCC applied, the M48T35/Y operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally power-fail deselect, write protecting itself
when VCC falls within the VPFD (max), VPFD (min)
window. All outputs become high impedance, and
all inputs are treated as “Don't care” (see Figure
14., page 18, Table 10., page 18, and Table
11., page 18).
Note: A power failure during a WRITE cycle may

corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T35/Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35/Y for
an accumulated period of at least 7 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to exter-
nal VCC. Write protection continues until VCC
reaches VPFD (min) plus trec (min). E should be
kept high as VCC rises past VPFD (min) to prevent
inadvertent WRITE Cycles prior to processor sta-
bilization. Normal RAM operation can resume trec
after VCC exceeds VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
11/26
M48T35, M48T35Y
CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER® registers (see Ta-
ble 5) should be halted before clock data is read to
prevent reading data in transition. The BiPORT™
TIMEKEEPER cells in the RAM array are only
data registers and not the actual clock counters,
so updating the registers can be halted without
disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register 7FF8h. As
long as a '1' remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Setting the Clock

Bit D7 of the Control Register 7FF8h is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
Bit, halts updates to the TIMEKEEPER® registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 5). Resetting the WRITE Bit to a '0' then
transfers the values of all time registers 7FF9h-
7FFFh to the actual TIMEKEEPER counters and
allows normal operation to resume. The FT Bit and
the bits marked as '0' in Table 5 must be written to
'0' to allow for normal TIMEKEEPER and RAM op-
eration. After the WRITE Bit is reset, the next clock
update will occur within one second.
See the Application Note AN923, “TIMEKEEPER®
Rolling Into the 21st Century” for information on
Century Rollover.
Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T35/Y is shipped
from STMicroelectronics with the STOP Bit set to
a '1.' When reset to a '0,' the M48T35/Y oscillator
starts within 1 second.
Table 5. Register Map

Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to '0' upon power
for normal operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
CEB = Century Enable Bit
CB = Century Bit
Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB.
M48T35, M48T35Y
Calibrating the Clock

The M48T35/Y is driven by a quartz-controlled os-
cillator with a nominal frequency of 32,768 Hz. The
devices are tested not to exceed 35 ppm (parts per
million) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month. With
the calibration bits properly set, the accuracy of
each M48T35/Y improves to better than +1/–2
ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10., page 13). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome “trim” capac-
itors. The M48T35/Y design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 11., page 13. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five calibration bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' in-
dicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768
Hz, each of the 31 increments in the Calibration
Byte would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T35/Y may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration Byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) Bit, the seventh-most significant bit in the Day
Register is set to a '1,' and D7 of the Seconds Reg-
ister is a '0' (Oscillator Running), DQ0 will toggle at
512 Hz during a READ of the Seconds Register.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10 (WR001010) to be loaded
into the Calibration Byte for correction.
Note: Setting or changing the
Calibration Byte
does not affect the Frequency Test output fre-
quency.
The FT Bit MUST be reset to '0' for normal clock
operations to resume. The FT Bit is automatically
Reset on power-down.
For more information on calibration, see Applica-
tion Note AN934, “TIMEKEEPER® Calibration.”
Century Bit

Bit D5 and D4 of Clock Register 1FFCh contain
the CENTURY ENABLE Bit (CEB) and the CEN-
TURY Bit (CB). Setting CEB to a '1' will cause CB
to toggle, either from a '0' to '1' or from '1' to '0' at
the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle.
Note: The WRITE Bit must be set in order to write

to the CENTURY Bit.
13/26
M48T35, M48T35Y
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