M48T251Y-70PM1 ,5.0 OR 3.3V, 4096K TIMEKEEPER%AE SRAM WITH PHANTOMBlock Diagram . . 5OPERATION MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M48T35-70PC1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. 28-pin PCDIP, CAPHAT™ PackageREAL TIM ..
M48T35AV-10MH1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMM48T35AYM48T35AV® 5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER SRAM
M48T35AV-10MH6 ,256 KBIT (32KB X8) TIMEKEEPER SRAMBlock Diagram . . 5OPERATION MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M48T35AV-10PC1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram Table 1. Signal NamesVCC A0-A14 Address InputsDQ0-DQ7 Data Inputs / Outputs15 8E Chip ..
M48T35Y-70MH1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram Table 1. Signal NamesV A0-A14 Address InputsCCDQ0-DQ7 Data Inputs / Outputs15 8E Chip ..
M61283FP , NTSC TV Signal Processor
M61283FP , NTSC TV Signal Processor
M61314SP , I2C BUS CONTROLLED VIDEO PRE-AMP FOR HIGH RESOLUTION COLOR DISPLAY
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M61323SP , WIDE FREQUENCY BAND ANALOG SWITCH
M48T251Y-70PM1
5.0 OR 3.3V, 4096K TIMEKEEPER%AE SRAM WITH PHANTOM
1/24February 2005
M48T251Y
M48T251V5.0 or 3.3V, 4096K TIMEKEEPER® SRAM with PHANTOM
FEATURES SUMMARY 5.0V OR 3.3V OPERATING VOLTAGE REAL TIME CLOCK KEEPS TRACK OF
TENTHS/HUNDREDTHS OF SECONDS,
SECONDS, MINUTES, HOURS, DAYS,
DATE OF THE MONTH, MONTHS, AND
YEARS AUTOMATIC LEAP YEAR CORRECTION
VALID UP TO THE YEAR 2100 AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT
VOLTAGES:
(VPFD = Power-fail Deselect Voltage): M48T251Y: 4.25V ≤ VPFD ≤ 4.50V M48T251V: 2.80V ≤ VPFD ≤ 2.97V FULL 10% VCC OPERATING RANGE OVER 10 YEARS’ DATA RETENTION IN
THE ABSENCE OF POWER WATCH FUNCTION IS TRANSPARENT TO
RAM OPERATION 512K x 8 NV SRAM DIRECTLY REPLACES
VOLATILE STATIC RAM OR EEPROM
M48T251Y, M48T251V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 32-pin, DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 5. Memory READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 6. Memory WRITE Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7. Memory WRITE Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Memory AC Characteristics, M48T251Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Memory AC Characteristics, M48T251V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 8. Comparison Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 5. Phantom Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 9. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 10.Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 11.Phantom Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 6. Phantom Clock AC Characteristics (M48T251Y). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 7. Phantom Clock AC Characteristics (M48T251V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 9. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 12.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 13.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3/24
M48T251Y, M48T251VTable 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 14.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . .21
Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . .21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 14. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
M48T251Y, M48T251V
SUMMARY DESCRIPTIONThe M48T251Y/V TIMEKEEPER® RAM is a
512Kbit x 8 non-volatile static RAM and real time
clock organized as 524,288 words by 8 bits. The
special DIP package provides a fully integrated
battery back-up memory and real time clock solu-
tion. In the event of power instability or absence, a
self-contained battery maintains the timekeeping
operation and provides power for a CMOS static
RAM. Control circuitry monitors VCC and invokes
write protection to prevent data corruption in the
memory and RTC.
The clock keeps track of tenths/hundredths of sec-
onds, seconds, minutes, hours, day, date, month,
and year information. The last day of the month is
automatically adjusted for months with less than
31 days, including leap year correction.
The clock operates in one of two formats: a 12-hour mode with an AM/PM indicator; a 24-hour mode
The M48T251Y/V is a 32-pin (PM) DIP module
that integrates the RTC, the battery, and SRAM in
one package.
The modules are shipped in plastic, anti-static
tubes (see Table 14., page 22).
Table 1. Signal Names
5/24
M48T251Y, M48T251V
M48T251Y, M48T251V
OPERATION MODES
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage See Table 12., page 20 for details.
READ
A READ cycle executes whenever WRITE Enable
(WE) is high and Chip Enable (CE) is low (see Fig-
ure 5.). The distinct address defined by the 19 ad-
dress inputs (A0-A18) specifies which of the 512K
bytes of data is to be accessed. Valid data will be
accessed by the eight data output drivers within
the specified Access Time (tACC) after the last ad-
dress input signal is stable, the CE and OE access
times, and their respective parameters are satis-
fied. When CE tACC and OE tACC are not satisfied,
then data access times must be measured from
the more recent CE and OE signals, with the limit-
ing parameter being tCO (for CE) or tOE (for OE) in-
stead of address access.
7/24
M48T251Y, M48T251V
WRITE
WRITE Mode (see Figure 6.) occurs whenever CE
and WE signals are low (after address inputs are
stable). The most recent falling edge of CE and
WE will determine when the WRITE cycle begins
(the earlier, rising edge of CE or WE determines
cycle termination). All address inputs must be kept
stable throughout the WRITE cycle. WE must be
high (inactive) for a minimum recovery time (tWR)
before a subsequent cycle is initiated. The OE
control signal should be kept high (inactive) during
the WRITE cycles to avoid bus contention. If CE
and OE are low (active), WE will disable the out-
puts for Output Data WRITE Time (tODW) from its
falling edge.
M48T251Y, M48T251V
9/24
M48T251Y, M48T251V
Table 3. Memory AC Characteristics, M48T251Y
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). These parameters are sampled with a 5 pF load are not 100% tested. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or
WE going high. tDH and tDS are measured from the earlier of CE or WE going high.
M48T251Y, M48T251V
Table 4. Memory AC Characteristics, M48T251V
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). These parameters are sampled with a 5 pF load are not 100% tested. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or
WE going high. tWR is a function of the latter occurring edge of WE or CE. tDH and tDS are measured from the earlier of CE or WE going high.
11/24
M48T251Y, M48T251V
Data Retention Mode
Data can be read or written only when VCC is
greater than VPFD. When VCC is below VPFD (the
point at which write protection occurs), the clock
registers and the SRAM are blocked from any ac-
cess. When VCC falls below the Battery Switch
Over threshold (VSO), the device is switched from
VCC to battery backup (VBAT). RTC operation and
SRAM data are maintained via battery backup un-
til power is stable. All control, data, and address
signals must be powered down when VCC is pow-
ered down.
The lithium power source is designed to provide
power for RTC activity as well as RTC and RAM
data retention when VCC is absent or unstable.
The capability of this source is sufficient to power
the device continuously for the life of the equip-
ment into which it has been installed. For specifi-
cation purposes, life expectancy is ten (10) years
at 25°C with the internal oscillator running without
VCC. Each unit is shipped with its energy source
disconnected, guaranteeing full energy capacity.
When VCC is first applied at a level greater than
VPFD, the energy source is enabled for battery
backup operation. The actual life expectancy will
be much longer if no battery energy is used (e.g.,
when VCC is present).
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is estab-
lished by pattern recognition of a serial bit-stream
of 64 bits which must be matched by executing 64
consecutive WRITE cycles containing the proper
data on DQ0.
All accesses which occur prior to recognition of the
64-bit pattern are directed to memory.
After recognition is established, the next 64 READ
or WRITE cycles either extract or update data in
the clock while disabling the memory.
Data transfer to and from the timekeeping function
is accomplished with a serial bit-stream under con-
trol of Chip Enable (CE), Output Enable (OE), and
WRITE Enable (WE). Initially, a READ cycle using
the CE and OE control of the clock starts the pat-
tern recognition sequence by moving the pointer to
the first bit of the 64-bit comparison register (see
Figure 8., page 12).
Next, 64 consecutive WRITE cycles are executed
using the CE and WE control of the device. These
64 WRITE cycles are used only to gain access to
the clock. Therefore, any address to the memory
is acceptable. However, the WRITE cycles gener-
ated to gain access to the Phantom Clock are also
writing data to a location in the mated RAM. The
preferred way to manage this requirement is to set
aside just one address location in RAM as a Phan-
tom Clock scratch pad.
When the first WRITE cycle is executed, it is com-
pared to Bit 1 of the 64-bit comparison register. If
a match is found, the pointer increments to the
next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not ad-
vance and all subsequent WRITE cycles are ig-
nored. If a READ cycle occurs at any time during
pattern recognition, the present sequence is abort-
ed and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all of the
bits in the comparison register have been
matched. With a correct match for 64-bits, the
Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The
next 64 cycles will cause the Phantom Clock to ei-
ther receive or transmit data on DQ0, depending
on the level of the OE pin or the WE pin. Cycles to
other locations outside the memory block can be
interleaved with CE cycles without interrupting the
pattern recognition sequence or data transfer se-
quence to the Phantom Clock.
M48T251Y, M48T251V
