M41T256YMT7TR ,256 Kbit 32K x8 SERIAL RTCElectrical Characteristics (Externally Supplied) . 20Figure 17.Power Down/Up Mode AC Waveforms ..
M41T315Y ,Serial Access Phantom RTC SupervisorElectrical Characteristics (Externally Supplied) . . 17Figure 13.Power Down/Up Mode AC Waveforms ..
M41T56 ,512 BIT (64B X 8) SERIAL ACCESS TIMEKEEPER SRAMElectrical Characteristics (Table 6.) . . . . 7OPERATION . . . . . . 82-Wire Bus Charac ..
M41T56M ,512 bit 64b x8 Serial Access TIMEKEEPER SRAMElectrical Characteristics . . . 16Figure 17.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M41T56M6 ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMElectrical Characteristics . . . 16Figure 17.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M41T56M6E ,512 Bit (64B X8) Serial Access TIMEKEEPER SRAMM41T56® 512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM
M5M5V108DFP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V108DFP-70H , 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M41T256YMT7TR
256 Kbit (32K X8) Serial RTC
1/27June 2004
M41T256Y256 Kbit (32K x8) Serial RTC
FEATURES SUMMARY 5V OPERATING VOLTAGE SERIAL INTERFACE SUPPORTS
EXTENDED I2 C BUS ADDRESSING
(400kHz) AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY POWER-FAIL DESELECT VOLTAGES: M41T256Y: VCC = 4.5 to 5.5V;
VPFD = 4.2 < VPFD < 4.5V COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, and YEAR PROGRAMMABLE SOFTWARE CLOCK
CALIBRATION 32,752 BYTES OF GENERAL PURPOSE
RAM MICROPROCESSOR POWER-ON RESET HOLDS MICROPROCESSOR IN RESET
UNTIL SUPPLY VOLTAGE REACHES
STABLE OPERATING LEVEL AUTOMATIC ADDRESS-INCREMENTING TAMPER INDICATION CIRCUIT WITH TIME-
STAMP SLEEP MODE FUNCTION PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT® TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
M41T256Y
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 44-pin, Hatless SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 44-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. 44-pin SOIC Connections (MT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. 44-pin SOIC (MH - SNAPHAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Stop data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 8. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 10.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 12.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 3. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Tamper Indication Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Tamper Event Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 14.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 15.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3/27
M41T256Y
Preferred Power-on/Battery Attach Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 4. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 6. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 16.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 9. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 17.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 18.SOH44 – 44-lead Plastic, Hatless, Small Package Outline. . . . . . . . . . . . . . . . . . . . . . .22
Table 11. SOH44 – 44-lead Plastic, Hatless, Small Package Mechanical Data . . . . . . . . . . . . . . .22
Figure 19.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline . . . . . . . . . . . . . .23
Table 12. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . .23
Figure 20.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal Outline . . . . . . . . . . . . . .24
Table 13. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data. . . . . .24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 15. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
M41T256Y
SUMMARY DESCRIPTIONThe M41T256Y Serial TIMEKEEPER® SRAM is a
low power 256 Kbit static CMOS SRAM organized
as 32K words by 8 bits. A built-in 32.768kHz oscil-
lator (external crystal controlled) and 8 bytes of the
SRAM (see Table 3., page 14) are used for the
clock/calendar function and are configured in bina-
ry coded decimal (BCD) format.
Addresses and data are transferred serially via a
two line, bi-directional I2 C interface. The built-in
address register is incremented automatically af-
ter each WRITE or READ data byte.
The M41T256Y has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
lithium button-cell supply when a power failure oc-
curs. Functions available to the user include a
non-volatile, time-of-day clock/calendar, and Pow-
er-on Reset. The eight clock address locations
contain the year, month, date, day, hour, minute,
second, and tenths/hundredths of seconds in 24-
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made automatically. The first clock address loca-
tion (7FF8h) stores the clock software calibration
settings as well as the Write Clock Bit.
The M41T256Y is supplied in a 44-lead SOIC
SNAPHAT® package (MH - which integrates both
crystal and battery in a single SNAPHAT top) or a
44-pin “hatless” SOIC (MT). The 44-pin, 330mil
SOIC provides sockets with gold-plated contacts
at both ends for direct connection to a separate
SNAPHAT housing containing the battery and
crystal. The unique design allows the SNAPHAT
battery/crystal package to be mounted on top of
the SOIC package after the completion of the sur-
face-mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion. The 44-pin
SOIC and crystal/battery packages are shipped
separately in plastic, anti-static tubes or in Tape &
Reel form. For the 44-lead SOIC, the battery/crys-
tal package (e.g., SNAPHAT) part number is
“M4Txx-BR12SH” (see Table 15., page 25).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium, button-cell battery.
Table 1. Signal NamesNote:1. For 44-pin SNAPHAT (MT) package only.
5/27
M41T256Y
Figure 4. 44-pin SOIC Connections (MT)Note: No Function (NF) must be tied to VSS.
Figure 5. 44-pin SOIC (MH - SNAPHAT)
M41T256Y
OPERATING MODESThe M41T256Y clock operates as a slave device
on the serial bus. Access is obtained by imple-
menting a start condition followed by the correct
slave address (D0h). The 256K bytes contained in
the device can then be accessed sequentially in
the following order:
0-7FEF = General Purpose RAM
7FF0-7FF6 = Reserved
7FF7h = Tenths/Hundredths Register
7FF8h = Control Register
7FF9h = Seconds Register
7FFAh = Minutes Register
7FFBh = Hour Register
7FFCh = Tamper/Day Register
7FFDh = Date Register
7FFEh = Month Register
7FFFh = Year Register
The M41T256Y clock continually monitors VCC for
an out-of tolerance condition. Should VCC fall be-
low VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from an out-of-tolerance system.
When VCC falls below VSO, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches VPFD
plus tREC.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus CharacteristicsThe bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one acknowledge clock pulse. This acknowl-
edge clock pulse is a low level put on the bus by
the receiver whereas the master generates an ex-
tra acknowledge related clock pulse. A slave re-
ceiver which is addressed is obliged to generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
7/27
M41T256Y
Figure 7. Serial Bus Data Transfer Sequence
Figure 8. Acknowledgement Sequence
M41T256Y
9/27
M41T256Y
READ ModeIn this mode the master reads the M41T256Y
slave after setting the slave address (see Figure
10., page 9). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the byte ad-
dresses A(0) and A(1) are written to the on-chip
address pointer (MSB of address byte A(0) is a
“Don’t care”). Next the START condition and slave
address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an acknowledge bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T256Y slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure
11., page 10).
Note: Address pointer will wrap around from max-imum address to minimum address if consecutive
READ or WRITE cycles are performed.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T256Y slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 12., page 10).
M41T256Y
11/27
M41T256Y
WRITE ModeIn this mode the master transmitter transmits to
the M41T256Y slave receiver. Bus protocol is
shown in Figure 13., page 11. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that byte addresses A(0) and A(1)
will follow and is to be written to the on-chip ad-
dress pointer (MSB of address byte A(0) is a
“Don’t care”).
The data byte to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge bit.
The M41T256Y slave receiver will send an ac-
knowledge bit to the master transmitter after it has
received the slave address (see Figure
10., page 9) and again after it has received each
address byte.
M41T256Y
Data Retention ModeWith valid VCC applied, the M41T256Y can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the
M41T256Y will automatically deselect, write pro-
tecting itself when VCC falls between VPFD (max)
and VPFD (min). This is accomplished by internally
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the external battery and the
clock registers and SRAM are maintained from the
attached battery supply.
All outputs become high impedance. On power up,
when VCC returns to a nominal value, write protec-
tion continues for tREC. The RST signal also re-
mains active during this time (see Figure
17., page 21).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Sleep ModeIn order to minimize the battery current draw while
in storage, the M41T256Y provides the user with a
battery “Sleep Mode,” which disconnects the RAM
memory array from the external Lithium battery
normally used to provide non-volatile operation in
the absence of VCC. This can significantly extend
the lifetime of the battery, when non-volatile oper-
ation is not needed.
Note: The Sleep Mode will remove power from theRAM array only and not affect the data retention of
the TIMEKEEPER Registers (7FF0h through
7FFFh - this includes the Calibration Register).
The Sleep Mode (SLP) Bit located in register
7FF8h (D6), must be set to a '1' by the user while
the device is powered by VCC. This will “arm” the
Sleep Mode latch, but not actually disconnect the
RAM array from power until the next power-down
cycle. This protects the user from immediate data
loss in the event he inadvertently sets the SLP Bit.
Once VCC falls below VSO (VBAT), the Sleep Mode
circuit will be engaged and the RAM array will be
isolated from the battery, resulting in both a lower
battery current, and a loss of RAM data.
Note: Upon initial battery attach or initial power
application without the battery, the state of the
SLP Bit will be undetermined. Therefore, the SLP
Bit should be initialized to '0' by the user.
Additional current reduction can be achieved by
setting the STOP (ST) Bit in register 7FF9h (D7),
turning off the clock oscillator. This combination
will result in the longest possible battery life, but
also loss of time and data. When the device is
again powered-up, the user should first read the
SLP Bit to determine if the device is currently in
Sleep Mode, then reset the bit to '0' in order to dis-
able the Sleep Mode (this will NOT be automatical-
ly taken care of during the power-up).
Note: See AN1570, “M41T256Y Sleep ModeFunction” for more information on Sleep Mode and
battery lifetimes.
13/27
M41T256Y
CLOCK OPERATIONYear, Month, and Date are contained in the last
three registers of the TIMEKEEPER® Register
Map (see Table 3., page 14). Bits D0 through D2
of the next register contain the Day (day of week).
Finally, there are the registers containing the Sec-
onds, Minutes, and Hours, respectively. The first
clock register is the Control Register (this is de-
scribed in the Clock Calibration section).
The nine Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 7FF8h) may be accessed
independently. Provision has been made to as-
sure that a clock update does not occur while any
of the nine clock addresses are being read. If a
clock address is being read, an update of the clock
registers will be halted. This will prevent a transi-
tion of data during the read.
Reading the ClockThe nine byte clock register (see Table
3., page 14) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. The system-to-user trans-
fer of clock data will be halted whenever the ad-
dress being read is a clock address (7FF9h to
7FFFh). The update will resume either due to a
Stop Condition or when the pointer increments to
a RAM address.
This prevents reading data in transition. The
TIMEKEEPER® cells in the Register Map are only
data registers and not actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Setting the ClockBit D7 of the Control Register (7FF8h) is the Write
Clock Bit. Setting the Write Clock Bit to a '1' will al-
low the user to write the desired Day, Date, and
Time data in 24-hour BCD format. Resetting the
Write Clock Bit to a '0' then transfers the values of
all time registers (7FF8h-7FFFh) to the actual
clock counters and resets the internal divider (or
clock) chain.
Note: The Tenths/Hundredths of Seconds Regis-ter will automatically be reset to zero when the
WRITE Clock Bit is set.
Other register bits such as FT, TEB, and ST may
be written without setting the WC Bit. In such cas-
es, the clock data will be undisturbed and will re-
tain their previous values.
Stopping and Starting the OscillatorThe oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The Stop Bit
(ST) is the most significant bit of the Seconds Reg-
ister. Setting it to '1' stops the oscillator. Setting it
to '0' restarts the oscillator in approximately one
second.
M41T256Y
Table 3. TIMEKEEPER® Register MapKeys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
WC = Write Clock Bit
X = '1' or '0'
BL = Battery Low Flag (Read only bit)
TB = Tamper Bit (Read only bit)
TEB = Tamper Enable Bit
0 = Must be set to '0'
SLP = Sleep Mode Bit
Note: 7FF0h through 7FF6h are invalid addresses and when read will return arbitrary data.
