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Partno Mfg Dc Qty AvailableDescript
M41T00M6STN/a4707avaiSerial Access TIMEKEEPER
M41T00M6ESTN/a2180avaiSerial Access TIMEKEEPER
M41T00M6FSTMN/a4864avaiSerial Access TIMEKEEPER
M41T00M6TRSTN/a1414avaiSerial Access TIMEKEEPER


M41T00M6F ,Serial Access TIMEKEEPERLogic Diagram Table 1. Signal NamesOSCI Oscillator InputV VCC BATOCSO Oscillator OutputFrequency Te ..
M41T00M6TR ,Serial Access TIMEKEEPERFEATURES SUMMARY■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE Figure 1. Package■ COUNTERS FOR SECONDS, MINU ..
M41T00S ,Serial Access Real-Time ClockBlock Diagram . . 5OPERATION . . . . . . 62-Wire Bus Characteristics . . . . . ..
M41T00S ,Serial Access Real-Time ClockAbsolute Maximum Ratings . . . . . . . 15DC AND AC PARAMETERS . 16Table 5. Operating and ..
M41T00SM6E ,Serial Access Real-Time ClockElectrical Characteristics . . . 17Figure 14.Power Down/Up Mode AC Waveforms . . . . . . 1 ..
M41T00SM6E ,Serial Access Real-Time ClockFEATURES SUMMARY■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE Figure 1. Packages■ COUNTERS FOR SECONDS, MIN ..
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08AJ-10 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-12 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R08J-15 , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M54R16AJ-10 , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M5M54R16AJ-12 , 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM


M41T00M6-M41T00M6E-M41T00M6F-M41T00M6TR
Serial Access TIMEKEEPER
1/21June 2004
M41T00

Serial Access TIMEKEEPER®
FEATURES SUMMARY
2.0 TO 5.5V CLOCK OPERATING VOLTAGE COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS, AND
CENTURY YEAR 2000 COMPLIANT SOFTWARE CLOCK CALIBRATION AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY I2 C BUS COMPATIBLE ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1µA LOW OPERATING CURRENT OF 300µA BATTERY OR SUPER-CAP BACK-UP BATTERY BACK-UP NOT RECOMMENDED
FOR 3.0V APPLICATIONS (CAPACITOR
BACK-UP ONLY) OPERATING TEMPERATURE OF –40 TO
85°C AUTOMATIC LEAP YEAR COMPENSATION SPECIAL SOFTWARE PROGRAMMABLE
OUTPUT
M41T00
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Stop data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 6. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 8. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 10.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 11.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 3. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 12.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 13.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 14.AC Testing Input/Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/21
M41T00

Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 16.SO8 – 8-lead Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. SO8 – 8-lead Plastic Small Outline Package Mechanical Data. . . . . . . . . . . . . . . . . . . .18
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
M41T00
SUMMARY DESCRIPTION

The M41T00 TIMEKEEPER® RAM is a low power
Serial TIMEKEEPER with a built-in 32.768kHz os-
cillator (external crystal controlled). Eight bytes of
the RAM are used for the clock/calendar function
and are configured in binary coded decimal (BCD)
format. Addresses and data are transferred serial-
ly via a two-line bi-directional bus. The built-in ad-
dress register is incremented automatically after
each WRITE or READ data byte.
The M41T00 clock has a built-in power sense cir-
cuit which detects power failures and automatical-
ly switches to the battery supply during power
failures. The energy needed to sustain the RAM
and clock operations can be supplied from a small
lithium coin cell.
Typical data retention time is in excess of 5 years
with a 50mA/h 3V lithium cell (see Data Retention
Mode, page 10 for AC/DC Characteristics). The
M41T00 is supplied in 8 lead Plastic Small Outline
package.
Table 1. Signal Names
5/21
M41T00
M41T00
OPERATION

The M41T00 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 8 bytes contained in the device
can then be accessed sequentially in the following
order: Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Years Register Control Register
The M41T00 clock continually monitors VCC for an
out of tolerance condition. Should VCC fall below
VSO, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from an out of tolerance system. When VCC
falls below VSO, the device automatically switches
over to the battery and powers down into an ultra
low current mode of operation to conserve battery
life. Upon power-up, the device switches from bat-
tery to VCC at VSO and recognizes inputs.
2-Wire Bus Characteristics

This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes
in the data line while the clock line is High will be
interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy.
Both data and clock lines remain
High.
Start data transfer.
A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer.
A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data valid.
The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition, a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The de-
vices that are controlled by the master are called
“slaves”.
Acknowledge.
Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver, whereas
the master generates an extra acknowledge relat-
ed clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
7/21
M41T00
Figure 5. Serial Bus Data Transfer Sequence
Figure 6. Acknowledgement Sequence
M41T00
Figure 7. Bus Timing Requirements Sequence

Note: P = STOP and S = START
Table 2. AC Characteristics

Note:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
9/21
M41T00
READ Mode

In this mode, the master reads the M41T00 slave
after setting the slave address (see Figure 8). Fol-
lowing the WRITE Mode Control Bit (R/W = 0) and
the Acknowledge Bit, the word address An is writ-
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ Mode Control Bit (R/W =1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Bit. The
M41T00 slave transmitter will now place the data
byte at address An+1 on the bus. The master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ Mode may also be implement-
ed, whereby the master reads the M41T00 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 10., page 10).
Figure 8. Slave Address Location
Figure 9. READ Mode Sequence
M41T00
Figure 10. Alternate READ Mode Sequence
WRITE Mode

In this mode the master transmitter transmits to
the M41T00 slave receiver. Bus protocol is shown
in Figure 11., page 10. Following the START con-
dition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address An will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The M41T00
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has received the
word address and each data byte (see Figure 8).
Data Retention Mode

With valid VCC applied, the M41T00 can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the
M41T00 will automatically deselect, write protect-
ing itself when VCC falls (see Figure 15., page 17).
11/21
M41T00
CLOCK OPERATION

The eight byte clock register (see Table 3) is used
to both set the clock and to read the date and time
from the clock, in a binary coded decimal format.
Seconds, Minutes, and Hours are contained within
the first three registers. Bits D6 and D7 of clock
register 2 (Hours Register) contain the CENTURY
ENABLE Bit (CEB) and the CENTURY Bit (CB).
Setting CEB to a '1' will cause CB to toggle, either
from '0' to '1' or from '1' to '0' at the turn of the cen-
tury (depending upon its initial state). If CEB is set
to a '0', CB will not toggle. Bits D0 through D2 of
register 3 contain the Day (day of week). Registers
4, 5 and 6 contain the Date (day of month), Month
and Years. The final register is the Control Regis-
ter (this is described in the Clock Calibration sec-
tion). Bit D7 of register 0 contains the STOP Bit
(ST). Setting this bit to a '1' will cause the oscillator
to stop. If the device is expected to spend a signif-
icant amount of time on the shelf, the oscillator
may be stopped to reduce current drain. When re-
set to a '0' the oscillator restarts within one second.
Note: In order to guarantee oscillator start-up after

the initial power-up, set the ST Bit to a '1,' then re-
set this bit to a '0.' This sequence enables a “kick
start” circuit which aids the oscillator start-up dur-
ing worst case conditions of voltage and tempera-
ture.
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Control
Register (Address location 7) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock reg-
isters will be delayed by 250ms to allow the READ
to be completed before the update occurs. This
will prevent a transition of data during the READ.
Note: This 250ms delay affects only the clock reg-

ister update and does not alter the actual clock
time.
Table 3. Register Map

Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
ST = STOP Bit
OUT = Output level
X = Don’t care
CEB = Century Enable Bit
CB = Century Bit
Note:1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).
When CEB is set to '0', CB will not toggle.
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