M41ST95WMX6 ,5.0 or 3.0V, 512 Bit (64 Bit x8) Serial RTC (SPI) SRAM and NVRAM SupervisorAbsolute Maximum Ratings . . . . . . . 25DC AND AC PARAMETERS . 26Table 11. DC and AC Mea ..
M41T0 ,SERIAL REAL-TIME CLOCKElectrical Characteristics (Table 6.) . . . . 7OPERATION . . . . . . 82-Wire Bus Charac ..
M41T00 ,SERIAL ACCESS TIMEKEEPERFEATURES SUMMARY
M41ST95WMX6
5.0 or 3.0V, 512 Bit (64 Bit x8) Serial RTC (SPI) SRAM and NVRAM Supervisor
1/35September 2004
M41ST95Y*
M41ST95W5.0 or 3.0V, 512 bit (64 bit x8) Serial RTC
(SPI) SRAM and NVRAM Supervisor
* Contact Local Sales Office
FEATURES SUMMARY 5.0 OR 3.0V OPERATING VOLTAGE SERIAL PERIPHERAL INTERFACE (SPI) NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT
VOLTAGES: M41ST95Y*: VCC = 4.5 to 5.5V
4.20V ≤ VPFD ≤ 4.50V M41ST95W: VCC = 2.7 to 3.6V
2.55V ≤ VPFD ≤ 24.70V 1.25V REFERENCE (FOR PFI/PFO) COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY 44 BYTES OF GENERAL PURPOSE RAM PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING
BATTERY BACK-UP MODE) WATCHDOG TIMER MICROPROCESSOR POWER-ON RESET BATTERY LOW FLAG 32kHz FREQUENCY OUTPUT AVAILABLE
IMMEDIATELY UPON POWER-ON (300mil
SO28 MX PACKAGE ONLY) AUTOMATICALLY RECORDS TIME WHEN
POWER-FAIL OCCURS ULTRA-LOW BATTERY SUPPLY CURRENT
OF 550nA (MAX) PACKAGING INCLUDES A 28-LEAD SOIC
and SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY and
CRYSTAL
M41ST95Y*, M41ST95W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. 28-pin SOIC Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. 28-pin (300mil) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 5. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SPI Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 2. Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 8. Data and Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 9. Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10.Output Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 11.WRITE Cycle Timing: RTC and External SRAM Control Signals . . . . . . . . . . . . . . . . . .11
Table 3. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
READ and WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 12.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 4. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 14.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 5. Alarm Repeat Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15.Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 6. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Full-time F32k Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
(Available only in 28-pin, 300mil SOIC (MX) package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Reset Input (RSTIN1 and RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 16.RSTIN1 and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3/35
M41ST95Y*, M41ST95WTable 7. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 17.Power-Fail Comparator Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Preferred Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 8. tREC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 9. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 18.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 19.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 10. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 20.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 21.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 14. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Figure 22.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline. . . . . . . .29
Table 15. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 29
Figure 23.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . .30
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data30
Figure 24.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . .31
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . .31
Figure 25.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline . . . . . . . .32
Table 18. SOX28 – 28-lead Plastic Small, 300mils, Embedded Crystal, Package Mech. Data . . .32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 20. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
M41ST95Y*, M41ST95W
SUMMARY DESCRIPTIONThe M41ST95Y/W Serial TIMEKEEPER® SRAM
is a low power, 512-bit static CMOS SRAM orga-
nized as 64 words by 8 bits. A built-in 32,768Hz
oscillator (external crystal controlled) and 8 bytes
of the SRAM (see Table 4., page 16) are used for
the clock/calendar function and are configured in
binary coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/con-
trol of Alarm, Watchdog and Square Wave func-
tions. Addresses and data are transferred serially
via a serial SPI interface. The built-in address reg-
ister is incremented automatically after each
WRITE or READ data byte. The M41ST95Y/W
has a built-in power sense circuit which detects
power failures and automatically switches to the
battery supply when a power failure occurs. The
energy needed to sustain the SRAM and clock op-
erations can be supplied by a small lithium button-
cell supply when a power failure occurs. Functions
available to the user include a non-volatile, time-
of-day clock/calendar, Alarm interrupts, Watchdog
Timer and programmable Square Wave output.
Other features include a Power-On Reset as well
as two additional debounced inputs (RSTIN1 and
RSTIN2) which can also generate an output Reset
(RST). The eight clock address locations contain
the century, year, month, date, day, hour, minute,
second and tenths/hundredths of a second in 24
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made automatically.
The M41ST95Y/W is supplied in a 28-lead SOIC
SNAPHAT® (MH) package (which integrates both
crystal and battery in a single SNAPHAT top), or a
28-pin, 300mil SOIC package (MX) which includes
an embedded 32kHz crystal.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SNAPHAT SOIC and battery/crystal packag-
es are shipped separately in plastic anti-static
tubes or in Tape & Reel form. For the 28-lead SO-
IC, the battery/crystal package (e.g., SNAPHAT)
part number is “M4TXX-BR12SH” (see Table
20., page 33).
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile op-
eration.
5/35
M41ST95Y*, M41ST95W
Table 1. Signal NamesNote:1. For SOX28 package only. Available only in 28-pin, 300mil SOIC (MX) package.
M41ST95Y*, M41ST95W
7/35
M41ST95Y*, M41ST95W
Figure 6. Block DiagramNote:1. Open Drain Output Available only in 28-pin, 300mil SOIC (MX) package.
M41ST95Y*, M41ST95W
Figure 7. Hardware HookupNote:1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU.
9/35
M41ST95Y*, M41ST95W
OPERATIONThe M41ST95Y/W clock operates as a slave de-
vice on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI
bus compatible. The bus signals are SCL, SDI and
SDO (see Table 1., page 5 and Figure 7., page8).
The device is selected when the Chip Enable input
(E) is held low. All instructions, addresses and
data are shifted serially in and out of the chip. The
most significant bit is presented first, with the data
input (SDI) sampled on the first rising edge of the
clock (SCL) after the Chip Enable (E) goes low.
The 64 bytes contained in the device can then be
accessed sequentially in the following order: Tenths/Hundredths of a Second Register Seconds Register Minutes Register Century/Hours Register Day Register Date Register Month Register Year Register Control Register
10. Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20. Square Wave Register
21 - 64.User RAM
The M41ST95Y/W clock continually monitors VCC
for an out-of tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD (min) plus tREC (min). For more information
on Battery Storage Life refer to Application Note
AN1012.
SPI Bus CharacteristicsThe Serial Peripheral interface (SPI) bus is intend-
ed for synchronous communication between dif-
ferent ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41ST95Y/W) devices.
The SCL input, which is generated by the micro-
controller, is active only during address and data
transfer to any device on the SPI bus (see Figure
7., page8).
The M41ST95Y/W can be driven by a microcon-
troller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2., page 10 and Fig-
ure 8., page 10).
There is one clock for each bit transferred. Ad-
dress and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).
M41ST95Y*, M41ST95W
Signal Description
Serial Data Output (SDO). The output pin is
used to transfer data serially out of the Memory.
Data is shifted out on the falling edge of the serial
clock.
Serial Data Input (SDI). The input pin is used to
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each re-
ceived this way. Input is latched on the rising edge
of the serial clock.
Serial Clock (SCL). The serial clock provides the
timing for the serial interface (as shown in Figure
9., page 11 and Figure 10., page 11). The W/R
Bit, addresses, or data are latched, from the input
pin, on the rising edge of the clock input. The out-
put data on the SDO pin changes state after the
falling edge of the clock input.
The M41ST95Y/W can be driven by a microcon-
troller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2 and Figure 8).
Chip Enable (E). When E is high, the memory
device is deselected, and the SDO output pin is
held in its high impedance state.
After power-on, a high-to-low transition on E is re-
quired prior to the start of any operation.
11/35
M41ST95Y*, M41ST95W
M41ST95Y*, M41ST95W
Table 3. AC CharacteristicsNote:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted). tCH + tCL ≥ 1/fSCL Value guaranteed by design, not 100% tested in production.
13/35
M41ST95Y*, M41ST95W
READ and WRITE CyclesAddress and data are shifted MSB first into the Se-
rial Data Input (SDI) and out of the Serial Data
Output (SDO). Any data transfer considers the first
bit to define whether a READ or WRITE will occur.
This is followed by seven bits defining the address
to be read or written. Data is transferred out of the
SDO for a READ operation and into the SDI for a
WRITE operation. The address is always the sec-
ond through the eighth bit written after the Enable
(E) pin goes low. If the first bit is a '1,' one or more
WRITE cycles will occur. If the first bit is a '0,' one
or more READ cycles will occur (see Figure 12
and Figure 13., page 14).
Data transfers can occur one byte at a time or in
multiple byte burst mode, during which the ad-
dress pointer will be automatically incremented.
For a single byte transfer, one byte is read or writ-
ten and then E is driven high. For a multiple byte
transfer all that is required is that E continue to re-
main low. Under this condition, the address pointer
will continue to increment as stated previously. In-
crementing will continue until the device is dese-
lected by taking E high. The address will wrap to
00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). Although the clock contin-
ues to maintain the correct time, this will prevent
updates of time and date during either a READ or
WRITE of these address locations by the user.
The update will resume either due to a deselect
condition or when the pointer increments to an
non-clock or RAM address (08h to 3Fh).
Note: This is true both in READ and WRITE mode.
M41ST95Y*, M41ST95WWith valid VCC applied, the M41ST95Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST95Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when VCC falls between VPFD(max) and
VPFD(min). This is accomplished by internally in-
hibiting access to the clock registers. At this time,
the Reset pin (RST) is driven active and will re-
main active until VCC returns to nominal levels. Ex-
ternal RAM access is inhibited in a similar manner
by forcing ECON to a high level. This level is within
0.2 volts of the VBAT. ECON will remain at this level
as long as VCC remains at an out-of-tolerance con-
dition. When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the SNAPHAT® battery, and
the clock registers and external SRAM are main-
tained from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100 µA of current to the at-
tached memory with less than 0.3 volts drop under
this condition. On power up, when VCC returns to
a nominal value, write protection continues for
tREC by inhibiting ECON. The RST signal also re-
mains active during this time (see Figure
21., page 28).
Note: Most low power SRAMs on the market to-day can be used with the M41ST95Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use.
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M41ST95Y/W
and SRAMs to be “Don’t Care” once VCC falls be-
low VPFD(min). The SRAM should also guarantee
data retention down to VCC = 2.0 volts. The chip
enable access time must be sufficient to meet the
system needs with the chip enable output propa-
gation delays included. If the SRAM includes a
second chip enable pin (E2), this pin should be
tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST95Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT® of your choice
can then be divided by this current to determine
the amount of data retention available (see 20).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
15/35
M41ST95Y*, M41ST95W
CLOCK OPERATIONThe eight byte clock register (see Table
4., page 16) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Tenths/Hundredths of Sec-
onds, Seconds, Minutes, and Hours are contained
within the first four registers.
Note: The Tenths/Hundredths of Seconds cannotbe written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h con-
tains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock ad-
dress is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Power-down Time-StampWhen a power failure occurs, the Halt Update Bit
(HT) will automatically be set to a '1.' This will pre-
vent the clock from updating the clock registers,
and will allow the user to read the exact time of the
power-down event. Resetting the HT Bit to a '0' will
allow the clock to update the clock registers with
the current time.
TIMEKEEPER® RegistersThe M41ST95Y/W offers 20 internal registers
which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data (see Table
4., page 16). These registers are memory loca-
tions which contain external (user accessible) and
internal copies of the data (usually referred to as
BiPORT™ TIMEKEEPER cells). The external cop-
ies are independent of internal functions except
that they are updated periodically by the simulta-
neous transfer of the incremented internal copy.
The internal divider (or clock) chain will be reset
upon the completion of a WRITE to any clock ad-
dress.
The system-to-user transfer of clock data will be
halted whenever the clock addresses (00h to 07h)
are being written. The update will resume either
due to a deselect condition or when the pointer in-
crements to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary format.
M41ST95Y*, M41ST95W
Table 4. TIMEKEEPER® Register MapKeys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
TR = tREC Bit
17/35
M41ST95Y*, M41ST95W
Calibrating the ClockThe M41ST95Y/W is driven by a quartz-controlled
oscillator with a nominal frequency of 32,768Hz.
Uncalibrated clock accuracy will not exceed ±35
ppm (parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than ±2 ppm
at 25°C.
The oscillation rate of crystals changes with tem-
perature (see Figure 18., page 24). Therefore, the
M41ST95Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure
19., page 24. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration Bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register (8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST95Y/W may re-
quire.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that ac-
cesses the Calibration Byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop Bit (ST, D7 of 1h) is '0,' the Fre-
quency Test Bit (FT, D6 of 8h) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of Ah) is '0,' and the Watch-
dog Steering Bit (WDS, D7 of 9h) is '1' or the
Watchdog Register (9h = 0) is reset.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor for proper opera-
tion. A 500 to 10kΩ resistor is recommended in or-
der to control the rise time. The FT Bit is cleared
on power-down.
Setting Alarm Clock RegistersAddress locations 0Ah-0Eh contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M41ST95Y/W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 5., page 18 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT/OUT pin.
Note: If the address pointer is allowed to incre-
ment to the Flag Register address, an alarm con-
dition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
dress.
It should also be noted that if the last address writ-
ten is the “Alarm Seconds,” the address pointer
will increment to the Flag address, causing this sit-
uation to occur.
M41ST95Y*, M41ST95WTo disable the alarm, write '0' to the Alarm Date
Register and to RPT1-5. The IRQ/FT/OUT output
is cleared by a READ to the Flags Register as
shown in Figure 14. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Bat-
tery Back-up Mode Enable) and AFE are set.
The ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST95Y/W was in the de-
select mode during power-up. Figure 15., page19
illustrates the back-up mode alarm timing.
